projects / thirdparty / kernel / stable-queue.git / blame
| Commit | Line | Data |
|---|---|---|
| 2bbc3dc8 GKH |
1 | From 96e5d31244c5542f5b2ea81d76f14ba4b8a7d440 Mon Sep 17 00:00:00 2001 |
| 2 | From: George Cherian <george.cherian@ti.com> | |
| 3 | Date: Fri, 13 Feb 2015 10:13:24 +0530 | |
| 4 | Subject: usb: dwc3: dwc3-omap: Fix disable IRQ | |
| 5 | ||
| 6 | From: George Cherian <george.cherian@ti.com> | |
| 7 | ||
| 8 | commit 96e5d31244c5542f5b2ea81d76f14ba4b8a7d440 upstream. | |
| 9 | ||
| 10 | In the wrapper the IRQ disable should be done by writing 1's to the | |
| 11 | IRQ*_CLR register. Existing code is broken because it instead writes | |
| 12 | zeros to IRQ*_SET register. | |
| 13 | ||
| 14 | Fix this by adding functions dwc3_omap_write_irqmisc_clr() and | |
| 15 | dwc3_omap_write_irq0_clr() which do the right thing. | |
| 16 | ||
| 17 | Fixes: 72246da40f37 ("usb: Introduce DesignWare USB3 DRD Driver") | |
| 18 | Signed-off-by: George Cherian <george.cherian@ti.com> | |
| 19 | Signed-off-by: Felipe Balbi <balbi@ti.com> | |
| 20 | Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> | |
| 21 | ||
| 22 | --- | |
| 23 | drivers/usb/dwc3/dwc3-omap.c | 30 ++++++++++++++++++++++++++++-- | |
| 24 | 1 file changed, 28 insertions(+), 2 deletions(-) | |
| 25 | ||
| 26 | --- a/drivers/usb/dwc3/dwc3-omap.c | |
| 27 | +++ b/drivers/usb/dwc3/dwc3-omap.c | |
| 28 | @@ -205,6 +205,18 @@ static void dwc3_omap_write_irq0_set(str | |
| 29 | omap->irq0_offset, value); | |
| 30 | } | |
| 31 | ||
| 32 | +static void dwc3_omap_write_irqmisc_clr(struct dwc3_omap *omap, u32 value) | |
| 33 | +{ | |
| 34 | + dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_MISC + | |
| 35 | + omap->irqmisc_offset, value); | |
| 36 | +} | |
| 37 | + | |
| 38 | +static void dwc3_omap_write_irq0_clr(struct dwc3_omap *omap, u32 value) | |
| 39 | +{ | |
| 40 | + dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_0 - | |
| 41 | + omap->irq0_offset, value); | |
| 42 | +} | |
| 43 | + | |
| 44 | static void dwc3_omap_set_mailbox(struct dwc3_omap *omap, | |
| 45 | enum omap_dwc3_vbus_id_status status) | |
| 46 | { | |
| 47 | @@ -345,9 +357,23 @@ static void dwc3_omap_enable_irqs(struct | |
| 48 | ||
| 49 | static void dwc3_omap_disable_irqs(struct dwc3_omap *omap) | |
| 50 | { | |
| 51 | + u32 reg; | |
| 52 | + | |
| 53 | /* disable all IRQs */ | |
| 54 | - dwc3_omap_write_irqmisc_set(omap, 0x00); | |
| 55 | - dwc3_omap_write_irq0_set(omap, 0x00); | |
| 56 | + reg = USBOTGSS_IRQO_COREIRQ_ST; | |
| 57 | + dwc3_omap_write_irq0_clr(omap, reg); | |
| 58 | + | |
| 59 | + reg = (USBOTGSS_IRQMISC_OEVT | | |
| 60 | + USBOTGSS_IRQMISC_DRVVBUS_RISE | | |
| 61 | + USBOTGSS_IRQMISC_CHRGVBUS_RISE | | |
| 62 | + USBOTGSS_IRQMISC_DISCHRGVBUS_RISE | | |
| 63 | + USBOTGSS_IRQMISC_IDPULLUP_RISE | | |
| 64 | + USBOTGSS_IRQMISC_DRVVBUS_FALL | | |
| 65 | + USBOTGSS_IRQMISC_CHRGVBUS_FALL | | |
| 66 | + USBOTGSS_IRQMISC_DISCHRGVBUS_FALL | | |
| 67 | + USBOTGSS_IRQMISC_IDPULLUP_FALL); | |
| 68 | + | |
| 69 | + dwc3_omap_write_irqmisc_clr(omap, reg); | |
| 70 | } | |
| 71 | ||
| 72 | static u64 dwc3_omap_dma_mask = DMA_BIT_MASK(32); |