projects / thirdparty / kernel / stable-queue.git / blame
| Commit | Line | Data |
|---|---|---|
| b7eef177 GKH |
1 | From 517e6341fa123ec3a2f9ea78ad547be910529881 Mon Sep 17 00:00:00 2001 |
| 2 | From: Peter Zijlstra <peterz@infradead.org> | |
| 3 | Date: Sat, 11 Apr 2015 12:16:22 +0200 | |
| 4 | Subject: perf/x86/intel: Fix Core2,Atom,NHM,WSM cycles:pp events | |
| 5 | ||
| 6 | From: Peter Zijlstra <peterz@infradead.org> | |
| 7 | ||
| 8 | commit 517e6341fa123ec3a2f9ea78ad547be910529881 upstream. | |
| 9 | ||
| 10 | Ingo reported that cycles:pp didn't work for him on some machines. | |
| 11 | ||
| 12 | It turns out that in this commit: | |
| 13 | ||
| 14 | af4bdcf675cf perf/x86/intel: Disallow flags for most Core2/Atom/Nehalem/Westmere events | |
| 15 | ||
| 16 | Andi forgot to explicitly allow that event when he | |
| 17 | disabled event flags for PEBS on those uarchs. | |
| 18 | ||
| 19 | Reported-by: Ingo Molnar <mingo@kernel.org> | |
| 20 | Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> | |
| 21 | Cc: Arnaldo Carvalho de Melo <acme@redhat.com> | |
| 22 | Cc: Jiri Olsa <jolsa@redhat.com> | |
| 23 | Cc: Linus Torvalds <torvalds@linux-foundation.org> | |
| 24 | Cc: Peter Zijlstra <peterz@infradead.org> | |
| 25 | Fixes: af4bdcf675cf ("perf/x86/intel: Disallow flags for most Core2/Atom/Nehalem/Westmere events") | |
| 26 | Signed-off-by: Ingo Molnar <mingo@kernel.org> | |
| 27 | Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> | |
| 28 | ||
| 29 | --- | |
| 30 | arch/x86/kernel/cpu/perf_event_intel_ds.c | 8 ++++++++ | |
| 31 | 1 file changed, 8 insertions(+) | |
| 32 | ||
| 33 | --- a/arch/x86/kernel/cpu/perf_event_intel_ds.c | |
| 34 | +++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c | |
| 35 | @@ -557,6 +557,8 @@ struct event_constraint intel_core2_pebs | |
| 36 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */ | |
| 37 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */ | |
| 38 | INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */ | |
| 39 | + /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */ | |
| 40 | + INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01), | |
| 41 | EVENT_CONSTRAINT_END | |
| 42 | }; | |
| 43 | ||
| 44 | @@ -564,6 +566,8 @@ struct event_constraint intel_atom_pebs_ | |
| 45 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */ | |
| 46 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */ | |
| 47 | INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */ | |
| 48 | + /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */ | |
| 49 | + INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01), | |
| 50 | EVENT_CONSTRAINT_END | |
| 51 | }; | |
| 52 | ||
| 53 | @@ -587,6 +591,8 @@ struct event_constraint intel_nehalem_pe | |
| 54 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */ | |
| 55 | INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */ | |
| 56 | INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */ | |
| 57 | + /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */ | |
| 58 | + INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f), | |
| 59 | EVENT_CONSTRAINT_END | |
| 60 | }; | |
| 61 | ||
| 62 | @@ -602,6 +608,8 @@ struct event_constraint intel_westmere_p | |
| 63 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */ | |
| 64 | INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */ | |
| 65 | INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */ | |
| 66 | + /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */ | |
| 67 | + INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f), | |
| 68 | EVENT_CONSTRAINT_END | |
| 69 | }; | |
| 70 |