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[thirdparty/kernel/stable-queue.git] / releases / 3.4.72 / drm-i915-flush-cursors-harder.patch
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47f6cb9e
GKH
1From b2ea8ef559b4d94190009f3651b5b3ab7c05afd3 Mon Sep 17 00:00:00 2001
2From: Daniel Vetter <daniel.vetter@ffwll.ch>
3Date: Mon, 4 Nov 2013 08:13:45 +0100
4Subject: drm/i915: flush cursors harder
5
6From: Daniel Vetter <daniel.vetter@ffwll.ch>
7
8commit b2ea8ef559b4d94190009f3651b5b3ab7c05afd3 upstream.
9
10Apparently they need the same treatment as primary planes. This fixes
11modesetting failures because of stuck cursors (!) on Thomas' i830M
12machine.
13
14I've figured while at it I'll also roll it out for the ivb 3 pipe
15version of this function. I didn't do this for i845/i865 since Bspec
16says the update mechanism works differently, and there's some
17additional rules about what can be updated in which order.
18
19Tested-by: Thomas Richter <thor@math.tu-berlin.de>
20Cc: Thomas Richter <thor@math.tu-berlin.de>
21Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
22Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
23Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
24
25---
26 drivers/gpu/drm/i915/intel_display.c | 4 ++++
27 1 file changed, 4 insertions(+)
28
29--- a/drivers/gpu/drm/i915/intel_display.c
30+++ b/drivers/gpu/drm/i915/intel_display.c
31@@ -6377,7 +6377,9 @@ static void i9xx_update_cursor(struct dr
32 intel_crtc->cursor_visible = visible;
33 }
34 /* and commit changes on next vblank */
35+ POSTING_READ(CURCNTR(pipe));
36 I915_WRITE(CURBASE(pipe), base);
37+ POSTING_READ(CURBASE(pipe));
38 }
39
40 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
41@@ -6402,7 +6404,9 @@ static void ivb_update_cursor(struct drm
42 intel_crtc->cursor_visible = visible;
43 }
44 /* and commit changes on next vblank */
45+ POSTING_READ(CURCNTR_IVB(pipe));
46 I915_WRITE(CURBASE_IVB(pipe), base);
47+ POSTING_READ(CURBASE_IVB(pipe));
48 }
49
50 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */