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60859109 GKH |
1 | From 65fc7f9957c52ad4fdf4ee5dfe3a75aa0a633d39 Mon Sep 17 00:00:00 2001 |
2 | From: Gabor Juhos <juhosg@openwrt.org> | |
3 | Date: Sat, 1 Sep 2012 18:46:00 +0200 | |
4 | Subject: MIPS: ath79: use correct fractional dividers for {CPU,DDR}_PLL on AR934x | |
5 | ||
6 | From: Gabor Juhos <juhosg@openwrt.org> | |
7 | ||
8 | commit 65fc7f9957c52ad4fdf4ee5dfe3a75aa0a633d39 upstream. | |
9 | ||
10 | The current dividers in the code are wrong and this | |
11 | leads to broken CPU frequency calculation on boards | |
12 | where the fractional part is used. | |
13 | ||
14 | For example, if the SoC is running from a 40MHz | |
15 | reference clock, refdiv=1, nint=14, outdiv=0 and | |
16 | nfrac=31 the real frequency is 579.375MHz but the | |
17 | current code calculates 569.687MHz instead. | |
18 | ||
19 | Because the system time is indirectly related to | |
20 | the CPU frequency the broken computation causes | |
21 | drift in the system time. | |
22 | ||
23 | The correct divider is 2^6 for the CPU PLL and 2^10 | |
24 | for the DDR PLL. Use the correct values to fix the | |
25 | issue. | |
26 | ||
27 | Signed-off-by: Gabor Juhos <juhosg@openwrt.org> | |
28 | Cc: linux-mips@linux-mips.org | |
29 | Patchwork: https://patchwork.linux-mips.org/patch/4305/ | |
30 | Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | |
31 | Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> | |
32 | ||
33 | --- | |
34 | arch/mips/ath79/clock.c | 4 ++-- | |
35 | 1 file changed, 2 insertions(+), 2 deletions(-) | |
36 | ||
37 | --- a/arch/mips/ath79/clock.c | |
38 | +++ b/arch/mips/ath79/clock.c | |
39 | @@ -189,7 +189,7 @@ static void __init ar934x_clocks_init(vo | |
40 | AR934X_PLL_CPU_CONFIG_NFRAC_MASK; | |
41 | ||
42 | cpu_pll = nint * ath79_ref_clk.rate / ref_div; | |
43 | - cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 6)); | |
44 | + cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 6)); | |
45 | cpu_pll /= (1 << out_div); | |
46 | ||
47 | pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG); | |
48 | @@ -203,7 +203,7 @@ static void __init ar934x_clocks_init(vo | |
49 | AR934X_PLL_DDR_CONFIG_NFRAC_MASK; | |
50 | ||
51 | ddr_pll = nint * ath79_ref_clk.rate / ref_div; | |
52 | - ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 10)); | |
53 | + ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 10)); | |
54 | ddr_pll /= (1 << out_div); | |
55 | ||
56 | clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG); |