projects / thirdparty / kernel / stable-queue.git / blame
| Commit | Line | Data |
|---|---|---|
| 2705b78f GKH |
1 | From a5719a40aef956ba704f2aa1c7b977224d60fa96 Mon Sep 17 00:00:00 2001 |
| 2 | From: Stuart Menefy <stuart.menefy@mathembedded.com> | |
| 3 | Date: Sun, 10 Feb 2019 22:51:13 +0000 | |
| 4 | Subject: clocksource/drivers/exynos_mct: Move one-shot check from tick clear to ISR | |
| 5 | ||
| 6 | From: Stuart Menefy <stuart.menefy@mathembedded.com> | |
| 7 | ||
| 8 | commit a5719a40aef956ba704f2aa1c7b977224d60fa96 upstream. | |
| 9 | ||
| 10 | When a timer tick occurs and the clock is in one-shot mode, the timer | |
| 11 | needs to be stopped to prevent it triggering subsequent interrupts. | |
| 12 | Currently this code is in exynos4_mct_tick_clear(), but as it is | |
| 13 | only needed when an ISR occurs move it into exynos4_mct_tick_isr(), | |
| 14 | leaving exynos4_mct_tick_clear() just doing what its name suggests it | |
| 15 | should. | |
| 16 | ||
| 17 | Signed-off-by: Stuart Menefy <stuart.menefy@mathembedded.com> | |
| 18 | Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> | |
| 19 | Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> | |
| 20 | Cc: stable@vger.kernel.org # v4.3+ | |
| 21 | Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> | |
| 22 | Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> | |
| 23 | ||
| 24 | --- | |
| 25 | drivers/clocksource/exynos_mct.c | 22 +++++++++++----------- | |
| 26 | 1 file changed, 11 insertions(+), 11 deletions(-) | |
| 27 | ||
| 28 | --- a/drivers/clocksource/exynos_mct.c | |
| 29 | +++ b/drivers/clocksource/exynos_mct.c | |
| 30 | @@ -388,6 +388,13 @@ static void exynos4_mct_tick_start(unsig | |
| 31 | exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET); | |
| 32 | } | |
| 33 | ||
| 34 | +static void exynos4_mct_tick_clear(struct mct_clock_event_device *mevt) | |
| 35 | +{ | |
| 36 | + /* Clear the MCT tick interrupt */ | |
| 37 | + if (readl_relaxed(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) | |
| 38 | + exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET); | |
| 39 | +} | |
| 40 | + | |
| 41 | static int exynos4_tick_set_next_event(unsigned long cycles, | |
| 42 | struct clock_event_device *evt) | |
| 43 | { | |
| 44 | @@ -420,8 +427,11 @@ static int set_state_periodic(struct clo | |
| 45 | return 0; | |
| 46 | } | |
| 47 | ||
| 48 | -static void exynos4_mct_tick_clear(struct mct_clock_event_device *mevt) | |
| 49 | +static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id) | |
| 50 | { | |
| 51 | + struct mct_clock_event_device *mevt = dev_id; | |
| 52 | + struct clock_event_device *evt = &mevt->evt; | |
| 53 | + | |
| 54 | /* | |
| 55 | * This is for supporting oneshot mode. | |
| 56 | * Mct would generate interrupt periodically | |
| 57 | @@ -430,16 +440,6 @@ static void exynos4_mct_tick_clear(struc | |
| 58 | if (!clockevent_state_periodic(&mevt->evt)) | |
| 59 | exynos4_mct_tick_stop(mevt); | |
| 60 | ||
| 61 | - /* Clear the MCT tick interrupt */ | |
| 62 | - if (readl_relaxed(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) | |
| 63 | - exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET); | |
| 64 | -} | |
| 65 | - | |
| 66 | -static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id) | |
| 67 | -{ | |
| 68 | - struct mct_clock_event_device *mevt = dev_id; | |
| 69 | - struct clock_event_device *evt = &mevt->evt; | |
| 70 | - | |
| 71 | exynos4_mct_tick_clear(mevt); | |
| 72 | ||
| 73 | evt->event_handler(evt); |