]>
Commit | Line | Data |
---|---|---|
04fd09d4 SL |
1 | From 0c735dd4456ff9d7a6fcbeb3c95bd27d75ae3130 Mon Sep 17 00:00:00 2001 |
2 | From: Mathieu Malaterre <malat@debian.org> | |
3 | Date: Fri, 15 Dec 2017 13:46:39 +0100 | |
4 | Subject: ARM: dts: lpc32xx: Remove leading 0x and 0s from bindings notation | |
5 | ||
6 | [ Upstream commit 3e3380d0675d5e20b0af067d60cb947a4348bf9b ] | |
7 | ||
8 | Improve the DTS files by removing all the leading "0x" and zeros to fix | |
9 | the following dtc warnings: | |
10 | ||
11 | Warning (unit_address_format): Node /XXX unit name should not have leading "0x" | |
12 | ||
13 | and | |
14 | ||
15 | Warning (unit_address_format): Node /XXX unit name should not have leading 0s | |
16 | ||
17 | Converted using the following command: | |
18 | ||
19 | find . -type f \( -iname *.dts -o -iname *.dtsi \) -exec sed -i -e "s/@\([0-9a-fA-FxX\.;:#]+\)\s*{/@\L\1 {/g" -e "s/@0x\(.*\) {/@\1 {/g" -e "s/@0+\(.*\) {/@\1 {/g" {} + | |
20 | ||
21 | For simplicity, two sed expressions were used to solve each warnings | |
22 | separately. | |
23 | ||
24 | To make the regex expression more robust a few other issues were resolved, | |
25 | namely setting unit-address to lower case, and adding a whitespace before | |
26 | the opening curly brace: | |
27 | ||
28 | https://elinux.org/Device_Tree_Linux#Linux_conventions | |
29 | ||
30 | This will solve as a side effect warning: | |
31 | ||
32 | Warning (simple_bus_reg): Node /XXX@<UPPER> simple-bus unit address format error, expected "<lower>" | |
33 | ||
34 | This is a follow up to commit 4c9847b7375a ("dt-bindings: Remove leading 0x from bindings notation") | |
35 | ||
36 | Reported-by: David Daney <ddaney@caviumnetworks.com> | |
37 | Suggested-by: Rob Herring <robh@kernel.org> | |
38 | Signed-off-by: Mathieu Malaterre <malat@debian.org> | |
39 | [vzapolskiy: fixed commit message to pass checkpatch.pl test] | |
40 | Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> | |
41 | Signed-off-by: Sasha Levin <sashal@kernel.org> | |
42 | --- | |
43 | arch/arm/boot/dts/lpc32xx.dtsi | 18 +++++++++--------- | |
44 | 1 file changed, 9 insertions(+), 9 deletions(-) | |
45 | ||
46 | diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi | |
47 | index d81fe433e3c8..f22a33a01819 100644 | |
48 | --- a/arch/arm/boot/dts/lpc32xx.dtsi | |
49 | +++ b/arch/arm/boot/dts/lpc32xx.dtsi | |
50 | @@ -230,7 +230,7 @@ | |
51 | status = "disabled"; | |
52 | }; | |
53 | ||
54 | - i2s1: i2s@2009C000 { | |
55 | + i2s1: i2s@2009c000 { | |
56 | compatible = "nxp,lpc3220-i2s"; | |
57 | reg = <0x2009C000 0x1000>; | |
58 | }; | |
59 | @@ -273,7 +273,7 @@ | |
60 | status = "disabled"; | |
61 | }; | |
62 | ||
63 | - i2c1: i2c@400A0000 { | |
64 | + i2c1: i2c@400a0000 { | |
65 | compatible = "nxp,pnx-i2c"; | |
66 | reg = <0x400A0000 0x100>; | |
67 | interrupt-parent = <&sic1>; | |
68 | @@ -284,7 +284,7 @@ | |
69 | clocks = <&clk LPC32XX_CLK_I2C1>; | |
70 | }; | |
71 | ||
72 | - i2c2: i2c@400A8000 { | |
73 | + i2c2: i2c@400a8000 { | |
74 | compatible = "nxp,pnx-i2c"; | |
75 | reg = <0x400A8000 0x100>; | |
76 | interrupt-parent = <&sic1>; | |
77 | @@ -295,7 +295,7 @@ | |
78 | clocks = <&clk LPC32XX_CLK_I2C2>; | |
79 | }; | |
80 | ||
81 | - mpwm: mpwm@400E8000 { | |
82 | + mpwm: mpwm@400e8000 { | |
83 | compatible = "nxp,lpc3220-motor-pwm"; | |
84 | reg = <0x400E8000 0x78>; | |
85 | status = "disabled"; | |
86 | @@ -394,7 +394,7 @@ | |
87 | #gpio-cells = <3>; /* bank, pin, flags */ | |
88 | }; | |
89 | ||
90 | - timer4: timer@4002C000 { | |
91 | + timer4: timer@4002c000 { | |
92 | compatible = "nxp,lpc3220-timer"; | |
93 | reg = <0x4002C000 0x1000>; | |
94 | interrupts = <3 IRQ_TYPE_LEVEL_LOW>; | |
95 | @@ -412,7 +412,7 @@ | |
96 | status = "disabled"; | |
97 | }; | |
98 | ||
99 | - watchdog: watchdog@4003C000 { | |
100 | + watchdog: watchdog@4003c000 { | |
101 | compatible = "nxp,pnx4008-wdt"; | |
102 | reg = <0x4003C000 0x1000>; | |
103 | clocks = <&clk LPC32XX_CLK_WDOG>; | |
104 | @@ -451,7 +451,7 @@ | |
105 | status = "disabled"; | |
106 | }; | |
107 | ||
108 | - timer1: timer@4004C000 { | |
109 | + timer1: timer@4004c000 { | |
110 | compatible = "nxp,lpc3220-timer"; | |
111 | reg = <0x4004C000 0x1000>; | |
112 | interrupts = <17 IRQ_TYPE_LEVEL_LOW>; | |
113 | @@ -475,7 +475,7 @@ | |
114 | status = "disabled"; | |
115 | }; | |
116 | ||
117 | - pwm1: pwm@4005C000 { | |
118 | + pwm1: pwm@4005c000 { | |
119 | compatible = "nxp,lpc3220-pwm"; | |
120 | reg = <0x4005C000 0x4>; | |
121 | clocks = <&clk LPC32XX_CLK_PWM1>; | |
122 | @@ -484,7 +484,7 @@ | |
123 | status = "disabled"; | |
124 | }; | |
125 | ||
126 | - pwm2: pwm@4005C004 { | |
127 | + pwm2: pwm@4005c004 { | |
128 | compatible = "nxp,lpc3220-pwm"; | |
129 | reg = <0x4005C004 0x4>; | |
130 | clocks = <&clk LPC32XX_CLK_PWM2>; | |
131 | -- | |
132 | 2.19.1 | |
133 |