projects / thirdparty / kernel / stable-queue.git / blame
| Commit | Line | Data |
|---|---|---|
| 04fd09d4 SL |
1 | From 133a62fff959672b761dab9f4b34139706ed9a62 Mon Sep 17 00:00:00 2001 |
| 2 | From: Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com> | |
| 3 | Date: Fri, 1 Feb 2019 13:02:26 +0530 | |
| 4 | Subject: platform/x86: intel_pmc_core: Fix PCH IP sts reading | |
| 5 | ||
| 6 | [ Upstream commit 0e68eeea9894feeba2edf7ec63e4551b87f39621 ] | |
| 7 | ||
| 8 | A previous commit "platform/x86: intel_pmc_core: Make the driver PCH | |
| 9 | family agnostic <c977b98bbef5898ed3d30b08ea67622e9e82082a>" provided | |
| 10 | better abstraction to this driver but has some fundamental issues. | |
| 11 | ||
| 12 | e.g. the following condition | |
| 13 | ||
| 14 | for (index = 0; index < pmcdev->map->ppfear_buckets && | |
| 15 | index < PPFEAR_MAX_NUM_ENTRIES; index++, iter++) | |
| 16 | ||
| 17 | is wrong because for CNL, PPFEAR_MAX_NUM_ENTRIES is hardcoded as 5 which | |
| 18 | is _wrong_ and even though ppfear_buckets is 8, the loop fails to read | |
| 19 | all eight registers needed for CNL PCH i.e. PPFEAR0 and PPFEAR1. This | |
| 20 | patch refactors the pfear show logic to correctly read PCH IP power | |
| 21 | gating status for Cannonlake and beyond. | |
| 22 | ||
| 23 | Cc: "David E. Box" <david.e.box@intel.com> | |
| 24 | Cc: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> | |
| 25 | Fixes: c977b98bbef5 ("platform/x86: intel_pmc_core: Make the driver PCH family agnostic") | |
| 26 | Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com> | |
| 27 | Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> | |
| 28 | Signed-off-by: Sasha Levin <sashal@kernel.org> | |
| 29 | --- | |
| 30 | drivers/platform/x86/intel_pmc_core.c | 3 ++- | |
| 31 | drivers/platform/x86/intel_pmc_core.h | 2 +- | |
| 32 | 2 files changed, 3 insertions(+), 2 deletions(-) | |
| 33 | ||
| 34 | diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c | |
| 35 | index 17e08b42b0a9..aaeb0242a99d 100644 | |
| 36 | --- a/drivers/platform/x86/intel_pmc_core.c | |
| 37 | +++ b/drivers/platform/x86/intel_pmc_core.c | |
| 38 | @@ -222,7 +222,8 @@ static int pmc_core_ppfear_sts_show(struct seq_file *s, void *unused) | |
| 39 | index < PPFEAR_MAX_NUM_ENTRIES; index++, iter++) | |
| 40 | pf_regs[index] = pmc_core_reg_read_byte(pmcdev, iter); | |
| 41 | ||
| 42 | - for (index = 0; map[index].name; index++) | |
| 43 | + for (index = 0; map[index].name && | |
| 44 | + index < pmcdev->map->ppfear_buckets * 8; index++) | |
| 45 | pmc_core_display_map(s, index, pf_regs[index / 8], map); | |
| 46 | ||
| 47 | return 0; | |
| 48 | diff --git a/drivers/platform/x86/intel_pmc_core.h b/drivers/platform/x86/intel_pmc_core.h | |
| 49 | index 3d225a9cc09f..1f13426eb61a 100644 | |
| 50 | --- a/drivers/platform/x86/intel_pmc_core.h | |
| 51 | +++ b/drivers/platform/x86/intel_pmc_core.h | |
| 52 | @@ -38,7 +38,7 @@ | |
| 53 | #define SPT_PMC_SLP_S0_RES_COUNTER_STEP 0x64 | |
| 54 | #define PMC_BASE_ADDR_MASK ~(SPT_PMC_MMIO_REG_LEN - 1) | |
| 55 | #define MTPMC_MASK 0xffff0000 | |
| 56 | -#define PPFEAR_MAX_NUM_ENTRIES 5 | |
| 57 | +#define PPFEAR_MAX_NUM_ENTRIES 12 | |
| 58 | #define SPT_PPFEAR_NUM_ENTRIES 5 | |
| 59 | #define SPT_PMC_READ_DISABLE_BIT 0x16 | |
| 60 | #define SPT_PMC_MSG_FULL_STS_BIT 0x18 | |
| 61 | -- | |
| 62 | 2.19.1 | |
| 63 |