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1 | From 3fe3331bb285700ab2253dbb07f8e478fcea2f1b Mon Sep 17 00:00:00 2001 |
2 | From: Kim Phillips <kim.phillips@amd.com> | |
3 | Date: Thu, 21 Mar 2019 21:15:22 +0000 | |
4 | Subject: perf/x86/amd: Add event map for AMD Family 17h | |
5 | MIME-Version: 1.0 | |
6 | Content-Type: text/plain; charset=UTF-8 | |
7 | Content-Transfer-Encoding: 8bit | |
8 | ||
9 | From: Kim Phillips <kim.phillips@amd.com> | |
10 | ||
11 | commit 3fe3331bb285700ab2253dbb07f8e478fcea2f1b upstream. | |
12 | ||
13 | Family 17h differs from prior families by: | |
14 | ||
15 | - Does not support an L2 cache miss event | |
16 | - It has re-enumerated PMC counters for: | |
17 | - L2 cache references | |
18 | - front & back end stalled cycles | |
19 | ||
20 | So we add a new amd_f17h_perfmon_event_map[] so that the generic | |
21 | perf event names will resolve to the correct h/w events on | |
22 | family 17h and above processors. | |
23 | ||
24 | Reference sections 2.1.13.3.3 (stalls) and 2.1.13.3.6 (L2): | |
25 | ||
26 | https://www.amd.com/system/files/TechDocs/54945_PPR_Family_17h_Models_00h-0Fh.pdf | |
27 | ||
28 | Signed-off-by: Kim Phillips <kim.phillips@amd.com> | |
29 | Cc: <stable@vger.kernel.org> # v4.9+ | |
30 | Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> | |
31 | Cc: Arnaldo Carvalho de Melo <acme@kernel.org> | |
32 | Cc: Borislav Petkov <bp@alien8.de> | |
33 | Cc: H. Peter Anvin <hpa@zytor.com> | |
34 | Cc: Janakarajan Natarajan <Janakarajan.Natarajan@amd.com> | |
35 | Cc: Jiri Olsa <jolsa@redhat.com> | |
36 | Cc: Linus Torvalds <torvalds@linux-foundation.org> | |
37 | Cc: Martin Liška <mliska@suse.cz> | |
38 | Cc: Namhyung Kim <namhyung@kernel.org> | |
39 | Cc: Peter Zijlstra <peterz@infradead.org> | |
40 | Cc: Pu Wen <puwen@hygon.cn> | |
41 | Cc: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> | |
42 | Cc: Thomas Gleixner <tglx@linutronix.de> | |
43 | Cc: linux-kernel@vger.kernel.org | |
44 | Fixes: e40ed1542dd7 ("perf/x86: Add perf support for AMD family-17h processors") | |
45 | [ Improved the formatting a bit. ] | |
46 | Signed-off-by: Ingo Molnar <mingo@kernel.org> | |
47 | Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> | |
48 | ||
49 | --- | |
50 | arch/x86/events/amd/core.c | 35 ++++++++++++++++++++++++++--------- | |
51 | 1 file changed, 26 insertions(+), 9 deletions(-) | |
52 | ||
53 | --- a/arch/x86/events/amd/core.c | |
54 | +++ b/arch/x86/events/amd/core.c | |
55 | @@ -117,22 +117,39 @@ static __initconst const u64 amd_hw_cach | |
56 | }; | |
57 | ||
58 | /* | |
59 | - * AMD Performance Monitor K7 and later. | |
60 | + * AMD Performance Monitor K7 and later, up to and including Family 16h: | |
61 | */ | |
62 | static const u64 amd_perfmon_event_map[PERF_COUNT_HW_MAX] = | |
63 | { | |
64 | - [PERF_COUNT_HW_CPU_CYCLES] = 0x0076, | |
65 | - [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, | |
66 | - [PERF_COUNT_HW_CACHE_REFERENCES] = 0x077d, | |
67 | - [PERF_COUNT_HW_CACHE_MISSES] = 0x077e, | |
68 | - [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c2, | |
69 | - [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c3, | |
70 | - [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x00d0, /* "Decoder empty" event */ | |
71 | - [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x00d1, /* "Dispatch stalls" event */ | |
72 | + [PERF_COUNT_HW_CPU_CYCLES] = 0x0076, | |
73 | + [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, | |
74 | + [PERF_COUNT_HW_CACHE_REFERENCES] = 0x077d, | |
75 | + [PERF_COUNT_HW_CACHE_MISSES] = 0x077e, | |
76 | + [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c2, | |
77 | + [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c3, | |
78 | + [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x00d0, /* "Decoder empty" event */ | |
79 | + [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x00d1, /* "Dispatch stalls" event */ | |
80 | +}; | |
81 | + | |
82 | +/* | |
83 | + * AMD Performance Monitor Family 17h and later: | |
84 | + */ | |
85 | +static const u64 amd_f17h_perfmon_event_map[PERF_COUNT_HW_MAX] = | |
86 | +{ | |
87 | + [PERF_COUNT_HW_CPU_CYCLES] = 0x0076, | |
88 | + [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, | |
89 | + [PERF_COUNT_HW_CACHE_REFERENCES] = 0xff60, | |
90 | + [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c2, | |
91 | + [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c3, | |
92 | + [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x0287, | |
93 | + [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x0187, | |
94 | }; | |
95 | ||
96 | static u64 amd_pmu_event_map(int hw_event) | |
97 | { | |
98 | + if (boot_cpu_data.x86 >= 0x17) | |
99 | + return amd_f17h_perfmon_event_map[hw_event]; | |
100 | + | |
101 | return amd_perfmon_event_map[hw_event]; | |
102 | } | |
103 |