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21cf661e GKH |
1 | From 9d5dcc93a6ddfc78124f006ccd3637ce070ef2fc Mon Sep 17 00:00:00 2001 |
2 | From: Kan Liang <kan.liang@linux.intel.com> | |
3 | Date: Tue, 2 Apr 2019 12:44:58 -0700 | |
4 | Subject: perf/x86: Fix incorrect PEBS_REGS | |
5 | ||
6 | From: Kan Liang <kan.liang@linux.intel.com> | |
7 | ||
8 | commit 9d5dcc93a6ddfc78124f006ccd3637ce070ef2fc upstream. | |
9 | ||
10 | PEBS_REGS used as mask for the supported registers for large PEBS. | |
11 | However, the mask cannot filter the sample_regs_user/sample_regs_intr | |
12 | correctly. | |
13 | ||
14 | (1ULL << PERF_REG_X86_*) should be used to replace PERF_REG_X86_*, which | |
15 | is only the index. | |
16 | ||
17 | Rename PEBS_REGS to PEBS_GP_REGS, because the mask is only for general | |
18 | purpose registers. | |
19 | ||
20 | Signed-off-by: Kan Liang <kan.liang@linux.intel.com> | |
21 | Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> | |
22 | Cc: <stable@vger.kernel.org> | |
23 | Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> | |
24 | Cc: Arnaldo Carvalho de Melo <acme@redhat.com> | |
25 | Cc: Jiri Olsa <jolsa@redhat.com> | |
26 | Cc: Linus Torvalds <torvalds@linux-foundation.org> | |
27 | Cc: Peter Zijlstra <peterz@infradead.org> | |
28 | Cc: Stephane Eranian <eranian@google.com> | |
29 | Cc: Thomas Gleixner <tglx@linutronix.de> | |
30 | Cc: Vince Weaver <vincent.weaver@maine.edu> | |
31 | Cc: acme@kernel.org | |
32 | Cc: jolsa@kernel.org | |
33 | Fixes: 2fe1bc1f501d ("perf/x86: Enable free running PEBS for REGS_USER/INTR") | |
34 | Link: https://lkml.kernel.org/r/20190402194509.2832-2-kan.liang@linux.intel.com | |
35 | [ Renamed it to PEBS_GP_REGS - as 'GPRS' is used elsewhere ;-) ] | |
36 | Signed-off-by: Ingo Molnar <mingo@kernel.org> | |
37 | Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> | |
38 | ||
39 | --- | |
40 | arch/x86/events/intel/core.c | 2 +- | |
41 | arch/x86/events/perf_event.h | 38 +++++++++++++++++++------------------- | |
42 | 2 files changed, 20 insertions(+), 20 deletions(-) | |
43 | ||
44 | --- a/arch/x86/events/intel/core.c | |
45 | +++ b/arch/x86/events/intel/core.c | |
46 | @@ -3001,7 +3001,7 @@ static unsigned long intel_pmu_free_runn | |
47 | flags &= ~PERF_SAMPLE_TIME; | |
48 | if (!event->attr.exclude_kernel) | |
49 | flags &= ~PERF_SAMPLE_REGS_USER; | |
50 | - if (event->attr.sample_regs_user & ~PEBS_REGS) | |
51 | + if (event->attr.sample_regs_user & ~PEBS_GP_REGS) | |
52 | flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR); | |
53 | return flags; | |
54 | } | |
55 | --- a/arch/x86/events/perf_event.h | |
56 | +++ b/arch/x86/events/perf_event.h | |
57 | @@ -95,25 +95,25 @@ struct amd_nb { | |
58 | PERF_SAMPLE_TRANSACTION | PERF_SAMPLE_PHYS_ADDR | \ | |
59 | PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER) | |
60 | ||
61 | -#define PEBS_REGS \ | |
62 | - (PERF_REG_X86_AX | \ | |
63 | - PERF_REG_X86_BX | \ | |
64 | - PERF_REG_X86_CX | \ | |
65 | - PERF_REG_X86_DX | \ | |
66 | - PERF_REG_X86_DI | \ | |
67 | - PERF_REG_X86_SI | \ | |
68 | - PERF_REG_X86_SP | \ | |
69 | - PERF_REG_X86_BP | \ | |
70 | - PERF_REG_X86_IP | \ | |
71 | - PERF_REG_X86_FLAGS | \ | |
72 | - PERF_REG_X86_R8 | \ | |
73 | - PERF_REG_X86_R9 | \ | |
74 | - PERF_REG_X86_R10 | \ | |
75 | - PERF_REG_X86_R11 | \ | |
76 | - PERF_REG_X86_R12 | \ | |
77 | - PERF_REG_X86_R13 | \ | |
78 | - PERF_REG_X86_R14 | \ | |
79 | - PERF_REG_X86_R15) | |
80 | +#define PEBS_GP_REGS \ | |
81 | + ((1ULL << PERF_REG_X86_AX) | \ | |
82 | + (1ULL << PERF_REG_X86_BX) | \ | |
83 | + (1ULL << PERF_REG_X86_CX) | \ | |
84 | + (1ULL << PERF_REG_X86_DX) | \ | |
85 | + (1ULL << PERF_REG_X86_DI) | \ | |
86 | + (1ULL << PERF_REG_X86_SI) | \ | |
87 | + (1ULL << PERF_REG_X86_SP) | \ | |
88 | + (1ULL << PERF_REG_X86_BP) | \ | |
89 | + (1ULL << PERF_REG_X86_IP) | \ | |
90 | + (1ULL << PERF_REG_X86_FLAGS) | \ | |
91 | + (1ULL << PERF_REG_X86_R8) | \ | |
92 | + (1ULL << PERF_REG_X86_R9) | \ | |
93 | + (1ULL << PERF_REG_X86_R10) | \ | |
94 | + (1ULL << PERF_REG_X86_R11) | \ | |
95 | + (1ULL << PERF_REG_X86_R12) | \ | |
96 | + (1ULL << PERF_REG_X86_R13) | \ | |
97 | + (1ULL << PERF_REG_X86_R14) | \ | |
98 | + (1ULL << PERF_REG_X86_R15)) | |
99 | ||
100 | /* | |
101 | * Per register state. |