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af53c2aa GKH |
1 | From 30414f3010aff95ffdb6bed7b9dce62cde94fdc7 Mon Sep 17 00:00:00 2001 |
2 | From: Lucas De Marchi <lucas.demarchi@intel.com> | |
3 | Date: Tue, 2 Jan 2018 12:18:37 -0800 | |
4 | Subject: drm/i915: Apply Display WA #1183 on skl, kbl, and cfl | |
5 | MIME-Version: 1.0 | |
6 | Content-Type: text/plain; charset=UTF-8 | |
7 | Content-Transfer-Encoding: 8bit | |
8 | ||
9 | From: Lucas De Marchi <lucas.demarchi@intel.com> | |
10 | ||
11 | commit 30414f3010aff95ffdb6bed7b9dce62cde94fdc7 upstream. | |
12 | ||
13 | Display WA #1183 was recently added to workaround | |
14 | "Failures when enabling DPLL0 with eDP link rate 2.16 | |
15 | or 4.32 GHz and CD clock frequency 308.57 or 617.14 MHz | |
16 | (CDCLK_CTL CD Frequency Select 10b or 11b) used in this | |
17 | enabling or in previous enabling." | |
18 | ||
19 | This workaround was designed to minimize the impact only | |
20 | to save the bad case with that link rates. But HW engineers | |
21 | indicated that it should be safe to apply broadly, although | |
22 | they were expecting the DPLL0 link rate to be unchanged on | |
23 | runtime. | |
24 | ||
25 | We need to cover 2 cases: when we are in fact enabling DPLL0 | |
26 | and when we are just changing the frequency with small | |
27 | differences. | |
28 | ||
29 | This is based on previous patch by Rodrigo Vivi with suggestions | |
30 | from Ville Syrjälä. | |
31 | ||
32 | Cc: Arthur J Runyan <arthur.j.runyan@intel.com> | |
33 | Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> | |
34 | Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> | |
35 | Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> | |
36 | Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> | |
37 | Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> | |
38 | Link: https://patchwork.freedesktop.org/patch/msgid/20171204232210.4958-1-lucas.demarchi@intel.com | |
39 | (cherry picked from commit 53421c2fe99ce16838639ad89d772d914a119a49) | |
40 | [ Lucas: Backport to 4.15 adding back variable that has been removed on | |
41 | commits not meant to be backported ] | |
42 | Signed-off-by: Jani Nikula <jani.nikula@intel.com> | |
43 | Link: https://patchwork.freedesktop.org/patch/msgid/20180102201837.6812-1-lucas.demarchi@intel.com | |
44 | Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> | |
45 | ||
46 | --- | |
47 | drivers/gpu/drm/i915/i915_reg.h | 2 + | |
48 | drivers/gpu/drm/i915/intel_cdclk.c | 35 +++++++++++++++++++++++--------- | |
49 | drivers/gpu/drm/i915/intel_runtime_pm.c | 10 +++++++++ | |
50 | 3 files changed, 38 insertions(+), 9 deletions(-) | |
51 | ||
52 | --- a/drivers/gpu/drm/i915/i915_reg.h | |
53 | +++ b/drivers/gpu/drm/i915/i915_reg.h | |
54 | @@ -6944,6 +6944,7 @@ enum { | |
55 | #define RESET_PCH_HANDSHAKE_ENABLE (1<<4) | |
56 | ||
57 | #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430) | |
58 | +#define SKL_SELECT_ALTERNATE_DC_EXIT (1<<30) | |
59 | #define MASK_WAKEMEM (1<<13) | |
60 | ||
61 | #define SKL_DFSM _MMIO(0x51000) | |
62 | @@ -8475,6 +8476,7 @@ enum skl_power_gate { | |
63 | #define BXT_CDCLK_CD2X_DIV_SEL_2 (2<<22) | |
64 | #define BXT_CDCLK_CD2X_DIV_SEL_4 (3<<22) | |
65 | #define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe)<<20) | |
66 | +#define CDCLK_DIVMUX_CD_OVERRIDE (1<<19) | |
67 | #define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3) | |
68 | #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1<<16) | |
69 | #define CDCLK_FREQ_DECIMAL_MASK (0x7ff) | |
70 | --- a/drivers/gpu/drm/i915/intel_cdclk.c | |
71 | +++ b/drivers/gpu/drm/i915/intel_cdclk.c | |
72 | @@ -859,16 +859,10 @@ static void skl_set_preferred_cdclk_vco( | |
73 | ||
74 | static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) | |
75 | { | |
76 | - int min_cdclk = skl_calc_cdclk(0, vco); | |
77 | u32 val; | |
78 | ||
79 | WARN_ON(vco != 8100000 && vco != 8640000); | |
80 | ||
81 | - /* select the minimum CDCLK before enabling DPLL 0 */ | |
82 | - val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk); | |
83 | - I915_WRITE(CDCLK_CTL, val); | |
84 | - POSTING_READ(CDCLK_CTL); | |
85 | - | |
86 | /* | |
87 | * We always enable DPLL0 with the lowest link rate possible, but still | |
88 | * taking into account the VCO required to operate the eDP panel at the | |
89 | @@ -922,7 +916,7 @@ static void skl_set_cdclk(struct drm_i91 | |
90 | { | |
91 | int cdclk = cdclk_state->cdclk; | |
92 | int vco = cdclk_state->vco; | |
93 | - u32 freq_select, pcu_ack; | |
94 | + u32 freq_select, pcu_ack, cdclk_ctl; | |
95 | int ret; | |
96 | ||
97 | WARN_ON((cdclk == 24000) != (vco == 0)); | |
98 | @@ -939,7 +933,7 @@ static void skl_set_cdclk(struct drm_i91 | |
99 | return; | |
100 | } | |
101 | ||
102 | - /* set CDCLK_CTL */ | |
103 | + /* Choose frequency for this cdclk */ | |
104 | switch (cdclk) { | |
105 | case 450000: | |
106 | case 432000: | |
107 | @@ -967,10 +961,33 @@ static void skl_set_cdclk(struct drm_i91 | |
108 | dev_priv->cdclk.hw.vco != vco) | |
109 | skl_dpll0_disable(dev_priv); | |
110 | ||
111 | + cdclk_ctl = I915_READ(CDCLK_CTL); | |
112 | + | |
113 | + if (dev_priv->cdclk.hw.vco != vco) { | |
114 | + /* Wa Display #1183: skl,kbl,cfl */ | |
115 | + cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); | |
116 | + cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); | |
117 | + I915_WRITE(CDCLK_CTL, cdclk_ctl); | |
118 | + } | |
119 | + | |
120 | + /* Wa Display #1183: skl,kbl,cfl */ | |
121 | + cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE; | |
122 | + I915_WRITE(CDCLK_CTL, cdclk_ctl); | |
123 | + POSTING_READ(CDCLK_CTL); | |
124 | + | |
125 | if (dev_priv->cdclk.hw.vco != vco) | |
126 | skl_dpll0_enable(dev_priv, vco); | |
127 | ||
128 | - I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk)); | |
129 | + /* Wa Display #1183: skl,kbl,cfl */ | |
130 | + cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); | |
131 | + I915_WRITE(CDCLK_CTL, cdclk_ctl); | |
132 | + | |
133 | + cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); | |
134 | + I915_WRITE(CDCLK_CTL, cdclk_ctl); | |
135 | + | |
136 | + /* Wa Display #1183: skl,kbl,cfl */ | |
137 | + cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE; | |
138 | + I915_WRITE(CDCLK_CTL, cdclk_ctl); | |
139 | POSTING_READ(CDCLK_CTL); | |
140 | ||
141 | /* inform PCU of the change */ | |
142 | --- a/drivers/gpu/drm/i915/intel_runtime_pm.c | |
143 | +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c | |
144 | @@ -598,6 +598,11 @@ void gen9_enable_dc5(struct drm_i915_pri | |
145 | ||
146 | DRM_DEBUG_KMS("Enabling DC5\n"); | |
147 | ||
148 | + /* Wa Display #1183: skl,kbl,cfl */ | |
149 | + if (IS_GEN9_BC(dev_priv)) | |
150 | + I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) | | |
151 | + SKL_SELECT_ALTERNATE_DC_EXIT); | |
152 | + | |
153 | gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5); | |
154 | } | |
155 | ||
156 | @@ -625,6 +630,11 @@ void skl_disable_dc6(struct drm_i915_pri | |
157 | { | |
158 | DRM_DEBUG_KMS("Disabling DC6\n"); | |
159 | ||
160 | + /* Wa Display #1183: skl,kbl,cfl */ | |
161 | + if (IS_GEN9_BC(dev_priv)) | |
162 | + I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) | | |
163 | + SKL_SELECT_ALTERNATE_DC_EXIT); | |
164 | + | |
165 | gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); | |
166 | } | |
167 |