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2ca3111c GKH |
1 | From 4636bda86aa1f34f45c629477476a0dcfa04e597 Mon Sep 17 00:00:00 2001 |
2 | From: Kenneth Graunke <kenneth@whitecape.org> | |
3 | Date: Fri, 5 Jan 2018 00:59:05 -0800 | |
4 | Subject: drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake. | |
5 | ||
6 | From: Kenneth Graunke <kenneth@whitecape.org> | |
7 | ||
8 | commit 4636bda86aa1f34f45c629477476a0dcfa04e597 upstream. | |
9 | ||
10 | Geminilake requires the 3D driver to select whether barriers are | |
11 | intended for compute shaders, or tessellation control shaders, by | |
12 | whacking a "Barrier Mode" bit in SLICE_COMMON_ECO_CHICKEN1 when | |
13 | switching pipelines. Failure to do this properly can result in GPU | |
14 | hangs. | |
15 | ||
16 | Unfortunately, this means it needs to switch mid-batch, so only | |
17 | userspace can properly set it. To facilitate this, the kernel needs | |
18 | to whitelist the register. | |
19 | ||
20 | The workarounds page currently tags this as applying to Broxton only, | |
21 | but that doesn't make sense. The documentation for the register it | |
22 | references says the bit userspace is supposed to toggle only exists on | |
23 | Geminilake. Empirically, the Mesa patch to toggle this bit appears to | |
24 | fix intermittent GPU hangs in tessellation control shader barrier tests | |
25 | on Geminilake; we haven't seen those hangs on Broxton. | |
26 | ||
27 | v2: Mention WA #0862 in the comment (it doesn't have a name). | |
28 | ||
29 | Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> | |
30 | Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> | |
31 | Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> | |
32 | Link: https://patchwork.freedesktop.org/patch/msgid/20180105085905.9298-1-kenneth@whitecape.org | |
33 | (cherry picked from commit ab062639edb0412daf6de540725276b9a5d217f9) | |
34 | Signed-off-by: Jani Nikula <jani.nikula@intel.com> | |
35 | Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> | |
36 | ||
37 | --- | |
38 | drivers/gpu/drm/i915/i915_reg.h | 2 ++ | |
39 | drivers/gpu/drm/i915/intel_engine_cs.c | 5 +++++ | |
40 | 2 files changed, 7 insertions(+) | |
41 | ||
42 | --- a/drivers/gpu/drm/i915/i915_reg.h | |
43 | +++ b/drivers/gpu/drm/i915/i915_reg.h | |
44 | @@ -6987,6 +6987,8 @@ enum { | |
45 | #define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308) | |
46 | #define DISABLE_PIXEL_MASK_CAMMING (1<<14) | |
47 | ||
48 | +#define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c) | |
49 | + | |
50 | #define GEN7_L3SQCREG1 _MMIO(0xB010) | |
51 | #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000 | |
52 | ||
53 | --- a/drivers/gpu/drm/i915/intel_engine_cs.c | |
54 | +++ b/drivers/gpu/drm/i915/intel_engine_cs.c | |
55 | @@ -1125,6 +1125,11 @@ static int glk_init_workarounds(struct i | |
56 | if (ret) | |
57 | return ret; | |
58 | ||
59 | + /* WA #0862: Userspace has to set "Barrier Mode" to avoid hangs. */ | |
60 | + ret = wa_ring_whitelist_reg(engine, GEN9_SLICE_COMMON_ECO_CHICKEN1); | |
61 | + if (ret) | |
62 | + return ret; | |
63 | + | |
64 | /* WaToEnableHwFixForPushConstHWBug:glk */ | |
65 | WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, | |
66 | GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); |