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Commit | Line | Data |
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06e23a17 GKH |
1 | From foo@baz Thu May 24 11:09:34 CEST 2018 |
2 | From: Andrzej Hajda <a.hajda@samsung.com> | |
3 | Date: Fri, 16 Feb 2018 15:57:50 +0100 | |
4 | Subject: clk: samsung: exynos5260: Fix PLL rates | |
5 | ||
6 | From: Andrzej Hajda <a.hajda@samsung.com> | |
7 | ||
8 | [ Upstream commit cdb68fbd4e7962be742c4f29475220c5bf28d8a5 ] | |
9 | ||
10 | Rates declared in PLL rate tables should match exactly rates calculated from | |
11 | the PLL coefficients. If that is not the case, rate of the PLL's child clock | |
12 | might be set not as expected. For instance, if in the PLL rates table we have | |
13 | a 393216000 Hz entry and the real value as returned by the PLL's recalc_rate | |
14 | callback is 393216003, after setting PLL's clk rate to 393216000 clk_get_rate | |
15 | will return 393216003. If we now attempt to set rate of a PLL's child divider | |
16 | clock to 393216000/2 its rate will be 131072001, rather than 196608000. | |
17 | That is, the divider will be set to 3 instead of 2, because 393216003/2 is | |
18 | greater than 196608000. | |
19 | ||
20 | To fix this issue declared rates are changed to exactly match rates generated | |
21 | by the PLL, as calculated from the P, M, S, K coefficients. | |
22 | ||
23 | Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> | |
24 | Acked-by: Tomasz Figa <tomasz.figa@gmail.com> | |
25 | Acked-by: Chanwoo Choi <cw00.choi@samsung.com> | |
26 | Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> | |
27 | Signed-off-by: Sasha Levin <alexander.levin@microsoft.com> | |
28 | Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> | |
29 | --- | |
30 | drivers/clk/samsung/clk-exynos5260.c | 2 +- | |
31 | 1 file changed, 1 insertion(+), 1 deletion(-) | |
32 | ||
33 | --- a/drivers/clk/samsung/clk-exynos5260.c | |
34 | +++ b/drivers/clk/samsung/clk-exynos5260.c | |
35 | @@ -65,7 +65,7 @@ static const struct samsung_pll_rate_tab | |
36 | PLL_36XX_RATE(480000000, 160, 2, 2, 0), | |
37 | PLL_36XX_RATE(432000000, 144, 2, 2, 0), | |
38 | PLL_36XX_RATE(400000000, 200, 3, 2, 0), | |
39 | - PLL_36XX_RATE(394073130, 459, 7, 2, 49282), | |
40 | + PLL_36XX_RATE(394073128, 459, 7, 2, 49282), | |
41 | PLL_36XX_RATE(333000000, 111, 2, 2, 0), | |
42 | PLL_36XX_RATE(300000000, 100, 2, 2, 0), | |
43 | PLL_36XX_RATE(266000000, 266, 3, 3, 0), |