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Commit | Line | Data |
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45f76c82 GKH |
1 | From fec3259c9f747c039f90e99570540114c8d81a14 Mon Sep 17 00:00:00 2001 |
2 | From: Max Filippov <jcmvbkbc@gmail.com> | |
3 | Date: Fri, 10 Aug 2018 22:21:22 -0700 | |
4 | Subject: xtensa: increase ranges in ___invalidate_{i,d}cache_all | |
5 | ||
6 | From: Max Filippov <jcmvbkbc@gmail.com> | |
7 | ||
8 | commit fec3259c9f747c039f90e99570540114c8d81a14 upstream. | |
9 | ||
10 | Cache invalidation macros use cache line size to iterate over | |
11 | invalidated cache lines, assuming that all cache ways are invalidated by | |
12 | single instruction, but xtensa ISA recommends to not assume that for | |
13 | future compatibility: | |
14 | In some implementations all ways at index Addry-1..z are invalidated | |
15 | regardless of the specified way, but for future compatibility this | |
16 | behavior should not be assumed. | |
17 | ||
18 | Iterate over all cache ways in ___invalidate_icache_all and | |
19 | ___invalidate_dcache_all. | |
20 | ||
21 | Cc: stable@vger.kernel.org | |
22 | Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | |
23 | Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> | |
24 | ||
25 | --- | |
26 | arch/xtensa/include/asm/cacheasm.h | 4 ++-- | |
27 | 1 file changed, 2 insertions(+), 2 deletions(-) | |
28 | ||
29 | --- a/arch/xtensa/include/asm/cacheasm.h | |
30 | +++ b/arch/xtensa/include/asm/cacheasm.h | |
31 | @@ -123,7 +123,7 @@ | |
32 | .macro ___invalidate_dcache_all ar at | |
33 | ||
34 | #if XCHAL_DCACHE_SIZE | |
35 | - __loop_cache_all \ar \at dii __stringify(DCACHE_WAY_SIZE) \ | |
36 | + __loop_cache_all \ar \at dii XCHAL_DCACHE_SIZE \ | |
37 | XCHAL_DCACHE_LINEWIDTH 1020 | |
38 | #endif | |
39 | ||
40 | @@ -133,7 +133,7 @@ | |
41 | .macro ___invalidate_icache_all ar at | |
42 | ||
43 | #if XCHAL_ICACHE_SIZE | |
44 | - __loop_cache_all \ar \at iii __stringify(ICACHE_WAY_SIZE) \ | |
45 | + __loop_cache_all \ar \at iii XCHAL_ICACHE_SIZE \ | |
46 | XCHAL_ICACHE_LINEWIDTH 1020 | |
47 | #endif | |
48 |