projects / thirdparty / kernel / stable-queue.git / blame
| Commit | Line | Data |
|---|---|---|
| b0b15cd0 GKH |
1 | From 85e290d92b4b794d0c758c53007eb4248d385386 Mon Sep 17 00:00:00 2001 |
| 2 | From: Paul Parsons <lost.distance@yahoo.com> | |
| 3 | Date: Sat, 2 Apr 2016 12:32:30 +0100 | |
| 4 | Subject: drm/radeon: Fix PCIe lane width calculation | |
| 5 | MIME-Version: 1.0 | |
| 6 | Content-Type: text/plain; charset=UTF-8 | |
| 7 | Content-Transfer-Encoding: 8bit | |
| 8 | ||
| 9 | From: Paul Parsons <lost.distance@yahoo.com> | |
| 10 | ||
| 11 | commit 85e290d92b4b794d0c758c53007eb4248d385386 upstream. | |
| 12 | ||
| 13 | Two years ago I tried an AMD Radeon E8860 embedded GPU with the drm driver. | |
| 14 | The dmesg output included driver warnings about an invalid PCIe lane width. | |
| 15 | Tracking the problem back led to si_set_pcie_lane_width_in_smc(). | |
| 16 | The calculation of the lane widths via ATOM_PPLIB_PCIE_LINK_WIDTH_MASK and | |
| 17 | ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT macros did not increment the resulting | |
| 18 | value, per the comment in pptable.h ("lanes - 1"), and per usage elsewhere. | |
| 19 | Applying the increment silenced the warnings. | |
| 20 | The code has not changed since, so either my analysis was incorrect or the | |
| 21 | bug has gone unnoticed. Hence submitting this as an RFC. | |
| 22 | ||
| 23 | Acked-by: Christian König <christian.koenig@amd.com> | |
| 24 | Acked-by: Chunming Zhou <david1.zhou@amd.com> | |
| 25 | Signed-off-by: Paul Parsons <lost.distance@yahoo.com> | |
| 26 | Signed-off-by: Alex Deucher <alexander.deucher@amd.com> | |
| 27 | Cc: stable@vger.kernel.org | |
| 28 | Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> | |
| 29 | ||
| 30 | --- | |
| 31 | drivers/gpu/drm/radeon/si_dpm.c | 4 ++-- | |
| 32 | 1 file changed, 2 insertions(+), 2 deletions(-) | |
| 33 | ||
| 34 | --- a/drivers/gpu/drm/radeon/si_dpm.c | |
| 35 | +++ b/drivers/gpu/drm/radeon/si_dpm.c | |
| 36 | @@ -5912,9 +5912,9 @@ static void si_set_pcie_lane_width_in_sm | |
| 37 | { | |
| 38 | u32 lane_width; | |
| 39 | u32 new_lane_width = | |
| 40 | - (radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT; | |
| 41 | + ((radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; | |
| 42 | u32 current_lane_width = | |
| 43 | - (radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT; | |
| 44 | + ((radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; | |
| 45 | ||
| 46 | if (new_lane_width != current_lane_width) { | |
| 47 | radeon_set_pcie_lanes(rdev, new_lane_width); |