projects / thirdparty / kernel / stable-queue.git / blame
| Commit | Line | Data |
|---|---|---|
| 15877d25 GKH |
1 | From 7797167ffde1f00446301cb22b37b7c03194cfaf Mon Sep 17 00:00:00 2001 |
| 2 | From: John David Anglin <dave.anglin@bell.net> | |
| 3 | Date: Sun, 12 Aug 2018 16:38:03 -0400 | |
| 4 | Subject: parisc: Remove ordered stores from syscall.S | |
| 5 | MIME-Version: 1.0 | |
| 6 | Content-Type: text/plain; charset=UTF-8 | |
| 7 | Content-Transfer-Encoding: 8bit | |
| 8 | ||
| 9 | From: John David Anglin <dave.anglin@bell.net> | |
| 10 | ||
| 11 | commit 7797167ffde1f00446301cb22b37b7c03194cfaf upstream. | |
| 12 | ||
| 13 | Now that we use a sync prior to releasing the locks in syscall.S, we don't need | |
| 14 | the PA 2.0 ordered stores used to release some locks. Using an ordered store, | |
| 15 | potentially slows the release and subsequent code. | |
| 16 | ||
| 17 | There are a number of other ordered stores and loads that serve no purpose. I | |
| 18 | have converted these to normal stores. | |
| 19 | ||
| 20 | Signed-off-by: John David Anglin <dave.anglin@bell.net> | |
| 21 | Cc: stable@vger.kernel.org # 4.0+ | |
| 22 | Signed-off-by: Helge Deller <deller@gmx.de> | |
| 23 | Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> | |
| 24 | ||
| 25 | --- | |
| 26 | arch/parisc/kernel/syscall.S | 24 ++++++++++++------------ | |
| 27 | 1 file changed, 12 insertions(+), 12 deletions(-) | |
| 28 | ||
| 29 | --- a/arch/parisc/kernel/syscall.S | |
| 30 | +++ b/arch/parisc/kernel/syscall.S | |
| 31 | @@ -627,12 +627,12 @@ cas_action: | |
| 32 | stw %r1, 4(%sr2,%r20) | |
| 33 | #endif | |
| 34 | /* The load and store could fail */ | |
| 35 | -1: ldw,ma 0(%r26), %r28 | |
| 36 | +1: ldw 0(%r26), %r28 | |
| 37 | sub,<> %r28, %r25, %r0 | |
| 38 | -2: stw,ma %r24, 0(%r26) | |
| 39 | +2: stw %r24, 0(%r26) | |
| 40 | /* Free lock */ | |
| 41 | sync | |
| 42 | - stw,ma %r20, 0(%sr2,%r20) | |
| 43 | + stw %r20, 0(%sr2,%r20) | |
| 44 | #if ENABLE_LWS_DEBUG | |
| 45 | /* Clear thread register indicator */ | |
| 46 | stw %r0, 4(%sr2,%r20) | |
| 47 | @@ -796,30 +796,30 @@ cas2_action: | |
| 48 | ldo 1(%r0),%r28 | |
| 49 | ||
| 50 | /* 8bit CAS */ | |
| 51 | -13: ldb,ma 0(%r26), %r29 | |
| 52 | +13: ldb 0(%r26), %r29 | |
| 53 | sub,= %r29, %r25, %r0 | |
| 54 | b,n cas2_end | |
| 55 | -14: stb,ma %r24, 0(%r26) | |
| 56 | +14: stb %r24, 0(%r26) | |
| 57 | b cas2_end | |
| 58 | copy %r0, %r28 | |
| 59 | nop | |
| 60 | nop | |
| 61 | ||
| 62 | /* 16bit CAS */ | |
| 63 | -15: ldh,ma 0(%r26), %r29 | |
| 64 | +15: ldh 0(%r26), %r29 | |
| 65 | sub,= %r29, %r25, %r0 | |
| 66 | b,n cas2_end | |
| 67 | -16: sth,ma %r24, 0(%r26) | |
| 68 | +16: sth %r24, 0(%r26) | |
| 69 | b cas2_end | |
| 70 | copy %r0, %r28 | |
| 71 | nop | |
| 72 | nop | |
| 73 | ||
| 74 | /* 32bit CAS */ | |
| 75 | -17: ldw,ma 0(%r26), %r29 | |
| 76 | +17: ldw 0(%r26), %r29 | |
| 77 | sub,= %r29, %r25, %r0 | |
| 78 | b,n cas2_end | |
| 79 | -18: stw,ma %r24, 0(%r26) | |
| 80 | +18: stw %r24, 0(%r26) | |
| 81 | b cas2_end | |
| 82 | copy %r0, %r28 | |
| 83 | nop | |
| 84 | @@ -827,10 +827,10 @@ cas2_action: | |
| 85 | ||
| 86 | /* 64bit CAS */ | |
| 87 | #ifdef CONFIG_64BIT | |
| 88 | -19: ldd,ma 0(%r26), %r29 | |
| 89 | +19: ldd 0(%r26), %r29 | |
| 90 | sub,*= %r29, %r25, %r0 | |
| 91 | b,n cas2_end | |
| 92 | -20: std,ma %r24, 0(%r26) | |
| 93 | +20: std %r24, 0(%r26) | |
| 94 | copy %r0, %r28 | |
| 95 | #else | |
| 96 | /* Compare first word */ | |
| 97 | @@ -849,7 +849,7 @@ cas2_action: | |
| 98 | cas2_end: | |
| 99 | /* Free lock */ | |
| 100 | sync | |
| 101 | - stw,ma %r20, 0(%sr2,%r20) | |
| 102 | + stw %r20, 0(%sr2,%r20) | |
| 103 | /* Enable interrupts */ | |
| 104 | ssm PSW_SM_I, %r0 | |
| 105 | /* Return to userspace, set no error */ |