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1From foo@baz Tue 14 May 2019 08:29:35 PM CEST
2From: Ben Hutchings <ben@decadent.org.uk>
3Date: Wed, 7 Nov 2018 17:09:42 +0000
4Subject: x86/cpufeatures: Hide AMD-specific speculation flags
5
6From: Ben Hutchings <ben@decadent.org.uk>
7
8Hide the AMD_{IBRS,IBPB,STIBP} flag from /proc/cpuinfo. This was done
9upstream as part of commit e7c587da1252 "x86/speculation: Use
10synthetic bits for IBRS/IBPB/STIBP". That commit has already been
11backported but this part was omitted.
12
13Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
14Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
15---
16 arch/x86/include/asm/cpufeatures.h | 6 +++---
17 1 file changed, 3 insertions(+), 3 deletions(-)
18
19--- a/arch/x86/include/asm/cpufeatures.h
20+++ b/arch/x86/include/asm/cpufeatures.h
21@@ -265,9 +265,9 @@
22
23 /* AMD-defined CPU features, CPUID level 0x80000008 (ebx), word 13 */
24 #define X86_FEATURE_CLZERO (13*32+0) /* CLZERO instruction */
25-#define X86_FEATURE_AMD_IBPB (13*32+12) /* Indirect Branch Prediction Barrier */
26-#define X86_FEATURE_AMD_IBRS (13*32+14) /* Indirect Branch Restricted Speculation */
27-#define X86_FEATURE_AMD_STIBP (13*32+15) /* Single Thread Indirect Branch Predictors */
28+#define X86_FEATURE_AMD_IBPB (13*32+12) /* "" Indirect Branch Prediction Barrier */
29+#define X86_FEATURE_AMD_IBRS (13*32+14) /* "" Indirect Branch Restricted Speculation */
30+#define X86_FEATURE_AMD_STIBP (13*32+15) /* "" Single Thread Indirect Branch Predictors */
31 #define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */
32
33 /* Thermal and Power Management Leaf, CPUID level 0x00000006 (eax), word 14 */