projects / thirdparty / kernel / stable-queue.git / blame
| Commit | Line | Data |
|---|---|---|
| 5a4432b0 SL |
1 | From 3ebfffa9fc0040c17a701bf2129d01b544ba0cd5 Mon Sep 17 00:00:00 2001 |
| 2 | From: Sasha Levin <sashal@kernel.org> | |
| 3 | Date: Mon, 21 Sep 2020 00:10:16 +0200 | |
| 4 | Subject: ARM: p2v: fix handling of LPAE translation in BE mode | |
| 5 | ||
| 6 | From: Ard Biesheuvel <ardb@kernel.org> | |
| 7 | ||
| 8 | [ Upstream commit 4e79f0211b473f8e1eab8211a9fd50cc41a3a061 ] | |
| 9 | ||
| 10 | When running in BE mode on LPAE hardware with a PA-to-VA translation | |
| 11 | that exceeds 4 GB, we patch bits 39:32 of the offset into the wrong | |
| 12 | byte of the opcode. So fix that, by rotating the offset in r0 to the | |
| 13 | right by 8 bits, which will put the 8-bit immediate in bits 31:24. | |
| 14 | ||
| 15 | Note that this will also move bit #22 in its correct place when | |
| 16 | applying the rotation to the constant #0x400000. | |
| 17 | ||
| 18 | Fixes: d9a790df8e984 ("ARM: 7883/1: fix mov to mvn conversion in case of 64 bit phys_addr_t and BE") | |
| 19 | Acked-by: Nicolas Pitre <nico@fluxnic.net> | |
| 20 | Reviewed-by: Linus Walleij <linus.walleij@linaro.org> | |
| 21 | Signed-off-by: Ard Biesheuvel <ardb@kernel.org> | |
| 22 | Signed-off-by: Sasha Levin <sashal@kernel.org> | |
| 23 | --- | |
| 24 | arch/arm/kernel/head.S | 6 +----- | |
| 25 | 1 file changed, 1 insertion(+), 5 deletions(-) | |
| 26 | ||
| 27 | diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S | |
| 28 | index 04286fd9e09ce..2e336acd68b0a 100644 | |
| 29 | --- a/arch/arm/kernel/head.S | |
| 30 | +++ b/arch/arm/kernel/head.S | |
| 31 | @@ -673,12 +673,8 @@ ARM_BE8(rev16 ip, ip) | |
| 32 | ldrcc r7, [r4], #4 @ use branch for delay slot | |
| 33 | bcc 1b | |
| 34 | bx lr | |
| 35 | -#else | |
| 36 | -#ifdef CONFIG_CPU_ENDIAN_BE8 | |
| 37 | - moveq r0, #0x00004000 @ set bit 22, mov to mvn instruction | |
| 38 | #else | |
| 39 | moveq r0, #0x400000 @ set bit 22, mov to mvn instruction | |
| 40 | -#endif | |
| 41 | b 2f | |
| 42 | 1: ldr ip, [r7, r3] | |
| 43 | #ifdef CONFIG_CPU_ENDIAN_BE8 | |
| 44 | @@ -687,7 +683,7 @@ ARM_BE8(rev16 ip, ip) | |
| 45 | tst ip, #0x000f0000 @ check the rotation field | |
| 46 | orrne ip, ip, r6, lsl #24 @ mask in offset bits 31-24 | |
| 47 | biceq ip, ip, #0x00004000 @ clear bit 22 | |
| 48 | - orreq ip, ip, r0 @ mask in offset bits 7-0 | |
| 49 | + orreq ip, ip, r0, ror #8 @ mask in offset bits 7-0 | |
| 50 | #else | |
| 51 | bic ip, ip, #0x000000ff | |
| 52 | tst ip, #0xf00 @ check the rotation field | |
| 53 | -- | |
| 54 | 2.27.0 | |
| 55 |