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526d5907 GKH |
1 | From 34dc8993eef63681b062871413a9484008a2a78f Mon Sep 17 00:00:00 2001 |
2 | From: Mika Kuoppala <mika.kuoppala@linux.intel.com> | |
3 | Date: Wed, 15 Feb 2017 15:52:59 +0200 | |
4 | Subject: drm/i915: Avoid tweaking evaluation thresholds on Baytrail v3 | |
5 | MIME-Version: 1.0 | |
6 | Content-Type: text/plain; charset=UTF-8 | |
7 | Content-Transfer-Encoding: 8bit | |
8 | ||
9 | From: Mika Kuoppala <mika.kuoppala@linux.intel.com> | |
10 | ||
11 | commit 34dc8993eef63681b062871413a9484008a2a78f upstream. | |
12 | ||
13 | Certain Baytrails, namely the 4 cpu core variants, have been | |
14 | plaqued by spurious system hangs, mostly occurring with light loads. | |
15 | ||
16 | Multiple bisects by various people point to a commit which changes the | |
17 | reclocking strategy for Baytrail to follow its bigger brethen: | |
18 | commit 8fb55197e64d ("drm/i915: Agressive downclocking on Baytrail") | |
19 | ||
20 | There is also a review comment attached to this commit from Deepak S | |
21 | on avoiding punit access on Cherryview and thus it was excluded on | |
22 | common reclocking path. By taking the same approach and omitting | |
23 | the punit access by not tweaking the thresholds when the hardware | |
24 | has been asked to move into different frequency, considerable gains | |
25 | in stability have been observed. | |
26 | ||
27 | With J1900 box, light render/video load would end up in system hang | |
28 | in usually less than 12 hours. With this patch applied, the cumulative | |
29 | uptime has now been 34 days without issues. To provoke system hang, | |
30 | light loads on both render and bsd engines in parallel have been used: | |
31 | glxgears >/dev/null 2>/dev/null & | |
32 | mpv --vo=vaapi --hwdec=vaapi --loop=inf vid.mp4 | |
33 | ||
34 | So far, author has not witnessed system hang with above load | |
35 | and this patch applied. Reports from the tenacious people at | |
36 | kernel bugzilla are also promising. | |
37 | ||
38 | Considering that the punit access frequency with this patch is | |
39 | considerably less, there is a possibility that this will push | |
40 | the, still unknown, root cause past the triggering point on most loads. | |
41 | ||
42 | But as we now can reliably reproduce the hang independently, | |
43 | we can reduce the pain that users are having and use a | |
44 | static thresholds until a root cause is found. | |
45 | ||
46 | v3: don't break debugfs and simplification (Chris Wilson) | |
47 | ||
48 | References: https://bugzilla.kernel.org/show_bug.cgi?id=109051 | |
49 | Cc: Chris Wilson <chris@chris-wilson.co.uk> | |
50 | Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> | |
51 | Cc: Len Brown <len.brown@intel.com> | |
52 | Cc: Daniel Vetter <daniel.vetter@ffwll.ch> | |
53 | Cc: Jani Nikula <jani.nikula@intel.com> | |
54 | Cc: fritsch@xbmc.org | |
55 | Cc: miku@iki.fi | |
56 | Cc: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> | |
57 | CC: Michal Feix <michal@feix.cz> | |
58 | Cc: Hans de Goede <hdegoede@redhat.com> | |
59 | Cc: Deepak S <deepak.s@linux.intel.com> | |
60 | Cc: Jarkko Nikula <jarkko.nikula@linux.intel.com> | |
61 | Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> | |
62 | Acked-by: Chris Wilson <chris@chris-wilson.co.uk> | |
63 | Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> | |
64 | Link: http://patchwork.freedesktop.org/patch/msgid/1487166779-26945-1-git-send-email-mika.kuoppala@intel.com | |
65 | (cherry picked from commit 6067a27d1f0184596d51decbac1c1fdc4acb012f) | |
66 | Signed-off-by: Jani Nikula <jani.nikula@intel.com> | |
67 | Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> | |
68 | ||
69 | --- | |
70 | drivers/gpu/drm/i915/intel_pm.c | 7 +++++++ | |
71 | 1 file changed, 7 insertions(+) | |
72 | ||
73 | --- a/drivers/gpu/drm/i915/intel_pm.c | |
74 | +++ b/drivers/gpu/drm/i915/intel_pm.c | |
75 | @@ -4376,6 +4376,12 @@ static void gen6_set_rps_thresholds(stru | |
76 | break; | |
77 | } | |
78 | ||
79 | + /* When byt can survive without system hang with dynamic | |
80 | + * sw freq adjustments, this restriction can be lifted. | |
81 | + */ | |
82 | + if (IS_VALLEYVIEW(dev_priv)) | |
83 | + goto skip_hw_write; | |
84 | + | |
85 | I915_WRITE(GEN6_RP_UP_EI, | |
86 | GT_INTERVAL_FROM_US(dev_priv, ei_up)); | |
87 | I915_WRITE(GEN6_RP_UP_THRESHOLD, | |
88 | @@ -4394,6 +4400,7 @@ static void gen6_set_rps_thresholds(stru | |
89 | GEN6_RP_UP_BUSY_AVG | | |
90 | GEN6_RP_DOWN_IDLE_AVG); | |
91 | ||
92 | +skip_hw_write: | |
93 | dev_priv->rps.power = new_power; | |
94 | dev_priv->rps.up_threshold = threshold_up; | |
95 | dev_priv->rps.down_threshold = threshold_down; |