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8fece351 GKH |
1 | From caed361d83b204b7766924b80463bf7502ee7986 Mon Sep 17 00:00:00 2001 |
2 | From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com> | |
3 | Date: Wed, 9 Mar 2016 19:07:25 +0200 | |
4 | Subject: drm/i915: Fix watermarks for VLV/CHV | |
5 | MIME-Version: 1.0 | |
6 | Content-Type: text/plain; charset=UTF-8 | |
7 | Content-Transfer-Encoding: 8bit | |
8 | ||
9 | From: Ville Syrjälä <ville.syrjala@linux.intel.com> | |
10 | ||
11 | commit caed361d83b204b7766924b80463bf7502ee7986 upstream. | |
12 | ||
13 | commit 92826fcdfc14 ("drm/i915: Calculate watermark related members in the crtc_state, v4.") | |
14 | broke thigns by removing the pre vs. post wm update distinction. We also | |
15 | lost the pre plane wm update entirely for VLV/CHV from the crtc enable | |
16 | path. | |
17 | ||
18 | This caused underruns on modeset and plane enable/disable on CHV, | |
19 | and often those can lead to a dead pipe. | |
20 | ||
21 | So let's bring back the pre vs. post thing, and let's toss in an | |
22 | explicit wm update to valleyview_crtc_enable() to avoid having to | |
23 | put it into the common code. | |
24 | ||
25 | This is more or less a partial revert of the offending commit. | |
26 | ||
27 | Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> | |
28 | Cc: drm-intel-fixes@lists.freedesktop.org | |
29 | Fixes: 92826fcdfc14 ("drm/i915: Calculate watermark related members in the crtc_state, v4.") | |
30 | Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> | |
31 | Link: http://patchwork.freedesktop.org/patch/msgid/1457543247-13987-4-git-send-email-ville.syrjala@linux.intel.com | |
32 | Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> | |
33 | Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> | |
34 | ||
35 | --- | |
36 | drivers/gpu/drm/i915/intel_atomic.c | 3 ++- | |
37 | drivers/gpu/drm/i915/intel_display.c | 21 +++++++++++++++------ | |
38 | drivers/gpu/drm/i915/intel_drv.h | 2 +- | |
39 | 3 files changed, 18 insertions(+), 8 deletions(-) | |
40 | ||
41 | --- a/drivers/gpu/drm/i915/intel_atomic.c | |
42 | +++ b/drivers/gpu/drm/i915/intel_atomic.c | |
43 | @@ -96,7 +96,8 @@ intel_crtc_duplicate_state(struct drm_cr | |
44 | crtc_state->update_pipe = false; | |
45 | crtc_state->disable_lp_wm = false; | |
46 | crtc_state->disable_cxsr = false; | |
47 | - crtc_state->wm_changed = false; | |
48 | + crtc_state->update_wm_pre = false; | |
49 | + crtc_state->update_wm_post = false; | |
50 | ||
51 | return &crtc_state->base; | |
52 | } | |
53 | --- a/drivers/gpu/drm/i915/intel_display.c | |
54 | +++ b/drivers/gpu/drm/i915/intel_display.c | |
55 | @@ -4816,7 +4816,7 @@ static void intel_post_plane_update(stru | |
56 | ||
57 | crtc->wm.cxsr_allowed = true; | |
58 | ||
59 | - if (pipe_config->wm_changed && pipe_config->base.active) | |
60 | + if (pipe_config->update_wm_post && pipe_config->base.active) | |
61 | intel_update_watermarks(&crtc->base); | |
62 | ||
63 | if (atomic->update_fbc) | |
64 | @@ -4850,7 +4850,7 @@ static void intel_pre_plane_update(struc | |
65 | intel_set_memory_cxsr(dev_priv, false); | |
66 | } | |
67 | ||
68 | - if (!needs_modeset(&pipe_config->base) && pipe_config->wm_changed) | |
69 | + if (!needs_modeset(&pipe_config->base) && pipe_config->update_wm_pre) | |
70 | intel_update_watermarks(&crtc->base); | |
71 | } | |
72 | ||
73 | @@ -6229,6 +6229,7 @@ static void valleyview_crtc_enable(struc | |
74 | ||
75 | intel_crtc_load_lut(crtc); | |
76 | ||
77 | + intel_update_watermarks(crtc); | |
78 | intel_enable_pipe(intel_crtc); | |
79 | ||
80 | assert_vblank_disabled(crtc); | |
81 | @@ -11881,8 +11882,14 @@ int intel_plane_atomic_calc_changes(stru | |
82 | plane->base.id, was_visible, visible, | |
83 | turn_off, turn_on, mode_changed); | |
84 | ||
85 | - if (turn_on || turn_off) { | |
86 | - pipe_config->wm_changed = true; | |
87 | + if (turn_on) { | |
88 | + pipe_config->update_wm_pre = true; | |
89 | + | |
90 | + /* must disable cxsr around plane enable/disable */ | |
91 | + if (plane->type != DRM_PLANE_TYPE_CURSOR) | |
92 | + pipe_config->disable_cxsr = true; | |
93 | + } else if (turn_off) { | |
94 | + pipe_config->update_wm_post = true; | |
95 | ||
96 | /* must disable cxsr around plane enable/disable */ | |
97 | if (plane->type != DRM_PLANE_TYPE_CURSOR) { | |
98 | @@ -11891,7 +11898,9 @@ int intel_plane_atomic_calc_changes(stru | |
99 | pipe_config->disable_cxsr = true; | |
100 | } | |
101 | } else if (intel_wm_need_update(plane, plane_state)) { | |
102 | - pipe_config->wm_changed = true; | |
103 | + /* FIXME bollocks */ | |
104 | + pipe_config->update_wm_pre = true; | |
105 | + pipe_config->update_wm_post = true; | |
106 | } | |
107 | ||
108 | if (visible || was_visible) | |
109 | @@ -12036,7 +12045,7 @@ static int intel_crtc_atomic_check(struc | |
110 | } | |
111 | ||
112 | if (mode_changed && !crtc_state->active) | |
113 | - pipe_config->wm_changed = true; | |
114 | + pipe_config->update_wm_post = true; | |
115 | ||
116 | if (mode_changed && crtc_state->enable && | |
117 | dev_priv->display.crtc_compute_clock && | |
118 | --- a/drivers/gpu/drm/i915/intel_drv.h | |
119 | +++ b/drivers/gpu/drm/i915/intel_drv.h | |
120 | @@ -367,7 +367,7 @@ struct intel_crtc_state { | |
121 | ||
122 | bool update_pipe; /* can a fast modeset be performed? */ | |
123 | bool disable_cxsr; | |
124 | - bool wm_changed; /* watermarks are updated */ | |
125 | + bool update_wm_pre, update_wm_post; /* watermarks are updated */ | |
126 | ||
127 | /* Pipe source size (ie. panel fitter input size) | |
128 | * All planes will be positioned inside this space, |