projects / thirdparty / kernel / stable-queue.git / blame
| Commit | Line | Data |
|---|---|---|
| 700b5fa6 GKH |
1 | From c7103f650a11328f28b9fa1c95027db331b7774b Mon Sep 17 00:00:00 2001 |
| 2 | From: Tony Luck <tony.luck@intel.com> | |
| 3 | Date: Tue, 31 May 2016 11:50:28 -0700 | |
| 4 | Subject: EDAC, sb_edac: Fix rank lookup on Broadwell | |
| 5 | ||
| 6 | From: Tony Luck <tony.luck@intel.com> | |
| 7 | ||
| 8 | commit c7103f650a11328f28b9fa1c95027db331b7774b upstream. | |
| 9 | ||
| 10 | Broadwell made a small change to the rank target register moving the | |
| 11 | target rank ID field up from bits 16:19 to bits 20:23. | |
| 12 | ||
| 13 | Also found that the offset field grew by one bit in the IVY_BRIDGE to | |
| 14 | HASWELL transition, so fix the RIR_OFFSET() macro too. | |
| 15 | ||
| 16 | Signed-off-by: Tony Luck <tony.luck@intel.com> | |
| 17 | Cc: Aristeu Rozanski <arozansk@redhat.com> | |
| 18 | Cc: Mauro Carvalho Chehab <mchehab@osg.samsung.com> | |
| 19 | Cc: linux-edac <linux-edac@vger.kernel.org> | |
| 20 | Link: http://lkml.kernel.org/r/2943fb819b1f7e396681165db9c12bb3df0e0b16.1464735623.git.tony.luck@intel.com | |
| 21 | Signed-off-by: Borislav Petkov <bp@suse.de> | |
| 22 | Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> | |
| 23 | ||
| 24 | --- | |
| 25 | drivers/edac/sb_edac.c | 13 ++++++++----- | |
| 26 | 1 file changed, 8 insertions(+), 5 deletions(-) | |
| 27 | ||
| 28 | --- a/drivers/edac/sb_edac.c | |
| 29 | +++ b/drivers/edac/sb_edac.c | |
| 30 | @@ -239,8 +239,11 @@ static const u32 rir_offset[MAX_RIR_RANG | |
| 31 | { 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc }, | |
| 32 | }; | |
| 33 | ||
| 34 | -#define RIR_RNK_TGT(reg) GET_BITFIELD(reg, 16, 19) | |
| 35 | -#define RIR_OFFSET(reg) GET_BITFIELD(reg, 2, 14) | |
| 36 | +#define RIR_RNK_TGT(type, reg) (((type) == BROADWELL) ? \ | |
| 37 | + GET_BITFIELD(reg, 20, 23) : GET_BITFIELD(reg, 16, 19)) | |
| 38 | + | |
| 39 | +#define RIR_OFFSET(type, reg) (((type) == HASWELL || (type) == BROADWELL) ? \ | |
| 40 | + GET_BITFIELD(reg, 2, 15) : GET_BITFIELD(reg, 2, 14)) | |
| 41 | ||
| 42 | /* Device 16, functions 2-7 */ | |
| 43 | ||
| 44 | @@ -1916,14 +1919,14 @@ static void get_memory_layout(const stru | |
| 45 | pci_read_config_dword(pvt->pci_tad[i], | |
| 46 | rir_offset[j][k], | |
| 47 | ®); | |
| 48 | - tmp_mb = RIR_OFFSET(reg) << 6; | |
| 49 | + tmp_mb = RIR_OFFSET(pvt->info.type, reg) << 6; | |
| 50 | ||
| 51 | gb = div_u64_rem(tmp_mb, 1024, &mb); | |
| 52 | edac_dbg(0, "CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n", | |
| 53 | i, j, k, | |
| 54 | gb, (mb*1000)/1024, | |
| 55 | ((u64)tmp_mb) << 20L, | |
| 56 | - (u32)RIR_RNK_TGT(reg), | |
| 57 | + (u32)RIR_RNK_TGT(pvt->info.type, reg), | |
| 58 | reg); | |
| 59 | } | |
| 60 | } | |
| 61 | @@ -2256,7 +2259,7 @@ static int get_memory_error_data(struct | |
| 62 | pci_read_config_dword(pvt->pci_tad[ch_add + base_ch], | |
| 63 | rir_offset[n_rir][idx], | |
| 64 | ®); | |
| 65 | - *rank = RIR_RNK_TGT(reg); | |
| 66 | + *rank = RIR_RNK_TGT(pvt->info.type, reg); | |
| 67 | ||
| 68 | edac_dbg(0, "RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n", | |
| 69 | n_rir, |