projects / thirdparty / kernel / stable-queue.git / blame
| Commit | Line | Data |
|---|---|---|
| 169a2920 GKH |
1 | From b1d51b448e4e6a392283b3eab06a7c5ec6d8a4e2 Mon Sep 17 00:00:00 2001 |
| 2 | From: Lucas Stach <l.stach@pengutronix.de> | |
| 3 | Date: Fri, 16 Sep 2016 11:16:10 +0200 | |
| 4 | Subject: clk: imx6: fix i.MX6DL clock tree to reflect reality | |
| 5 | ||
| 6 | From: Lucas Stach <l.stach@pengutronix.de> | |
| 7 | ||
| 8 | commit b1d51b448e4e6a392283b3eab06a7c5ec6d8a4e2 upstream. | |
| 9 | ||
| 10 | The current clock tree only implements the minimal set of differences | |
| 11 | between the i.MX6Q and the i.MX6DL, but that doesn't really reflect | |
| 12 | reality. | |
| 13 | ||
| 14 | Apply the following fixes to match the RM: | |
| 15 | - DL has no GPU3D_SHADER_SEL/PODF, the shader domain is clocked by | |
| 16 | GPU3D_CORE | |
| 17 | - GPU3D_SHADER_SEL/PODF has been repurposed as GPU2D_CORE_SEL/PODF | |
| 18 | - GPU2D_CORE_SEL/PODF has been repurposed as MLB_SEL/PODF | |
| 19 | ||
| 20 | Signed-off-by: Lucas Stach <l.stach@pengutronix.de> | |
| 21 | Acked-by: Shawn Guo <shawnguo@kernel.org> | |
| 22 | Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> | |
| 23 | Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> | |
| 24 | ||
| 25 | --- | |
| 26 | drivers/clk/imx/clk-imx6q.c | 28 ++++++++++++++++------------ | |
| 27 | include/dt-bindings/clock/imx6qdl-clock.h | 4 +++- | |
| 28 | 2 files changed, 19 insertions(+), 13 deletions(-) | |
| 29 | ||
| 30 | --- a/drivers/clk/imx/clk-imx6q.c | |
| 31 | +++ b/drivers/clk/imx/clk-imx6q.c | |
| 32 | @@ -318,11 +318,16 @@ static void __init imx6q_clocks_init(str | |
| 33 | clk[IMX6QDL_CLK_IPG_PER_SEL] = imx_clk_mux("ipg_per_sel", base + 0x1c, 6, 1, ipg_per_sels, ARRAY_SIZE(ipg_per_sels)); | |
| 34 | clk[IMX6QDL_CLK_UART_SEL] = imx_clk_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels)); | |
| 35 | clk[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels_2, ARRAY_SIZE(gpu2d_core_sels_2)); | |
| 36 | + } else if (clk_on_imx6dl()) { | |
| 37 | + clk[IMX6QDL_CLK_MLB_SEL] = imx_clk_mux("mlb_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels)); | |
| 38 | } else { | |
| 39 | clk[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels)); | |
| 40 | } | |
| 41 | clk[IMX6QDL_CLK_GPU3D_CORE_SEL] = imx_clk_mux("gpu3d_core_sel", base + 0x18, 4, 2, gpu3d_core_sels, ARRAY_SIZE(gpu3d_core_sels)); | |
| 42 | - clk[IMX6QDL_CLK_GPU3D_SHADER_SEL] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels)); | |
| 43 | + if (clk_on_imx6dl()) | |
| 44 | + clk[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels)); | |
| 45 | + else | |
| 46 | + clk[IMX6QDL_CLK_GPU3D_SHADER_SEL] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels)); | |
| 47 | clk[IMX6QDL_CLK_IPU1_SEL] = imx_clk_mux("ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); | |
| 48 | clk[IMX6QDL_CLK_IPU2_SEL] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); | |
| 49 | clk[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT); | |
| 50 | @@ -400,9 +405,15 @@ static void __init imx6q_clocks_init(str | |
| 51 | clk[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7); | |
| 52 | clk[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7); | |
| 53 | } | |
| 54 | - clk[IMX6QDL_CLK_GPU2D_CORE_PODF] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3); | |
| 55 | + if (clk_on_imx6dl()) | |
| 56 | + clk[IMX6QDL_CLK_MLB_PODF] = imx_clk_divider("mlb_podf", "mlb_sel", base + 0x18, 23, 3); | |
| 57 | + else | |
| 58 | + clk[IMX6QDL_CLK_GPU2D_CORE_PODF] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3); | |
| 59 | clk[IMX6QDL_CLK_GPU3D_CORE_PODF] = imx_clk_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3); | |
| 60 | - clk[IMX6QDL_CLK_GPU3D_SHADER] = imx_clk_divider("gpu3d_shader", "gpu3d_shader_sel", base + 0x18, 29, 3); | |
| 61 | + if (clk_on_imx6dl()) | |
| 62 | + clk[IMX6QDL_CLK_GPU2D_CORE_PODF] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 29, 3); | |
| 63 | + else | |
| 64 | + clk[IMX6QDL_CLK_GPU3D_SHADER] = imx_clk_divider("gpu3d_shader", "gpu3d_shader_sel", base + 0x18, 29, 3); | |
| 65 | clk[IMX6QDL_CLK_IPU1_PODF] = imx_clk_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3); | |
| 66 | clk[IMX6QDL_CLK_IPU2_PODF] = imx_clk_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3); | |
| 67 | clk[IMX6QDL_CLK_LDB_DI0_PODF] = imx_clk_divider_flags("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1, 0); | |
| 68 | @@ -473,14 +484,7 @@ static void __init imx6q_clocks_init(str | |
| 69 | clk[IMX6QDL_CLK_ESAI_MEM] = imx_clk_gate2_shared("esai_mem", "ahb", base + 0x6c, 16, &share_count_esai); | |
| 70 | clk[IMX6QDL_CLK_GPT_IPG] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20); | |
| 71 | clk[IMX6QDL_CLK_GPT_IPG_PER] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22); | |
| 72 | - if (clk_on_imx6dl()) | |
| 73 | - /* | |
| 74 | - * The multiplexer and divider of imx6q clock gpu3d_shader get | |
| 75 | - * redefined/reused as gpu2d_core_sel and gpu2d_core_podf on imx6dl. | |
| 76 | - */ | |
| 77 | - clk[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_gate2("gpu2d_core", "gpu3d_shader", base + 0x6c, 24); | |
| 78 | - else | |
| 79 | - clk[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24); | |
| 80 | + clk[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24); | |
| 81 | clk[IMX6QDL_CLK_GPU3D_CORE] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26); | |
| 82 | clk[IMX6QDL_CLK_HDMI_IAHB] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0); | |
| 83 | clk[IMX6QDL_CLK_HDMI_ISFR] = imx_clk_gate2("hdmi_isfr", "video_27m", base + 0x70, 4); | |
| 84 | @@ -511,7 +515,7 @@ static void __init imx6q_clocks_init(str | |
| 85 | * The multiplexer and divider of the imx6q clock gpu2d get | |
| 86 | * redefined/reused as mlb_sys_sel and mlb_sys_clk_podf on imx6dl. | |
| 87 | */ | |
| 88 | - clk[IMX6QDL_CLK_MLB] = imx_clk_gate2("mlb", "gpu2d_core_podf", base + 0x74, 18); | |
| 89 | + clk[IMX6QDL_CLK_MLB] = imx_clk_gate2("mlb", "mlb_podf", base + 0x74, 18); | |
| 90 | else | |
| 91 | clk[IMX6QDL_CLK_MLB] = imx_clk_gate2("mlb", "axi", base + 0x74, 18); | |
| 92 | clk[IMX6QDL_CLK_MMDC_CH0_AXI] = imx_clk_gate2("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20); | |
| 93 | --- a/include/dt-bindings/clock/imx6qdl-clock.h | |
| 94 | +++ b/include/dt-bindings/clock/imx6qdl-clock.h | |
| 95 | @@ -269,6 +269,8 @@ | |
| 96 | #define IMX6QDL_CLK_PRG0_APB 256 | |
| 97 | #define IMX6QDL_CLK_PRG1_APB 257 | |
| 98 | #define IMX6QDL_CLK_PRE_AXI 258 | |
| 99 | -#define IMX6QDL_CLK_END 259 | |
| 100 | +#define IMX6QDL_CLK_MLB_SEL 259 | |
| 101 | +#define IMX6QDL_CLK_MLB_PODF 260 | |
| 102 | +#define IMX6QDL_CLK_END 261 | |
| 103 | ||
| 104 | #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */ |