projects / thirdparty / kernel / stable-queue.git / blame
| Commit | Line | Data |
|---|---|---|
| 95244f99 GKH |
1 | From foo@baz Wed Dec 6 17:39:55 CET 2017 |
| 2 | From: Subhash Jadavani <subhashj@codeaurora.org> | |
| 3 | Date: Wed, 27 Sep 2017 11:04:40 +0530 | |
| 4 | Subject: mmc: sdhci-msm: fix issue with power irq | |
| 5 | ||
| 6 | From: Subhash Jadavani <subhashj@codeaurora.org> | |
| 7 | ||
| 8 | ||
| 9 | [ Upstream commit c7ccee224d2d551f712752c4a16947f6529d6506 ] | |
| 10 | ||
| 11 | SDCC controller reset (SW_RST) during probe may trigger power irq if | |
| 12 | previous status of PWRCTL was either BUS_ON or IO_HIGH_V. So before we | |
| 13 | enable the power irq interrupt in GIC (by registering the interrupt | |
| 14 | handler), we need to ensure that any pending power irq interrupt status | |
| 15 | is acknowledged otherwise power irq interrupt handler would be fired | |
| 16 | prematurely. | |
| 17 | ||
| 18 | Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org> | |
| 19 | Signed-off-by: Vijay Viswanath <vviswana@codeaurora.org> | |
| 20 | Acked-by: Adrian Hunter <adrian.hunter@intel.com> | |
| 21 | Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> | |
| 22 | Signed-off-by: Sasha Levin <alexander.levin@verizon.com> | |
| 23 | Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> | |
| 24 | --- | |
| 25 | drivers/mmc/host/sdhci-msm.c | 18 ++++++++++++++++++ | |
| 26 | 1 file changed, 18 insertions(+) | |
| 27 | ||
| 28 | --- a/drivers/mmc/host/sdhci-msm.c | |
| 29 | +++ b/drivers/mmc/host/sdhci-msm.c | |
| 30 | @@ -642,6 +642,21 @@ static int sdhci_msm_probe(struct platfo | |
| 31 | CORE_VENDOR_SPEC_CAPABILITIES0); | |
| 32 | } | |
| 33 | ||
| 34 | + /* | |
| 35 | + * Power on reset state may trigger power irq if previous status of | |
| 36 | + * PWRCTL was either BUS_ON or IO_HIGH_V. So before enabling pwr irq | |
| 37 | + * interrupt in GIC, any pending power irq interrupt should be | |
| 38 | + * acknowledged. Otherwise power irq interrupt handler would be | |
| 39 | + * fired prematurely. | |
| 40 | + */ | |
| 41 | + sdhci_msm_voltage_switch(host); | |
| 42 | + | |
| 43 | + /* | |
| 44 | + * Ensure that above writes are propogated before interrupt enablement | |
| 45 | + * in GIC. | |
| 46 | + */ | |
| 47 | + mb(); | |
| 48 | + | |
| 49 | /* Setup IRQ for handling power/voltage tasks with PMIC */ | |
| 50 | msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq"); | |
| 51 | if (msm_host->pwr_irq < 0) { | |
| 52 | @@ -651,6 +666,9 @@ static int sdhci_msm_probe(struct platfo | |
| 53 | goto clk_disable; | |
| 54 | } | |
| 55 | ||
| 56 | + /* Enable pwr irq interrupts */ | |
| 57 | + writel_relaxed(INT_MASK, msm_host->core_mem + CORE_PWRCTL_MASK); | |
| 58 | + | |
| 59 | ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL, | |
| 60 | sdhci_msm_pwr_irq, IRQF_ONESHOT, | |
| 61 | dev_name(&pdev->dev), host); |