projects / thirdparty / kernel / stable-queue.git / blame
| Commit | Line | Data |
|---|---|---|
| 95244f99 GKH |
1 | From foo@baz Wed Dec 6 17:39:55 CET 2017 |
| 2 | From: Slava Shwartsman <slavash@mellanox.com> | |
| 3 | Date: Thu, 29 Dec 2016 18:37:12 +0200 | |
| 4 | Subject: net/mlx4_en: Fix type mismatch for 32-bit systems | |
| 5 | ||
| 6 | From: Slava Shwartsman <slavash@mellanox.com> | |
| 7 | ||
| 8 | ||
| 9 | [ Upstream commit 61b6034c6cfdcb265bb453505c3d688e7567727a ] | |
| 10 | ||
| 11 | is_power_of_2 expects unsigned long and we pass u64 max_val_cycles, | |
| 12 | this will be truncated on 32 bit systems, and the result is not what we | |
| 13 | were expecting. | |
| 14 | div_u64 expects u32 as a second argument and we pass | |
| 15 | max_val_cycles_rounded which is u64 hence it will always be truncated. | |
| 16 | Fix was tested on both 64 and 32 bit systems and got same results for | |
| 17 | max_val_cycles and max_val_cycles_rounded. | |
| 18 | ||
| 19 | Fixes: 4850cf458157 ("net/mlx4_en: Resolve dividing by zero in 32-bit system") | |
| 20 | Signed-off-by: Slava Shwartsman <slavash@mellanox.com> | |
| 21 | Signed-off-by: Tariq Toukan <tariqt@mellanox.com> | |
| 22 | Signed-off-by: David S. Miller <davem@davemloft.net> | |
| 23 | Signed-off-by: Sasha Levin <alexander.levin@verizon.com> | |
| 24 | Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> | |
| 25 | --- | |
| 26 | drivers/net/ethernet/mellanox/mlx4/en_clock.c | 8 ++------ | |
| 27 | 1 file changed, 2 insertions(+), 6 deletions(-) | |
| 28 | ||
| 29 | --- a/drivers/net/ethernet/mellanox/mlx4/en_clock.c | |
| 30 | +++ b/drivers/net/ethernet/mellanox/mlx4/en_clock.c | |
| 31 | @@ -251,13 +251,9 @@ static u32 freq_to_shift(u16 freq) | |
| 32 | { | |
| 33 | u32 freq_khz = freq * 1000; | |
| 34 | u64 max_val_cycles = freq_khz * 1000 * MLX4_EN_WRAP_AROUND_SEC; | |
| 35 | - u64 tmp_rounded = | |
| 36 | - roundup_pow_of_two(max_val_cycles) > max_val_cycles ? | |
| 37 | - roundup_pow_of_two(max_val_cycles) - 1 : UINT_MAX; | |
| 38 | - u64 max_val_cycles_rounded = is_power_of_2(max_val_cycles + 1) ? | |
| 39 | - max_val_cycles : tmp_rounded; | |
| 40 | + u64 max_val_cycles_rounded = 1ULL << fls64(max_val_cycles - 1); | |
| 41 | /* calculate max possible multiplier in order to fit in 64bit */ | |
| 42 | - u64 max_mul = div_u64(0xffffffffffffffffULL, max_val_cycles_rounded); | |
| 43 | + u64 max_mul = div64_u64(ULLONG_MAX, max_val_cycles_rounded); | |
| 44 | ||
| 45 | /* This comes from the reverse of clocksource_khz2mult */ | |
| 46 | return ilog2(div_u64(max_mul * freq_khz, 1000000)); |