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Commit | Line | Data |
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dc13a30d GKH |
1 | From be20bbcb0a8cb5597cc62b3e28d275919f3431df Mon Sep 17 00:00:00 2001 |
2 | From: Kazufumi Ikeda <kaz-ikeda@xc.jp.nec.com> | |
3 | Date: Mon, 25 Mar 2019 20:43:19 +0100 | |
4 | Subject: PCI: rcar: Add the initialization of PCIe link in resume_noirq() | |
5 | ||
6 | From: Kazufumi Ikeda <kaz-ikeda@xc.jp.nec.com> | |
7 | ||
8 | commit be20bbcb0a8cb5597cc62b3e28d275919f3431df upstream. | |
9 | ||
10 | Reestablish the PCIe link very early in the resume process in case it | |
11 | went down to prevent PCI accesses from hanging the bus. Such accesses | |
12 | can happen early in the PCI resume process, as early as the | |
13 | SUSPEND_RESUME_NOIRQ step, thus the link must be reestablished in the | |
14 | driver resume_noirq() callback. | |
15 | ||
16 | Fixes: e015f88c368d ("PCI: rcar: Add support for R-Car H3 to pcie-rcar") | |
17 | Signed-off-by: Kazufumi Ikeda <kaz-ikeda@xc.jp.nec.com> | |
18 | Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com> | |
19 | Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> | |
20 | [lorenzo.pieralisi@arm.com: reformatted commit log] | |
21 | Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | |
22 | Reviewed-by: Simon Horman <horms+renesas@verge.net.au> | |
23 | Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> | |
24 | Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> | |
25 | Cc: stable@vger.kernel.org | |
26 | Cc: Geert Uytterhoeven <geert+renesas@glider.be> | |
27 | Cc: Phil Edworthy <phil.edworthy@renesas.com> | |
28 | Cc: Simon Horman <horms+renesas@verge.net.au> | |
29 | Cc: Wolfram Sang <wsa@the-dreams.de> | |
30 | Cc: linux-renesas-soc@vger.kernel.org | |
31 | Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> | |
32 | ||
33 | --- | |
34 | drivers/pci/controller/pcie-rcar.c | 21 +++++++++++++++++++++ | |
35 | 1 file changed, 21 insertions(+) | |
36 | ||
37 | --- a/drivers/pci/controller/pcie-rcar.c | |
38 | +++ b/drivers/pci/controller/pcie-rcar.c | |
39 | @@ -46,6 +46,7 @@ | |
40 | ||
41 | /* Transfer control */ | |
42 | #define PCIETCTLR 0x02000 | |
43 | +#define DL_DOWN BIT(3) | |
44 | #define CFINIT 1 | |
45 | #define PCIETSTR 0x02004 | |
46 | #define DATA_LINK_ACTIVE 1 | |
47 | @@ -94,6 +95,7 @@ | |
48 | #define MACCTLR 0x011058 | |
49 | #define SPEED_CHANGE BIT(24) | |
50 | #define SCRAMBLE_DISABLE BIT(27) | |
51 | +#define PMSR 0x01105c | |
52 | #define MACS2R 0x011078 | |
53 | #define MACCGSPSETR 0x011084 | |
54 | #define SPCNGRSN BIT(31) | |
55 | @@ -1130,6 +1132,7 @@ static int rcar_pcie_probe(struct platfo | |
56 | pcie = pci_host_bridge_priv(bridge); | |
57 | ||
58 | pcie->dev = dev; | |
59 | + platform_set_drvdata(pdev, pcie); | |
60 | ||
61 | err = pci_parse_request_of_pci_ranges(dev, &pcie->resources, NULL); | |
62 | if (err) | |
63 | @@ -1221,10 +1224,28 @@ err_free_bridge: | |
64 | return err; | |
65 | } | |
66 | ||
67 | +static int rcar_pcie_resume_noirq(struct device *dev) | |
68 | +{ | |
69 | + struct rcar_pcie *pcie = dev_get_drvdata(dev); | |
70 | + | |
71 | + if (rcar_pci_read_reg(pcie, PMSR) && | |
72 | + !(rcar_pci_read_reg(pcie, PCIETCTLR) & DL_DOWN)) | |
73 | + return 0; | |
74 | + | |
75 | + /* Re-establish the PCIe link */ | |
76 | + rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); | |
77 | + return rcar_pcie_wait_for_dl(pcie); | |
78 | +} | |
79 | + | |
80 | +static const struct dev_pm_ops rcar_pcie_pm_ops = { | |
81 | + .resume_noirq = rcar_pcie_resume_noirq, | |
82 | +}; | |
83 | + | |
84 | static struct platform_driver rcar_pcie_driver = { | |
85 | .driver = { | |
86 | .name = "rcar-pcie", | |
87 | .of_match_table = rcar_pcie_of_match, | |
88 | + .pm = &rcar_pcie_pm_ops, | |
89 | .suppress_bind_attrs = true, | |
90 | }, | |
91 | .probe = rcar_pcie_probe, |