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Commit | Line | Data |
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3824f72d GKH |
1 | From 32d0be018f6f5ee2d5d19c4795304613560814cf Mon Sep 17 00:00:00 2001 |
2 | From: Atish Patra <atish.patra@wdc.com> | |
3 | Date: Fri, 22 Mar 2019 14:54:11 -0700 | |
4 | Subject: clocksource/drivers/riscv: Fix clocksource mask | |
5 | ||
6 | From: Atish Patra <atish.patra@wdc.com> | |
7 | ||
8 | commit 32d0be018f6f5ee2d5d19c4795304613560814cf upstream. | |
9 | ||
10 | For all riscv architectures (RV32, RV64 and RV128), the clocksource | |
11 | is a 64 bit incrementing counter. | |
12 | ||
13 | Fix the clock source mask accordingly. | |
14 | ||
15 | Tested on both 64bit and 32 bit virt machine in QEMU. | |
16 | ||
17 | Fixes: 62b019436814 ("clocksource: new RISC-V SBI timer driver") | |
18 | Signed-off-by: Atish Patra <atish.patra@wdc.com> | |
19 | Signed-off-by: Thomas Gleixner <tglx@linutronix.de> | |
20 | Reviewed-by: Anup Patel <anup@brainfault.org> | |
21 | Cc: Albert Ou <aou@eecs.berkeley.edu> | |
22 | Cc: Daniel Lezcano <daniel.lezcano@linaro.org> | |
23 | Cc: linux-riscv@lists.infradead.org | |
24 | Cc: Palmer Dabbelt <palmer@sifive.com> | |
25 | Cc: Anup Patel <Anup.Patel@wdc.com> | |
26 | Cc: Damien Le Moal <Damien.LeMoal@wdc.com> | |
27 | Cc: stable@vger.kernel.org | |
28 | Link: https://lkml.kernel.org/r/20190322215411.19362-1-atish.patra@wdc.com | |
29 | Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> | |
30 | ||
31 | --- | |
32 | drivers/clocksource/timer-riscv.c | 5 ++--- | |
33 | 1 file changed, 2 insertions(+), 3 deletions(-) | |
34 | ||
35 | --- a/drivers/clocksource/timer-riscv.c | |
36 | +++ b/drivers/clocksource/timer-riscv.c | |
37 | @@ -58,7 +58,7 @@ static u64 riscv_sched_clock(void) | |
38 | static DEFINE_PER_CPU(struct clocksource, riscv_clocksource) = { | |
39 | .name = "riscv_clocksource", | |
40 | .rating = 300, | |
41 | - .mask = CLOCKSOURCE_MASK(BITS_PER_LONG), | |
42 | + .mask = CLOCKSOURCE_MASK(64), | |
43 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
44 | .read = riscv_clocksource_rdtime, | |
45 | }; | |
46 | @@ -103,8 +103,7 @@ static int __init riscv_timer_init_dt(st | |
47 | cs = per_cpu_ptr(&riscv_clocksource, cpuid); | |
48 | clocksource_register_hz(cs, riscv_timebase); | |
49 | ||
50 | - sched_clock_register(riscv_sched_clock, | |
51 | - BITS_PER_LONG, riscv_timebase); | |
52 | + sched_clock_register(riscv_sched_clock, 64, riscv_timebase); | |
53 | ||
54 | error = cpuhp_setup_state(CPUHP_AP_RISCV_TIMER_STARTING, | |
55 | "clockevents/riscv/timer:starting", |