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3cd9d207 GKH |
1 | From c985fa2d7afdce5f7ad112dfa4ba800e4fd8bba8 Mon Sep 17 00:00:00 2001 |
2 | From: Thomas Gleixner <tglx@linutronix.de> | |
3 | Date: Fri, 1 Mar 2019 20:21:08 +0100 | |
4 | Subject: [PATCH 04/27] x86/speculation/mds: Add BUG_MSBDS_ONLY | |
5 | ||
6 | commit e261f209c3666e842fd645a1e31f001c3a26def9 upstream | |
7 | ||
8 | This bug bit is set on CPUs which are only affected by Microarchitectural | |
9 | Store Buffer Data Sampling (MSBDS) and not by any other MDS variant. | |
10 | ||
11 | This is important because the Store Buffers are partitioned between | |
12 | Hyper-Threads so cross thread forwarding is not possible. But if a thread | |
13 | enters or exits a sleep state the store buffer is repartitioned which can | |
14 | expose data from one thread to the other. This transition can be mitigated. | |
15 | ||
16 | That means that for CPUs which are only affected by MSBDS SMT can be | |
17 | enabled, if the CPU is not affected by other SMT sensitive vulnerabilities, | |
18 | e.g. L1TF. The XEON PHI variants fall into that category. Also the | |
19 | Silvermont/Airmont ATOMs, but for them it's not really relevant as they do | |
20 | not support SMT, but mark them for completeness sake. | |
21 | ||
22 | Signed-off-by: Thomas Gleixner <tglx@linutronix.de> | |
23 | Reviewed-by: Frederic Weisbecker <frederic@kernel.org> | |
24 | Reviewed-by: Jon Masters <jcm@redhat.com> | |
25 | Tested-by: Jon Masters <jcm@redhat.com> | |
26 | Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> | |
27 | --- | |
28 | arch/x86/include/asm/cpufeatures.h | 1 + | |
29 | arch/x86/kernel/cpu/common.c | 20 ++++++++++++-------- | |
30 | 2 files changed, 13 insertions(+), 8 deletions(-) | |
31 | ||
32 | diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h | |
33 | index 71375c827f4f..75f27ee2c263 100644 | |
34 | --- a/arch/x86/include/asm/cpufeatures.h | |
35 | +++ b/arch/x86/include/asm/cpufeatures.h | |
36 | @@ -384,5 +384,6 @@ | |
37 | #define X86_BUG_SPEC_STORE_BYPASS X86_BUG(17) /* CPU is affected by speculative store bypass attack */ | |
38 | #define X86_BUG_L1TF X86_BUG(18) /* CPU is affected by L1 Terminal Fault */ | |
39 | #define X86_BUG_MDS X86_BUG(19) /* CPU is affected by Microarchitectural data sampling */ | |
40 | +#define X86_BUG_MSBDS_ONLY X86_BUG(20) /* CPU is only affected by the MSDBS variant of BUG_MDS */ | |
41 | ||
42 | #endif /* _ASM_X86_CPUFEATURES_H */ | |
43 | diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c | |
44 | index e34817bca504..132a63dc5a76 100644 | |
45 | --- a/arch/x86/kernel/cpu/common.c | |
46 | +++ b/arch/x86/kernel/cpu/common.c | |
47 | @@ -953,6 +953,7 @@ static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) | |
48 | #define NO_SSB BIT(2) | |
49 | #define NO_L1TF BIT(3) | |
50 | #define NO_MDS BIT(4) | |
51 | +#define MSBDS_ONLY BIT(5) | |
52 | ||
53 | #define VULNWL(_vendor, _family, _model, _whitelist) \ | |
54 | { X86_VENDOR_##_vendor, _family, _model, X86_FEATURE_ANY, _whitelist } | |
55 | @@ -979,16 +980,16 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { | |
56 | VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION), | |
57 | VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION), | |
58 | ||
59 | - VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF), | |
60 | - VULNWL_INTEL(ATOM_SILVERMONT_X, NO_SSB | NO_L1TF), | |
61 | - VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF), | |
62 | - VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF), | |
63 | - VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF), | |
64 | - VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF), | |
65 | + VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY), | |
66 | + VULNWL_INTEL(ATOM_SILVERMONT_X, NO_SSB | NO_L1TF | MSBDS_ONLY), | |
67 | + VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY), | |
68 | + VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY), | |
69 | + VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY), | |
70 | + VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY), | |
71 | ||
72 | VULNWL_INTEL(CORE_YONAH, NO_SSB), | |
73 | ||
74 | - VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF), | |
75 | + VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY), | |
76 | ||
77 | VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF), | |
78 | VULNWL_INTEL(ATOM_GOLDMONT_X, NO_MDS | NO_L1TF), | |
79 | @@ -1033,8 +1034,11 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) | |
80 | if (ia32_cap & ARCH_CAP_IBRS_ALL) | |
81 | setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED); | |
82 | ||
83 | - if (!cpu_matches(NO_MDS) && !(ia32_cap & ARCH_CAP_MDS_NO)) | |
84 | + if (!cpu_matches(NO_MDS) && !(ia32_cap & ARCH_CAP_MDS_NO)) { | |
85 | setup_force_cpu_bug(X86_BUG_MDS); | |
86 | + if (cpu_matches(MSBDS_ONLY)) | |
87 | + setup_force_cpu_bug(X86_BUG_MSBDS_ONLY); | |
88 | + } | |
89 | ||
90 | if (cpu_matches(NO_MELTDOWN)) | |
91 | return; | |
92 | -- | |
93 | 2.21.0 | |
94 |