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Commit | Line | Data |
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08fa46a8 GKH |
1 | From foo@baz Tue Mar 8 08:47:19 PM CET 2022 |
2 | From: Joey Gouly <joey.gouly@arm.com> | |
3 | Date: Fri, 10 Dec 2021 16:54:31 +0000 | |
4 | Subject: arm64: add ID_AA64ISAR2_EL1 sys register | |
5 | ||
6 | From: Joey Gouly <joey.gouly@arm.com> | |
7 | ||
8 | commit 9e45365f1469ef2b934f9d035975dbc9ad352116 upstream. | |
9 | ||
10 | This is a new ID register, introduced in 8.7. | |
11 | ||
12 | Signed-off-by: Joey Gouly <joey.gouly@arm.com> | |
13 | Cc: Will Deacon <will@kernel.org> | |
14 | Cc: Marc Zyngier <maz@kernel.org> | |
15 | Cc: James Morse <james.morse@arm.com> | |
16 | Cc: Alexandru Elisei <alexandru.elisei@arm.com> | |
17 | Cc: Suzuki K Poulose <suzuki.poulose@arm.com> | |
18 | Cc: Reiji Watanabe <reijiw@google.com> | |
19 | Acked-by: Marc Zyngier <maz@kernel.org> | |
20 | Link: https://lore.kernel.org/r/20211210165432.8106-3-joey.gouly@arm.com | |
21 | Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> | |
22 | Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> | |
23 | --- | |
24 | arch/arm64/include/asm/cpu.h | 1 + | |
25 | arch/arm64/include/asm/sysreg.h | 15 +++++++++++++++ | |
26 | arch/arm64/kernel/cpufeature.c | 9 +++++++++ | |
27 | arch/arm64/kernel/cpuinfo.c | 1 + | |
28 | arch/arm64/kvm/sys_regs.c | 2 +- | |
29 | 5 files changed, 27 insertions(+), 1 deletion(-) | |
30 | ||
31 | --- a/arch/arm64/include/asm/cpu.h | |
32 | +++ b/arch/arm64/include/asm/cpu.h | |
33 | @@ -51,6 +51,7 @@ struct cpuinfo_arm64 { | |
34 | u64 reg_id_aa64dfr1; | |
35 | u64 reg_id_aa64isar0; | |
36 | u64 reg_id_aa64isar1; | |
37 | + u64 reg_id_aa64isar2; | |
38 | u64 reg_id_aa64mmfr0; | |
39 | u64 reg_id_aa64mmfr1; | |
40 | u64 reg_id_aa64mmfr2; | |
41 | --- a/arch/arm64/include/asm/sysreg.h | |
42 | +++ b/arch/arm64/include/asm/sysreg.h | |
43 | @@ -180,6 +180,7 @@ | |
44 | ||
45 | #define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0) | |
46 | #define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1) | |
47 | +#define SYS_ID_AA64ISAR2_EL1 sys_reg(3, 0, 0, 6, 2) | |
48 | ||
49 | #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0) | |
50 | #define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1) | |
51 | @@ -764,6 +765,20 @@ | |
52 | #define ID_AA64ISAR1_GPI_NI 0x0 | |
53 | #define ID_AA64ISAR1_GPI_IMP_DEF 0x1 | |
54 | ||
55 | +/* id_aa64isar2 */ | |
56 | +#define ID_AA64ISAR2_RPRES_SHIFT 4 | |
57 | +#define ID_AA64ISAR2_WFXT_SHIFT 0 | |
58 | + | |
59 | +#define ID_AA64ISAR2_RPRES_8BIT 0x0 | |
60 | +#define ID_AA64ISAR2_RPRES_12BIT 0x1 | |
61 | +/* | |
62 | + * Value 0x1 has been removed from the architecture, and is | |
63 | + * reserved, but has not yet been removed from the ARM ARM | |
64 | + * as of ARM DDI 0487G.b. | |
65 | + */ | |
66 | +#define ID_AA64ISAR2_WFXT_NI 0x0 | |
67 | +#define ID_AA64ISAR2_WFXT_SUPPORTED 0x2 | |
68 | + | |
69 | /* id_aa64pfr0 */ | |
70 | #define ID_AA64PFR0_CSV3_SHIFT 60 | |
71 | #define ID_AA64PFR0_CSV2_SHIFT 56 | |
72 | --- a/arch/arm64/kernel/cpufeature.c | |
73 | +++ b/arch/arm64/kernel/cpufeature.c | |
74 | @@ -225,6 +225,10 @@ static const struct arm64_ftr_bits ftr_i | |
75 | ARM64_FTR_END, | |
76 | }; | |
77 | ||
78 | +static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { | |
79 | + ARM64_FTR_END, | |
80 | +}; | |
81 | + | |
82 | static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { | |
83 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0), | |
84 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0), | |
85 | @@ -637,6 +641,7 @@ static const struct __ftr_reg_entry { | |
86 | ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), | |
87 | ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1, | |
88 | &id_aa64isar1_override), | |
89 | + ARM64_FTR_REG(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2), | |
90 | ||
91 | /* Op1 = 0, CRn = 0, CRm = 7 */ | |
92 | ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0), | |
93 | @@ -933,6 +938,7 @@ void __init init_cpu_features(struct cpu | |
94 | init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); | |
95 | init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); | |
96 | init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); | |
97 | + init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2); | |
98 | init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); | |
99 | init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); | |
100 | init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); | |
101 | @@ -1151,6 +1157,8 @@ void update_cpu_features(int cpu, | |
102 | info->reg_id_aa64isar0, boot->reg_id_aa64isar0); | |
103 | taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, | |
104 | info->reg_id_aa64isar1, boot->reg_id_aa64isar1); | |
105 | + taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu, | |
106 | + info->reg_id_aa64isar2, boot->reg_id_aa64isar2); | |
107 | ||
108 | /* | |
109 | * Differing PARange support is fine as long as all peripherals and | |
110 | @@ -1272,6 +1280,7 @@ u64 __read_sysreg_by_encoding(u32 sys_id | |
111 | read_sysreg_case(SYS_ID_AA64MMFR2_EL1); | |
112 | read_sysreg_case(SYS_ID_AA64ISAR0_EL1); | |
113 | read_sysreg_case(SYS_ID_AA64ISAR1_EL1); | |
114 | + read_sysreg_case(SYS_ID_AA64ISAR2_EL1); | |
115 | ||
116 | read_sysreg_case(SYS_CNTFRQ_EL0); | |
117 | read_sysreg_case(SYS_CTR_EL0); | |
118 | --- a/arch/arm64/kernel/cpuinfo.c | |
119 | +++ b/arch/arm64/kernel/cpuinfo.c | |
120 | @@ -391,6 +391,7 @@ static void __cpuinfo_store_cpu(struct c | |
121 | info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1); | |
122 | info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1); | |
123 | info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1); | |
124 | + info->reg_id_aa64isar2 = read_cpuid(ID_AA64ISAR2_EL1); | |
125 | info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); | |
126 | info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); | |
127 | info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1); | |
128 | --- a/arch/arm64/kvm/sys_regs.c | |
129 | +++ b/arch/arm64/kvm/sys_regs.c | |
130 | @@ -1518,7 +1518,7 @@ static const struct sys_reg_desc sys_reg | |
131 | /* CRm=6 */ | |
132 | ID_SANITISED(ID_AA64ISAR0_EL1), | |
133 | ID_SANITISED(ID_AA64ISAR1_EL1), | |
134 | - ID_UNALLOCATED(6,2), | |
135 | + ID_SANITISED(ID_AA64ISAR2_EL1), | |
136 | ID_UNALLOCATED(6,3), | |
137 | ID_UNALLOCATED(6,4), | |
138 | ID_UNALLOCATED(6,5), |