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Drop nfc patches from older trees
[thirdparty/kernel/stable-queue.git] / releases / 5.2.19 / mmc-sdhci-fix-incorrect-switch-to-hs-mode.patch
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1From 5a433a915be47c7b5aa8eea21d70b7b086b1a793 Mon Sep 17 00:00:00 2001
2From: Sasha Levin <sashal@kernel.org>
3Date: Tue, 3 Sep 2019 07:51:14 -0400
4Subject: mmc: sdhci: Fix incorrect switch to HS mode
5
6From: Al Cooper <alcooperx@gmail.com>
7
8[ Upstream commit c894e33ddc1910e14d6f2a2016f60ab613fd8b37 ]
9
10When switching from any MMC speed mode that requires 1.8v
11(HS200, HS400 and HS400ES) to High Speed (HS) mode, the system
12ends up configured for SDR12 with a 50MHz clock which is an illegal
13mode.
14
15This happens because the SDHCI_CTRL_VDD_180 bit in the
16SDHCI_HOST_CONTROL2 register is left set and when this bit is
17set, the speed mode is controlled by the SDHCI_CTRL_UHS field
18in the SDHCI_HOST_CONTROL2 register. The SDHCI_CTRL_UHS field
19will end up being set to 0 (SDR12) by sdhci_set_uhs_signaling()
20because there is no UHS mode being set.
21
22The fix is to change sdhci_set_uhs_signaling() to set the
23SDHCI_CTRL_UHS field to SDR25 (which is the same as HS) for
24any switch to HS mode.
25
26This was found on a new eMMC controller that does strict checking
27of the speed mode and the corresponding clock rate. It caused the
28switch to HS400 mode to fail because part of the sequence to switch
29to HS400 requires a switch from HS200 to HS before going to HS400.
30
31Suggested-by: Adrian Hunter <adrian.hunter@intel.com>
32Signed-off-by: Al Cooper <alcooperx@gmail.com>
33Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
34Signed-off-by: Sasha Levin <sashal@kernel.org>
35---
36 drivers/mmc/host/sdhci.c | 4 +++-
37 1 file changed, 3 insertions(+), 1 deletion(-)
38
39diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
40index a5dc5aae973e6..c66e66fbaeb40 100644
41--- a/drivers/mmc/host/sdhci.c
42+++ b/drivers/mmc/host/sdhci.c
43@@ -1849,7 +1849,9 @@ void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
44 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
45 else if (timing == MMC_TIMING_UHS_SDR12)
46 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
47- else if (timing == MMC_TIMING_UHS_SDR25)
48+ else if (timing == MMC_TIMING_SD_HS ||
49+ timing == MMC_TIMING_MMC_HS ||
50+ timing == MMC_TIMING_UHS_SDR25)
51 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
52 else if (timing == MMC_TIMING_UHS_SDR50)
53 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
54--
552.20.1
56