projects / thirdparty / kernel / stable-queue.git / blame
| Commit | Line | Data |
|---|---|---|
| 7e19d03b SL |
1 | From 9f9f3f0d764a6c0c9462e9e05b2da5be458c9b17 Mon Sep 17 00:00:00 2001 |
| 2 | From: Sasha Levin <sashal@kernel.org> | |
| 3 | Date: Wed, 17 Jan 2024 16:46:02 -0500 | |
| 4 | Subject: drm/amd/display: Fix DPSTREAM CLK on and off sequence | |
| 5 | ||
| 6 | From: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> | |
| 7 | ||
| 8 | [ Upstream commit e8d131285c98927554cd007f47cedc4694bfedde ] | |
| 9 | ||
| 10 | [Why] | |
| 11 | Secondary DP2 display fails to light up in some instances | |
| 12 | ||
| 13 | [How] | |
| 14 | Clock needs to be on when DPSTREAMCLK*_EN =1. This change | |
| 15 | moves dtbclk_p enable/disable point to make sure this is | |
| 16 | the case | |
| 17 | ||
| 18 | Reviewed-by: Charlene Liu <charlene.liu@amd.com> | |
| 19 | Reviewed-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> | |
| 20 | Acked-by: Tom Chung <chiahsuan.chung@amd.com> | |
| 21 | Signed-off-by: Daniel Miess <daniel.miess@amd.com> | |
| 22 | Signed-off-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> | |
| 23 | Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> | |
| 24 | Signed-off-by: Alex Deucher <alexander.deucher@amd.com> | |
| 25 | Stable-dep-of: 72d72e8fddbc ("drm/amd/display: Prevent crash when disable stream") | |
| 26 | Signed-off-by: Sasha Levin <sashal@kernel.org> | |
| 27 | --- | |
| 28 | .../drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 2 +- | |
| 29 | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 11 +++++------ | |
| 30 | 2 files changed, 6 insertions(+), 7 deletions(-) | |
| 31 | ||
| 32 | diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | |
| 33 | index 251dd800a2a66..2ac41c2a7238c 100644 | |
| 34 | --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | |
| 35 | +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | |
| 36 | @@ -1179,9 +1179,9 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx) | |
| 37 | dto_params.timing = &pipe_ctx->stream->timing; | |
| 38 | dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst; | |
| 39 | if (dccg) { | |
| 40 | - dccg->funcs->set_dtbclk_dto(dccg, &dto_params); | |
| 41 | dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst); | |
| 42 | dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, dp_hpo_inst); | |
| 43 | + dccg->funcs->set_dtbclk_dto(dccg, &dto_params); | |
| 44 | } | |
| 45 | } else if (dccg && dccg->funcs->disable_symclk_se) { | |
| 46 | dccg->funcs->disable_symclk_se(dccg, stream_enc->stream_enc_inst, | |
| 47 | diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | |
| 48 | index 1e3803739ae61..12af2859002f7 100644 | |
| 49 | --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | |
| 50 | +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | |
| 51 | @@ -2728,18 +2728,17 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx) | |
| 52 | } | |
| 53 | ||
| 54 | if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { | |
| 55 | - dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst; | |
| 56 | - dccg->funcs->set_dpstreamclk(dccg, DTBCLK0, tg->inst, dp_hpo_inst); | |
| 57 | - | |
| 58 | - phyd32clk = get_phyd32clk_src(link); | |
| 59 | - dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk); | |
| 60 | - | |
| 61 | dto_params.otg_inst = tg->inst; | |
| 62 | dto_params.pixclk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10; | |
| 63 | dto_params.num_odm_segments = get_odm_segment_count(pipe_ctx); | |
| 64 | dto_params.timing = &pipe_ctx->stream->timing; | |
| 65 | dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr); | |
| 66 | dccg->funcs->set_dtbclk_dto(dccg, &dto_params); | |
| 67 | + dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst; | |
| 68 | + dccg->funcs->set_dpstreamclk(dccg, DTBCLK0, tg->inst, dp_hpo_inst); | |
| 69 | + | |
| 70 | + phyd32clk = get_phyd32clk_src(link); | |
| 71 | + dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk); | |
| 72 | } else { | |
| 73 | } | |
| 74 | if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) { | |
| 75 | -- | |
| 76 | 2.43.0 | |
| 77 |