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1 | From be0e34af5ba1762d8fef2004f311776ee45303af Mon Sep 17 00:00:00 2001 |
2 | From: Sasha Levin <sashal@kernel.org> | |
3 | Date: Mon, 21 Aug 2023 11:06:23 -0700 | |
4 | Subject: drm/i915/xelpg: Call Xe_LPG workaround functions based on IP version | |
5 | ||
6 | From: Matt Roper <matthew.d.roper@intel.com> | |
7 | ||
8 | [ Upstream commit f7696ded7c9e358670dae1801660f442f059c7db ] | |
9 | ||
10 | Although some of our Xe_LPG workarounds were already being applied based | |
11 | on IP version correctly, others were matching on MTL as a base platform, | |
12 | which is incorrect. Although MTL is the only platform right now that | |
13 | uses Xe_LPG IP, this may not always be the case. If a future platform | |
14 | re-uses this graphics IP, the same workarounds should be applied, even | |
15 | if it isn't a "MTL" platform. | |
16 | ||
17 | We were also incorrectly applying Xe_LPG workarounds/tuning to the | |
18 | Xe_LPM+ media IP in one or two places; we should make sure that we don't | |
19 | try to apply graphics workarounds to the media GT and vice versa where | |
20 | they don't belong. A new helper macro IS_GT_IP_RANGE() is added to help | |
21 | ensure this is handled properly -- it checks that the GT matches the IP | |
22 | type being tested as well as the IP version falling in the proper range. | |
23 | ||
24 | Note that many of the stepping-based workarounds are still incorrectly | |
25 | checking for a MTL base platform; that will be remedied in a later | |
26 | patch. | |
27 | ||
28 | v2: | |
29 | - Rework macro into a slightly more generic IS_GT_IP_RANGE() that can | |
30 | be used for either GFX or MEDIA checks. | |
31 | ||
32 | v3: | |
33 | - Switch back to separate macros for gfx and media. (Jani) | |
34 | - Move macro to intel_gt.h. (Andi) | |
35 | ||
36 | Cc: Gustavo Sousa <gustavo.sousa@intel.com> | |
37 | Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> | |
38 | Cc: Jani Nikula <jani.nikula@linux.intel.com> | |
39 | Cc: Andi Shyti <andi.shyti@linux.intel.com> | |
40 | Signed-off-by: Matt Roper <matthew.d.roper@intel.com> | |
41 | Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> | |
42 | Link: https://patchwork.freedesktop.org/patch/msgid/20230821180619.650007-14-matthew.d.roper@intel.com | |
43 | Stable-dep-of: 186bce682772 ("drm/i915/mtl: Update workaround 14018575942") | |
44 | Signed-off-by: Sasha Levin <sashal@kernel.org> | |
45 | --- | |
46 | drivers/gpu/drm/i915/gt/intel_gt.h | 11 ++++++ | |
47 | drivers/gpu/drm/i915/gt/intel_workarounds.c | 38 +++++++++++---------- | |
48 | 2 files changed, 31 insertions(+), 18 deletions(-) | |
49 | ||
50 | diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h | |
51 | index 6c34547b58b59..15c25980411db 100644 | |
52 | --- a/drivers/gpu/drm/i915/gt/intel_gt.h | |
53 | +++ b/drivers/gpu/drm/i915/gt/intel_gt.h | |
54 | @@ -14,6 +14,17 @@ | |
55 | struct drm_i915_private; | |
56 | struct drm_printer; | |
57 | ||
58 | +/* | |
59 | + * Check that the GT is a graphics GT and has an IP version within the | |
60 | + * specified range (inclusive). | |
61 | + */ | |
62 | +#define IS_GFX_GT_IP_RANGE(gt, from, until) ( \ | |
63 | + BUILD_BUG_ON_ZERO((from) < IP_VER(2, 0)) + \ | |
64 | + BUILD_BUG_ON_ZERO((until) < (from)) + \ | |
65 | + ((gt)->type != GT_MEDIA && \ | |
66 | + GRAPHICS_VER_FULL((gt)->i915) >= (from) && \ | |
67 | + GRAPHICS_VER_FULL((gt)->i915) <= (until))) | |
68 | + | |
69 | #define GT_TRACE(gt, fmt, ...) do { \ | |
70 | const struct intel_gt *gt__ __maybe_unused = (gt); \ | |
71 | GEM_TRACE("%s " fmt, dev_name(gt__->i915->drm.dev), \ | |
72 | diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c | |
73 | index 69973dc518280..4c24f3897aee1 100644 | |
74 | --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c | |
75 | +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c | |
76 | @@ -781,8 +781,8 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine, | |
77 | wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE); | |
78 | } | |
79 | ||
80 | -static void mtl_ctx_gt_tuning_init(struct intel_engine_cs *engine, | |
81 | - struct i915_wa_list *wal) | |
82 | +static void xelpg_ctx_gt_tuning_init(struct intel_engine_cs *engine, | |
83 | + struct i915_wa_list *wal) | |
84 | { | |
85 | struct drm_i915_private *i915 = engine->i915; | |
86 | ||
87 | @@ -793,12 +793,12 @@ static void mtl_ctx_gt_tuning_init(struct intel_engine_cs *engine, | |
88 | wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false); | |
89 | } | |
90 | ||
91 | -static void mtl_ctx_workarounds_init(struct intel_engine_cs *engine, | |
92 | - struct i915_wa_list *wal) | |
93 | +static void xelpg_ctx_workarounds_init(struct intel_engine_cs *engine, | |
94 | + struct i915_wa_list *wal) | |
95 | { | |
96 | struct drm_i915_private *i915 = engine->i915; | |
97 | ||
98 | - mtl_ctx_gt_tuning_init(engine, wal); | |
99 | + xelpg_ctx_gt_tuning_init(engine, wal); | |
100 | ||
101 | if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || | |
102 | IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) { | |
103 | @@ -907,8 +907,8 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, | |
104 | if (engine->class != RENDER_CLASS) | |
105 | goto done; | |
106 | ||
107 | - if (IS_METEORLAKE(i915)) | |
108 | - mtl_ctx_workarounds_init(engine, wal); | |
109 | + if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 71))) | |
110 | + xelpg_ctx_workarounds_init(engine, wal); | |
111 | else if (IS_PONTEVECCHIO(i915)) | |
112 | ; /* noop; none at this time */ | |
113 | else if (IS_DG2(i915)) | |
114 | @@ -1688,10 +1688,8 @@ xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) | |
115 | */ | |
116 | static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal) | |
117 | { | |
118 | - if (IS_METEORLAKE(gt->i915)) { | |
119 | - if (gt->type != GT_MEDIA) | |
120 | - wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS); | |
121 | - | |
122 | + if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71))) { | |
123 | + wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS); | |
124 | wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS); | |
125 | } | |
126 | ||
127 | @@ -1723,7 +1721,7 @@ gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal) | |
128 | return; | |
129 | } | |
130 | ||
131 | - if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) | |
132 | + if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71))) | |
133 | xelpg_gt_workarounds_init(gt, wal); | |
134 | else if (IS_PONTEVECCHIO(i915)) | |
135 | pvc_gt_workarounds_init(gt, wal); | |
136 | @@ -2172,7 +2170,7 @@ static void pvc_whitelist_build(struct intel_engine_cs *engine) | |
137 | blacklist_trtt(engine); | |
138 | } | |
139 | ||
140 | -static void mtl_whitelist_build(struct intel_engine_cs *engine) | |
141 | +static void xelpg_whitelist_build(struct intel_engine_cs *engine) | |
142 | { | |
143 | struct i915_wa_list *w = &engine->whitelist; | |
144 | ||
145 | @@ -2194,8 +2192,10 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine) | |
146 | ||
147 | wa_init_start(w, engine->gt, "whitelist", engine->name); | |
148 | ||
149 | - if (IS_METEORLAKE(i915)) | |
150 | - mtl_whitelist_build(engine); | |
151 | + if (engine->gt->type == GT_MEDIA) | |
152 | + ; /* none yet */ | |
153 | + else if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 71))) | |
154 | + xelpg_whitelist_build(engine); | |
155 | else if (IS_PONTEVECCHIO(i915)) | |
156 | pvc_whitelist_build(engine); | |
157 | else if (IS_DG2(i915)) | |
158 | @@ -2795,10 +2795,12 @@ ccs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) | |
159 | * function invoked by __intel_engine_init_ctx_wa(). | |
160 | */ | |
161 | static void | |
162 | -add_render_compute_tuning_settings(struct drm_i915_private *i915, | |
163 | +add_render_compute_tuning_settings(struct intel_gt *gt, | |
164 | struct i915_wa_list *wal) | |
165 | { | |
166 | - if (IS_METEORLAKE(i915) || IS_DG2(i915)) | |
167 | + struct drm_i915_private *i915 = gt->i915; | |
168 | + | |
169 | + if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) || IS_DG2(i915)) | |
170 | wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512); | |
171 | ||
172 | /* | |
173 | @@ -2828,7 +2830,7 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li | |
174 | { | |
175 | struct drm_i915_private *i915 = engine->i915; | |
176 | ||
177 | - add_render_compute_tuning_settings(i915, wal); | |
178 | + add_render_compute_tuning_settings(engine->gt, wal); | |
179 | ||
180 | if (GRAPHICS_VER(i915) >= 11) { | |
181 | /* This is not a Wa (although referred to as | |
182 | -- | |
183 | 2.43.0 | |
184 |