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b34f6357 | 1 | /* frv trap support |
3666a048 | 2 | Copyright (C) 1999-2021 Free Software Foundation, Inc. |
b34f6357 DB |
3 | Contributed by Red Hat. |
4 | ||
5 | This file is part of the GNU simulators. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
4744ac1b JB |
9 | the Free Software Foundation; either version 3 of the License, or |
10 | (at your option) any later version. | |
b34f6357 DB |
11 | |
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
4744ac1b JB |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
b34f6357 | 19 | |
6df01ab8 MF |
20 | /* This must come before any other includes. */ |
21 | #include "defs.h" | |
22 | ||
b34f6357 DB |
23 | #define WANT_CPU frvbf |
24 | #define WANT_CPU_FRVBF | |
25 | ||
26 | #include "sim-main.h" | |
27 | #include "targ-vals.h" | |
28 | #include "cgen-engine.h" | |
29 | #include "cgen-par.h" | |
30 | #include "sim-fpu.h" | |
1fef66b0 | 31 | #include "sim-signal.h" |
ef5058ae | 32 | #include "sim/callback.h" |
b34f6357 DB |
33 | |
34 | #include "bfd.h" | |
35 | #include "libiberty.h" | |
36 | ||
32a046ab TT |
37 | #include <stdlib.h> |
38 | ||
79e59fe6 | 39 | CGEN_ATTR_VALUE_ENUM_TYPE frv_current_fm_slot; |
e930b1f5 | 40 | |
b34f6357 DB |
41 | /* The semantic code invokes this for invalid (unrecognized) instructions. */ |
42 | ||
43 | SEM_PC | |
44 | sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia, SEM_PC vpc) | |
45 | { | |
46 | frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); | |
47 | return vpc; | |
48 | } | |
49 | ||
50 | /* Process an address exception. */ | |
51 | ||
52 | void | |
53 | frv_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia, | |
54 | unsigned int map, int nr_bytes, address_word addr, | |
55 | transfer_type transfer, sim_core_signals sig) | |
56 | { | |
57 | if (sig == sim_core_unaligned_signal) | |
58 | { | |
676a64f4 RS |
59 | if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400 |
60 | || STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr450) | |
b34f6357 DB |
61 | frv_queue_data_access_error_interrupt (current_cpu, addr); |
62 | else | |
63 | frv_queue_mem_address_not_aligned_interrupt (current_cpu, addr); | |
64 | } | |
65 | ||
66 | frv_term (sd); | |
67 | sim_core_signal (sd, current_cpu, cia, map, nr_bytes, addr, transfer, sig); | |
68 | } | |
69 | ||
70 | void | |
71 | frv_sim_engine_halt_hook (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia) | |
72 | { | |
73 | int i; | |
74 | if (current_cpu != NULL) | |
034685f9 | 75 | CPU_PC_SET (current_cpu, cia); |
b34f6357 DB |
76 | |
77 | /* Invalidate the insn and data caches of all cpus. */ | |
78 | for (i = 0; i < MAX_NR_PROCESSORS; ++i) | |
79 | { | |
80 | current_cpu = STATE_CPU (sd, i); | |
81 | frv_cache_invalidate_all (CPU_INSN_CACHE (current_cpu), 0); | |
82 | frv_cache_invalidate_all (CPU_DATA_CACHE (current_cpu), 1); | |
83 | } | |
84 | frv_term (sd); | |
85 | } | |
86 | \f | |
87 | /* Read/write functions for system call interface. */ | |
88 | ||
89 | static int | |
90 | syscall_read_mem (host_callback *cb, struct cb_syscall *sc, | |
91 | unsigned long taddr, char *buf, int bytes) | |
92 | { | |
93 | SIM_DESC sd = (SIM_DESC) sc->p1; | |
94 | SIM_CPU *cpu = (SIM_CPU *) sc->p2; | |
95 | ||
96 | frv_cache_invalidate_all (CPU_DATA_CACHE (cpu), 1); | |
97 | return sim_core_read_buffer (sd, cpu, read_map, buf, taddr, bytes); | |
98 | } | |
99 | ||
100 | static int | |
101 | syscall_write_mem (host_callback *cb, struct cb_syscall *sc, | |
102 | unsigned long taddr, const char *buf, int bytes) | |
103 | { | |
104 | SIM_DESC sd = (SIM_DESC) sc->p1; | |
105 | SIM_CPU *cpu = (SIM_CPU *) sc->p2; | |
106 | ||
107 | frv_cache_invalidate_all (CPU_INSN_CACHE (cpu), 0); | |
108 | frv_cache_invalidate_all (CPU_DATA_CACHE (cpu), 1); | |
109 | return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes); | |
110 | } | |
111 | ||
112 | /* Handle TRA and TIRA insns. */ | |
113 | void | |
114 | frv_itrap (SIM_CPU *current_cpu, PCADDR pc, USI base, SI offset) | |
115 | { | |
116 | SIM_DESC sd = CPU_STATE (current_cpu); | |
117 | host_callback *cb = STATE_CALLBACK (sd); | |
118 | USI num = ((base + offset) & 0x7f) + 0x80; | |
119 | ||
b34f6357 DB |
120 | if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT) |
121 | { | |
122 | frv_queue_software_interrupt (current_cpu, num); | |
123 | return; | |
124 | } | |
125 | ||
126 | switch (num) | |
127 | { | |
128 | case TRAP_SYSCALL : | |
129 | { | |
130 | CB_SYSCALL s; | |
131 | CB_SYSCALL_INIT (&s); | |
132 | s.func = GET_H_GR (7); | |
133 | s.arg1 = GET_H_GR (8); | |
134 | s.arg2 = GET_H_GR (9); | |
135 | s.arg3 = GET_H_GR (10); | |
136 | ||
137 | if (s.func == TARGET_SYS_exit) | |
138 | { | |
139 | sim_engine_halt (sd, current_cpu, NULL, pc, sim_exited, s.arg1); | |
140 | } | |
141 | ||
142 | s.p1 = (PTR) sd; | |
143 | s.p2 = (PTR) current_cpu; | |
144 | s.read_mem = syscall_read_mem; | |
145 | s.write_mem = syscall_write_mem; | |
146 | cb_syscall (cb, &s); | |
147 | SET_H_GR (8, s.result); | |
148 | SET_H_GR (9, s.result2); | |
149 | SET_H_GR (10, s.errcode); | |
150 | break; | |
151 | } | |
152 | ||
153 | case TRAP_BREAKPOINT: | |
154 | sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP); | |
155 | break; | |
156 | ||
157 | /* Add support for dumping registers, either at fixed traps, or all | |
158 | unknown traps if configured with --enable-sim-trapdump. */ | |
159 | default: | |
160 | #if !TRAPDUMP | |
161 | frv_queue_software_interrupt (current_cpu, num); | |
162 | return; | |
163 | #endif | |
164 | ||
165 | #ifdef TRAP_REGDUMP1 | |
166 | case TRAP_REGDUMP1: | |
167 | #endif | |
168 | ||
169 | #ifdef TRAP_REGDUMP2 | |
170 | case TRAP_REGDUMP2: | |
171 | #endif | |
172 | ||
173 | #if TRAPDUMP || (defined (TRAP_REGDUMP1)) || (defined (TRAP_REGDUMP2)) | |
174 | { | |
175 | char buf[256]; | |
176 | int i, j; | |
177 | ||
178 | buf[0] = 0; | |
179 | if (STATE_TEXT_SECTION (sd) | |
180 | && pc >= STATE_TEXT_START (sd) | |
181 | && pc < STATE_TEXT_END (sd)) | |
182 | { | |
183 | const char *pc_filename = (const char *)0; | |
184 | const char *pc_function = (const char *)0; | |
185 | unsigned int pc_linenum = 0; | |
186 | ||
187 | if (bfd_find_nearest_line (STATE_PROG_BFD (sd), | |
188 | STATE_TEXT_SECTION (sd), | |
fc0a2244 | 189 | (struct bfd_symbol **) 0, |
b34f6357 DB |
190 | pc - STATE_TEXT_START (sd), |
191 | &pc_filename, &pc_function, &pc_linenum) | |
192 | && (pc_function || pc_filename)) | |
193 | { | |
194 | char *p = buf+2; | |
195 | buf[0] = ' '; | |
196 | buf[1] = '('; | |
197 | if (pc_function) | |
198 | { | |
199 | strcpy (p, pc_function); | |
200 | p += strlen (p); | |
201 | } | |
202 | else | |
203 | { | |
204 | char *q = (char *) strrchr (pc_filename, '/'); | |
205 | strcpy (p, (q) ? q+1 : pc_filename); | |
206 | p += strlen (p); | |
207 | } | |
208 | ||
209 | if (pc_linenum) | |
210 | { | |
211 | sprintf (p, " line %d", pc_linenum); | |
212 | p += strlen (p); | |
213 | } | |
214 | ||
215 | p[0] = ')'; | |
216 | p[1] = '\0'; | |
217 | if ((p+1) - buf > sizeof (buf)) | |
218 | abort (); | |
219 | } | |
220 | } | |
221 | ||
222 | sim_io_printf (sd, | |
223 | "\nRegister dump, pc = 0x%.8x%s, base = %u, offset = %d\n", | |
224 | (unsigned)pc, buf, (unsigned)base, (int)offset); | |
225 | ||
226 | for (i = 0; i < 64; i += 8) | |
227 | { | |
228 | long g0 = (long)GET_H_GR (i); | |
229 | long g1 = (long)GET_H_GR (i+1); | |
230 | long g2 = (long)GET_H_GR (i+2); | |
231 | long g3 = (long)GET_H_GR (i+3); | |
232 | long g4 = (long)GET_H_GR (i+4); | |
233 | long g5 = (long)GET_H_GR (i+5); | |
234 | long g6 = (long)GET_H_GR (i+6); | |
235 | long g7 = (long)GET_H_GR (i+7); | |
236 | ||
237 | if ((g0 | g1 | g2 | g3 | g4 | g5 | g6 | g7) != 0) | |
238 | sim_io_printf (sd, | |
239 | "\tgr%02d - gr%02d: 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx\n", | |
240 | i, i+7, g0, g1, g2, g3, g4, g5, g6, g7); | |
241 | } | |
242 | ||
243 | for (i = 0; i < 64; i += 8) | |
244 | { | |
245 | long f0 = (long)GET_H_FR (i); | |
246 | long f1 = (long)GET_H_FR (i+1); | |
247 | long f2 = (long)GET_H_FR (i+2); | |
248 | long f3 = (long)GET_H_FR (i+3); | |
249 | long f4 = (long)GET_H_FR (i+4); | |
250 | long f5 = (long)GET_H_FR (i+5); | |
251 | long f6 = (long)GET_H_FR (i+6); | |
252 | long f7 = (long)GET_H_FR (i+7); | |
253 | ||
254 | if ((f0 | f1 | f2 | f3 | f4 | f5 | f6 | f7) != 0) | |
255 | sim_io_printf (sd, | |
256 | "\tfr%02d - fr%02d: 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx\n", | |
257 | i, i+7, f0, f1, f2, f3, f4, f5, f6, f7); | |
258 | } | |
259 | ||
260 | sim_io_printf (sd, | |
261 | "\tlr/lcr/cc/ccc: 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx\n", | |
262 | (long)GET_H_SPR (272), | |
263 | (long)GET_H_SPR (273), | |
264 | (long)GET_H_SPR (256), | |
265 | (long)GET_H_SPR (263)); | |
266 | } | |
267 | break; | |
268 | #endif | |
269 | } | |
270 | } | |
271 | ||
272 | /* Handle the MTRAP insn. */ | |
273 | void | |
274 | frv_mtrap (SIM_CPU *current_cpu) | |
275 | { | |
e930b1f5 DB |
276 | SIM_DESC sd = CPU_STATE (current_cpu); |
277 | ||
b34f6357 DB |
278 | /* Check the status of media exceptions in MSR0. */ |
279 | SI msr = GET_MSR (0); | |
fc12ae42 MF |
280 | if (GET_MSR_AOVF (msr) |
281 | || (GET_MSR_MTT (msr) && STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550)) | |
b34f6357 DB |
282 | frv_queue_program_interrupt (current_cpu, FRV_MP_EXCEPTION); |
283 | } | |
284 | ||
285 | /* Handle the BREAK insn. */ | |
286 | void | |
287 | frv_break (SIM_CPU *current_cpu) | |
288 | { | |
289 | IADDR pc; | |
290 | SIM_DESC sd = CPU_STATE (current_cpu); | |
291 | ||
b34f6357 DB |
292 | if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT) |
293 | { | |
294 | /* Invalidate the insn cache because the debugger will presumably | |
295 | replace the breakpoint insn with the real one. */ | |
b34f6357 DB |
296 | sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP); |
297 | } | |
298 | ||
299 | frv_queue_break_interrupt (current_cpu); | |
300 | } | |
301 | ||
302 | /* Return from trap. */ | |
303 | USI | |
304 | frv_rett (SIM_CPU *current_cpu, PCADDR pc, BI debug_field) | |
305 | { | |
306 | USI new_pc; | |
307 | /* if (normal running mode and debug_field==0 | |
308 | PC=PCSR | |
309 | PSR.ET=1 | |
310 | PSR.S=PSR.PS | |
311 | else if (debug running mode and debug_field==1) | |
312 | PC=(BPCSR) | |
313 | PSR.ET=BPSR.BET | |
314 | PSR.S=BPSR.BS | |
315 | change to normal running mode | |
316 | */ | |
317 | int psr_s = GET_H_PSR_S (); | |
318 | int psr_et = GET_H_PSR_ET (); | |
319 | ||
320 | /* Check for exceptions in the priority order listed in the FRV Architecture | |
321 | Volume 2. */ | |
322 | if (! psr_s) | |
323 | { | |
324 | /* Halt if PSR.ET is not set. See chapter 6 of the LSI. */ | |
325 | if (! psr_et) | |
326 | { | |
327 | SIM_DESC sd = CPU_STATE (current_cpu); | |
328 | sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP); | |
329 | } | |
330 | ||
331 | /* privileged_instruction interrupt will have already been queued by | |
332 | frv_detect_insn_access_interrupts. */ | |
333 | new_pc = pc + 4; | |
334 | } | |
335 | else if (psr_et) | |
336 | { | |
337 | /* Halt if PSR.S is set. See chapter 6 of the LSI. */ | |
338 | if (psr_s) | |
339 | { | |
340 | SIM_DESC sd = CPU_STATE (current_cpu); | |
341 | sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP); | |
342 | } | |
343 | ||
344 | frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); | |
345 | new_pc = pc + 4; | |
346 | } | |
347 | else if (! CPU_DEBUG_STATE (current_cpu) && debug_field == 0) | |
348 | { | |
349 | USI psr = GET_PSR (); | |
350 | /* Return from normal running state. */ | |
351 | new_pc = GET_H_SPR (H_SPR_PCSR); | |
352 | SET_PSR_ET (psr, 1); | |
353 | SET_PSR_S (psr, GET_PSR_PS (psr)); | |
354 | sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, H_SPR_PSR, psr); | |
355 | } | |
356 | else if (CPU_DEBUG_STATE (current_cpu) && debug_field == 1) | |
357 | { | |
358 | USI psr = GET_PSR (); | |
359 | /* Return from debug state. */ | |
360 | new_pc = GET_H_SPR (H_SPR_BPCSR); | |
361 | SET_PSR_ET (psr, GET_H_BPSR_BET ()); | |
362 | SET_PSR_S (psr, GET_H_BPSR_BS ()); | |
363 | sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, H_SPR_PSR, psr); | |
364 | CPU_DEBUG_STATE (current_cpu) = 0; | |
365 | } | |
366 | else | |
367 | new_pc = pc + 4; | |
368 | ||
369 | return new_pc; | |
370 | } | |
371 | \f | |
372 | /* Functions for handling non-excepting instruction side effects. */ | |
373 | static SI next_available_nesr (SIM_CPU *current_cpu, SI current_index) | |
374 | { | |
375 | FRV_REGISTER_CONTROL *control = CPU_REGISTER_CONTROL (current_cpu); | |
376 | if (control->spr[H_SPR_NECR].implemented) | |
377 | { | |
378 | int limit; | |
379 | USI necr = GET_NECR (); | |
380 | ||
381 | /* See if any NESRs are implemented. First need to check the validity of | |
382 | the NECR. */ | |
383 | if (! GET_NECR_VALID (necr)) | |
384 | return NO_NESR; | |
385 | ||
386 | limit = GET_NECR_NEN (necr); | |
387 | for (++current_index; current_index < limit; ++current_index) | |
388 | { | |
389 | SI nesr = GET_NESR (current_index); | |
390 | if (! GET_NESR_VALID (nesr)) | |
391 | return current_index; | |
392 | } | |
393 | } | |
394 | return NO_NESR; | |
395 | } | |
396 | ||
397 | static SI next_valid_nesr (SIM_CPU *current_cpu, SI current_index) | |
398 | { | |
399 | FRV_REGISTER_CONTROL *control = CPU_REGISTER_CONTROL (current_cpu); | |
400 | if (control->spr[H_SPR_NECR].implemented) | |
401 | { | |
402 | int limit; | |
403 | USI necr = GET_NECR (); | |
404 | ||
405 | /* See if any NESRs are implemented. First need to check the validity of | |
406 | the NECR. */ | |
407 | if (! GET_NECR_VALID (necr)) | |
408 | return NO_NESR; | |
409 | ||
410 | limit = GET_NECR_NEN (necr); | |
411 | for (++current_index; current_index < limit; ++current_index) | |
412 | { | |
413 | SI nesr = GET_NESR (current_index); | |
414 | if (GET_NESR_VALID (nesr)) | |
415 | return current_index; | |
416 | } | |
417 | } | |
418 | return NO_NESR; | |
419 | } | |
420 | ||
421 | BI | |
422 | frvbf_check_non_excepting_load ( | |
423 | SIM_CPU *current_cpu, SI base_index, SI disp_index, SI target_index, | |
424 | SI immediate_disp, QI data_size, BI is_float | |
425 | ) | |
426 | { | |
427 | BI rc = 1; /* perform the load. */ | |
428 | SIM_DESC sd = CPU_STATE (current_cpu); | |
429 | int daec = 0; | |
430 | int rec = 0; | |
431 | int ec = 0; | |
432 | USI necr; | |
433 | int do_elos; | |
434 | SI NE_flags[2]; | |
435 | SI NE_base; | |
436 | SI nesr; | |
437 | SI ne_index; | |
438 | FRV_REGISTER_CONTROL *control; | |
439 | ||
440 | SI address = GET_H_GR (base_index); | |
441 | if (disp_index >= 0) | |
442 | address += GET_H_GR (disp_index); | |
443 | else | |
444 | address += immediate_disp; | |
445 | ||
446 | /* Check for interrupt factors. */ | |
447 | switch (data_size) | |
448 | { | |
449 | case NESR_UQI_SIZE: | |
450 | case NESR_QI_SIZE: | |
451 | break; | |
452 | case NESR_UHI_SIZE: | |
453 | case NESR_HI_SIZE: | |
454 | if (address & 1) | |
455 | ec = 1; | |
456 | break; | |
457 | case NESR_SI_SIZE: | |
458 | if (address & 3) | |
459 | ec = 1; | |
460 | break; | |
461 | case NESR_DI_SIZE: | |
462 | if (address & 7) | |
463 | ec = 1; | |
464 | if (target_index & 1) | |
465 | rec = 1; | |
466 | break; | |
467 | case NESR_XI_SIZE: | |
468 | if (address & 0xf) | |
469 | ec = 1; | |
470 | if (target_index & 3) | |
471 | rec = 1; | |
472 | break; | |
473 | default: | |
474 | { | |
475 | IADDR pc = GET_H_PC (); | |
476 | sim_engine_abort (sd, current_cpu, pc, | |
477 | "check_non_excepting_load: Incorrect data_size\n"); | |
478 | break; | |
479 | } | |
480 | } | |
481 | ||
482 | control = CPU_REGISTER_CONTROL (current_cpu); | |
483 | if (control->spr[H_SPR_NECR].implemented) | |
484 | { | |
485 | necr = GET_NECR (); | |
486 | do_elos = GET_NECR_VALID (necr) && GET_NECR_ELOS (necr); | |
487 | } | |
488 | else | |
489 | do_elos = 0; | |
490 | ||
491 | /* NECR, NESR, NEEAR are only implemented for the full frv machine. */ | |
492 | if (do_elos) | |
493 | { | |
494 | ne_index = next_available_nesr (current_cpu, NO_NESR); | |
495 | if (ne_index == NO_NESR) | |
496 | { | |
497 | IADDR pc = GET_H_PC (); | |
498 | sim_engine_abort (sd, current_cpu, pc, | |
499 | "No available NESR register\n"); | |
500 | } | |
501 | ||
502 | /* Fill in the basic fields of the NESR. */ | |
503 | nesr = GET_NESR (ne_index); | |
504 | SET_NESR_VALID (nesr); | |
505 | SET_NESR_EAV (nesr); | |
506 | SET_NESR_DRN (nesr, target_index); | |
507 | SET_NESR_SIZE (nesr, data_size); | |
508 | SET_NESR_NEAN (nesr, ne_index); | |
509 | if (is_float) | |
510 | SET_NESR_FR (nesr); | |
511 | else | |
512 | CLEAR_NESR_FR (nesr); | |
513 | ||
514 | /* Set the corresponding NEEAR. */ | |
515 | SET_NEEAR (ne_index, address); | |
516 | ||
517 | SET_NESR_DAEC (nesr, 0); | |
518 | SET_NESR_REC (nesr, 0); | |
519 | SET_NESR_EC (nesr, 0); | |
520 | } | |
521 | ||
522 | /* Set the NE flag corresponding to the target register if an interrupt | |
523 | factor was detected. | |
524 | daec is not checked here yet, but is declared for future reference. */ | |
525 | if (is_float) | |
526 | NE_base = H_SPR_FNER0; | |
527 | else | |
528 | NE_base = H_SPR_GNER0; | |
529 | ||
530 | GET_NE_FLAGS (NE_flags, NE_base); | |
531 | if (rec) | |
532 | { | |
533 | SET_NE_FLAG (NE_flags, target_index); | |
534 | if (do_elos) | |
535 | SET_NESR_REC (nesr, NESR_REGISTER_NOT_ALIGNED); | |
536 | } | |
537 | ||
538 | if (ec) | |
539 | { | |
540 | SET_NE_FLAG (NE_flags, target_index); | |
541 | if (do_elos) | |
542 | SET_NESR_EC (nesr, NESR_MEM_ADDRESS_NOT_ALIGNED); | |
543 | } | |
544 | ||
545 | if (do_elos) | |
546 | SET_NESR (ne_index, nesr); | |
547 | ||
548 | /* If no interrupt factor was detected then set the NE flag on the | |
549 | target register if the NE flag on one of the input registers | |
550 | is already set. */ | |
551 | if (! rec && ! ec && ! daec) | |
552 | { | |
553 | BI ne_flag = GET_NE_FLAG (NE_flags, base_index); | |
554 | if (disp_index >= 0) | |
555 | ne_flag |= GET_NE_FLAG (NE_flags, disp_index); | |
556 | if (ne_flag) | |
557 | { | |
558 | SET_NE_FLAG (NE_flags, target_index); | |
559 | rc = 0; /* Do not perform the load. */ | |
560 | } | |
561 | else | |
562 | CLEAR_NE_FLAG (NE_flags, target_index); | |
563 | } | |
564 | ||
565 | SET_NE_FLAGS (NE_base, NE_flags); | |
566 | ||
567 | return rc; /* perform the load? */ | |
568 | } | |
569 | ||
570 | /* Record state for media exception: media_cr_not_aligned. */ | |
571 | void | |
572 | frvbf_media_cr_not_aligned (SIM_CPU *current_cpu) | |
573 | { | |
574 | SIM_DESC sd = CPU_STATE (current_cpu); | |
575 | ||
e930b1f5 DB |
576 | /* On some machines this generates an illegal_instruction interrupt. */ |
577 | switch (STATE_ARCHITECTURE (sd)->mach) | |
578 | { | |
676a64f4 RS |
579 | /* Note: there is a discrepancy between V2.2 of the FR400 |
580 | instruction manual and the various FR4xx LSI specs. The former | |
581 | claims that unaligned registers cause an mp_exception while the | |
582 | latter say it's an illegal_instruction. The LSI specs appear | |
583 | to be correct since MTT is fixed at 1. */ | |
e930b1f5 | 584 | case bfd_mach_fr400: |
676a64f4 | 585 | case bfd_mach_fr450: |
e930b1f5 DB |
586 | case bfd_mach_fr550: |
587 | frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); | |
588 | break; | |
589 | default: | |
590 | frv_set_mp_exception_registers (current_cpu, MTT_CR_NOT_ALIGNED, 0); | |
591 | break; | |
592 | } | |
b34f6357 DB |
593 | } |
594 | ||
595 | /* Record state for media exception: media_acc_not_aligned. */ | |
596 | void | |
597 | frvbf_media_acc_not_aligned (SIM_CPU *current_cpu) | |
598 | { | |
599 | SIM_DESC sd = CPU_STATE (current_cpu); | |
600 | ||
e930b1f5 DB |
601 | /* On some machines this generates an illegal_instruction interrupt. */ |
602 | switch (STATE_ARCHITECTURE (sd)->mach) | |
603 | { | |
676a64f4 | 604 | /* See comment in frvbf_cr_not_aligned(). */ |
e930b1f5 | 605 | case bfd_mach_fr400: |
676a64f4 | 606 | case bfd_mach_fr450: |
e930b1f5 DB |
607 | case bfd_mach_fr550: |
608 | frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); | |
609 | break; | |
610 | default: | |
611 | frv_set_mp_exception_registers (current_cpu, MTT_ACC_NOT_ALIGNED, 0); | |
612 | break; | |
613 | } | |
b34f6357 DB |
614 | } |
615 | ||
616 | /* Record state for media exception: media_register_not_aligned. */ | |
617 | void | |
618 | frvbf_media_register_not_aligned (SIM_CPU *current_cpu) | |
619 | { | |
620 | SIM_DESC sd = CPU_STATE (current_cpu); | |
621 | ||
e930b1f5 DB |
622 | /* On some machines this generates an illegal_instruction interrupt. */ |
623 | switch (STATE_ARCHITECTURE (sd)->mach) | |
624 | { | |
676a64f4 | 625 | /* See comment in frvbf_cr_not_aligned(). */ |
e930b1f5 | 626 | case bfd_mach_fr400: |
676a64f4 | 627 | case bfd_mach_fr450: |
e930b1f5 DB |
628 | case bfd_mach_fr550: |
629 | frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); | |
630 | break; | |
631 | default: | |
632 | frv_set_mp_exception_registers (current_cpu, MTT_INVALID_FR, 0); | |
633 | break; | |
634 | } | |
b34f6357 DB |
635 | } |
636 | ||
637 | /* Record state for media exception: media_overflow. */ | |
638 | void | |
639 | frvbf_media_overflow (SIM_CPU *current_cpu, int sie) | |
640 | { | |
641 | frv_set_mp_exception_registers (current_cpu, MTT_OVERFLOW, sie); | |
642 | } | |
643 | ||
644 | /* Queue a division exception. */ | |
645 | enum frv_dtt | |
646 | frvbf_division_exception (SIM_CPU *current_cpu, enum frv_dtt dtt, | |
647 | int target_index, int non_excepting) | |
648 | { | |
649 | /* If there was an overflow and it is masked, then record it in | |
650 | ISR.AEXC. */ | |
651 | USI isr = GET_ISR (); | |
652 | if ((dtt & FRV_DTT_OVERFLOW) && GET_ISR_EDE (isr)) | |
653 | { | |
654 | dtt &= ~FRV_DTT_OVERFLOW; | |
655 | SET_ISR_AEXC (isr); | |
656 | SET_ISR (isr); | |
657 | } | |
658 | if (dtt != FRV_DTT_NO_EXCEPTION) | |
659 | { | |
660 | if (non_excepting) | |
661 | { | |
662 | /* Non excepting instruction, simply set the NE flag for the target | |
663 | register. */ | |
664 | SI NE_flags[2]; | |
665 | GET_NE_FLAGS (NE_flags, H_SPR_GNER0); | |
666 | SET_NE_FLAG (NE_flags, target_index); | |
667 | SET_NE_FLAGS (H_SPR_GNER0, NE_flags); | |
668 | } | |
669 | else | |
670 | frv_queue_division_exception_interrupt (current_cpu, dtt); | |
671 | } | |
672 | return dtt; | |
673 | } | |
674 | ||
675 | void | |
676 | frvbf_check_recovering_store ( | |
677 | SIM_CPU *current_cpu, PCADDR address, SI regno, int size, int is_float | |
678 | ) | |
679 | { | |
680 | FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu); | |
681 | int reg_ix; | |
682 | ||
683 | CPU_RSTR_INVALIDATE(current_cpu) = 0; | |
684 | ||
685 | for (reg_ix = next_valid_nesr (current_cpu, NO_NESR); | |
686 | reg_ix != NO_NESR; | |
687 | reg_ix = next_valid_nesr (current_cpu, reg_ix)) | |
688 | { | |
689 | if (address == GET_H_SPR (H_SPR_NEEAR0 + reg_ix)) | |
690 | { | |
691 | SI nesr = GET_NESR (reg_ix); | |
692 | int nesr_drn = GET_NESR_DRN (nesr); | |
693 | BI nesr_fr = GET_NESR_FR (nesr); | |
694 | SI remain; | |
695 | ||
696 | /* Invalidate cache block containing this address. | |
697 | If we need to count cycles, then the cache operation will be | |
698 | initiated from the model profiling functions. | |
699 | See frvbf_model_.... */ | |
700 | if (model_insn) | |
701 | { | |
702 | CPU_RSTR_INVALIDATE(current_cpu) = 1; | |
703 | CPU_LOAD_ADDRESS (current_cpu) = address; | |
704 | } | |
705 | else | |
706 | frv_cache_invalidate (cache, address, 1/* flush */); | |
707 | ||
708 | /* Copy the stored value to the register indicated by NESR.DRN. */ | |
709 | for (remain = size; remain > 0; remain -= 4) | |
710 | { | |
711 | SI value; | |
712 | ||
713 | if (is_float) | |
714 | value = GET_H_FR (regno); | |
715 | else | |
716 | value = GET_H_GR (regno); | |
717 | ||
718 | switch (size) | |
719 | { | |
720 | case 1: | |
721 | value &= 0xff; | |
722 | break; | |
723 | case 2: | |
724 | value &= 0xffff; | |
725 | break; | |
726 | default: | |
727 | break; | |
728 | } | |
729 | ||
730 | if (nesr_fr) | |
731 | sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, nesr_drn, | |
732 | value); | |
733 | else | |
734 | sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, nesr_drn, | |
735 | value); | |
736 | ||
737 | nesr_drn++; | |
738 | regno++; | |
739 | } | |
740 | break; /* Only consider the first matching register. */ | |
741 | } | |
742 | } /* loop over active neear registers. */ | |
743 | } | |
744 | ||
e930b1f5 DB |
745 | SI |
746 | frvbf_check_acc_range (SIM_CPU *current_cpu, SI regno) | |
747 | { | |
748 | /* Only applicable to fr550 */ | |
749 | SIM_DESC sd = CPU_STATE (current_cpu); | |
750 | if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550) | |
f00b50d0 | 751 | return 0; |
e930b1f5 DB |
752 | |
753 | /* On the fr550, media insns in slots 0 and 2 can only access | |
754 | accumulators acc0-acc3. Insns in slots 1 and 3 can only access | |
755 | accumulators acc4-acc7 */ | |
756 | switch (frv_current_fm_slot) | |
757 | { | |
758 | case UNIT_FM0: | |
759 | case UNIT_FM2: | |
760 | if (regno <= 3) | |
761 | return 1; /* all is ok */ | |
762 | break; | |
763 | case UNIT_FM1: | |
764 | case UNIT_FM3: | |
765 | if (regno >= 4) | |
766 | return 1; /* all is ok */ | |
767 | break; | |
768 | } | |
769 | ||
770 | /* The specified accumulator is out of range. Queue an illegal_instruction | |
771 | interrupt. */ | |
772 | frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); | |
773 | return 0; | |
774 | } | |
775 | ||
776 | void | |
777 | frvbf_check_swap_address (SIM_CPU *current_cpu, SI address) | |
778 | { | |
779 | /* Only applicable to fr550 */ | |
780 | SIM_DESC sd = CPU_STATE (current_cpu); | |
781 | if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550) | |
782 | return; | |
783 | ||
784 | /* Adress must be aligned on a word boundary. */ | |
785 | if (address & 0x3) | |
786 | frv_queue_data_access_exception_interrupt (current_cpu); | |
787 | } | |
788 | ||
b34f6357 DB |
789 | static void |
790 | clear_nesr_neear (SIM_CPU *current_cpu, SI target_index, BI is_float) | |
791 | { | |
792 | int reg_ix; | |
793 | ||
794 | /* Only implemented for full frv. */ | |
795 | SIM_DESC sd = CPU_STATE (current_cpu); | |
796 | if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_frv) | |
797 | return; | |
798 | ||
799 | /* Clear the appropriate NESR and NEEAR registers. */ | |
800 | for (reg_ix = next_valid_nesr (current_cpu, NO_NESR); | |
801 | reg_ix != NO_NESR; | |
802 | reg_ix = next_valid_nesr (current_cpu, reg_ix)) | |
803 | { | |
804 | SI nesr; | |
805 | /* The register is available, now check if it is active. */ | |
806 | nesr = GET_NESR (reg_ix); | |
807 | if (GET_NESR_FR (nesr) == is_float) | |
808 | { | |
809 | if (target_index < 0 || GET_NESR_DRN (nesr) == target_index) | |
810 | { | |
811 | SET_NESR (reg_ix, 0); | |
812 | SET_NEEAR (reg_ix, 0); | |
813 | } | |
814 | } | |
815 | } | |
816 | } | |
817 | ||
818 | static void | |
819 | clear_ne_flags ( | |
820 | SIM_CPU *current_cpu, | |
821 | SI target_index, | |
822 | int hi_available, | |
823 | int lo_available, | |
824 | SI NE_base | |
825 | ) | |
826 | { | |
827 | SI NE_flags[2]; | |
828 | int exception; | |
829 | ||
830 | GET_NE_FLAGS (NE_flags, NE_base); | |
831 | if (target_index >= 0) | |
832 | CLEAR_NE_FLAG (NE_flags, target_index); | |
833 | else | |
834 | { | |
835 | if (lo_available) | |
836 | NE_flags[1] = 0; | |
837 | if (hi_available) | |
838 | NE_flags[0] = 0; | |
839 | } | |
840 | SET_NE_FLAGS (NE_base, NE_flags); | |
841 | } | |
842 | ||
843 | /* Return 1 if the given register is available, 0 otherwise. TARGET_INDEX==-1 | |
844 | means to check for any register available. */ | |
845 | static void | |
846 | which_registers_available ( | |
847 | SIM_CPU *current_cpu, int *hi_available, int *lo_available, int is_float | |
848 | ) | |
849 | { | |
850 | if (is_float) | |
851 | frv_fr_registers_available (current_cpu, hi_available, lo_available); | |
852 | else | |
853 | frv_gr_registers_available (current_cpu, hi_available, lo_available); | |
854 | } | |
855 | ||
856 | void | |
857 | frvbf_clear_ne_flags (SIM_CPU *current_cpu, SI target_index, BI is_float) | |
858 | { | |
859 | int hi_available; | |
860 | int lo_available; | |
861 | int exception; | |
862 | SI NE_base; | |
863 | USI necr; | |
864 | FRV_REGISTER_CONTROL *control; | |
865 | ||
866 | /* Check for availability of the target register(s). */ | |
867 | which_registers_available (current_cpu, & hi_available, & lo_available, | |
868 | is_float); | |
869 | ||
870 | /* Check to make sure that the target register is available. */ | |
871 | if (! frv_check_register_access (current_cpu, target_index, | |
872 | hi_available, lo_available)) | |
873 | return; | |
874 | ||
875 | /* Determine whether we're working with GR or FR registers. */ | |
876 | if (is_float) | |
877 | NE_base = H_SPR_FNER0; | |
878 | else | |
879 | NE_base = H_SPR_GNER0; | |
880 | ||
881 | /* Always clear the appropriate NE flags. */ | |
882 | clear_ne_flags (current_cpu, target_index, hi_available, lo_available, | |
883 | NE_base); | |
884 | ||
885 | /* Clear the appropriate NESR and NEEAR registers. */ | |
886 | control = CPU_REGISTER_CONTROL (current_cpu); | |
887 | if (control->spr[H_SPR_NECR].implemented) | |
888 | { | |
889 | necr = GET_NECR (); | |
890 | if (GET_NECR_VALID (necr) && GET_NECR_ELOS (necr)) | |
891 | clear_nesr_neear (current_cpu, target_index, is_float); | |
892 | } | |
893 | } | |
894 | ||
895 | void | |
896 | frvbf_commit (SIM_CPU *current_cpu, SI target_index, BI is_float) | |
897 | { | |
898 | SI NE_base; | |
899 | SI NE_flags[2]; | |
900 | BI NE_flag; | |
901 | int exception; | |
902 | int hi_available; | |
903 | int lo_available; | |
904 | USI necr; | |
905 | FRV_REGISTER_CONTROL *control; | |
906 | ||
907 | /* Check for availability of the target register(s). */ | |
908 | which_registers_available (current_cpu, & hi_available, & lo_available, | |
909 | is_float); | |
910 | ||
911 | /* Check to make sure that the target register is available. */ | |
912 | if (! frv_check_register_access (current_cpu, target_index, | |
913 | hi_available, lo_available)) | |
914 | return; | |
915 | ||
916 | /* Determine whether we're working with GR or FR registers. */ | |
917 | if (is_float) | |
918 | NE_base = H_SPR_FNER0; | |
919 | else | |
920 | NE_base = H_SPR_GNER0; | |
921 | ||
922 | /* Determine whether a ne exception is pending. */ | |
923 | GET_NE_FLAGS (NE_flags, NE_base); | |
924 | if (target_index >= 0) | |
925 | NE_flag = GET_NE_FLAG (NE_flags, target_index); | |
926 | else | |
927 | { | |
fc12ae42 MF |
928 | NE_flag = (hi_available && NE_flags[0] != 0) |
929 | || (lo_available && NE_flags[1] != 0); | |
b34f6357 DB |
930 | } |
931 | ||
932 | /* Always clear the appropriate NE flags. */ | |
933 | clear_ne_flags (current_cpu, target_index, hi_available, lo_available, | |
934 | NE_base); | |
935 | ||
936 | control = CPU_REGISTER_CONTROL (current_cpu); | |
937 | if (control->spr[H_SPR_NECR].implemented) | |
938 | { | |
939 | necr = GET_NECR (); | |
940 | if (GET_NECR_VALID (necr) && GET_NECR_ELOS (necr) && NE_flag) | |
941 | { | |
942 | /* Clear the appropriate NESR and NEEAR registers. */ | |
943 | clear_nesr_neear (current_cpu, target_index, is_float); | |
944 | frv_queue_program_interrupt (current_cpu, FRV_COMMIT_EXCEPTION); | |
945 | } | |
946 | } | |
947 | } | |
948 | ||
949 | /* Generate the appropriate fp_exception(s) based on the given status code. */ | |
950 | void | |
951 | frvbf_fpu_error (CGEN_FPU* fpu, int status) | |
952 | { | |
953 | struct frv_fp_exception_info fp_info = { | |
954 | FSR_NO_EXCEPTION, FTT_IEEE_754_EXCEPTION | |
955 | }; | |
956 | ||
957 | if (status & | |
958 | (sim_fpu_status_invalid_snan | | |
959 | sim_fpu_status_invalid_qnan | | |
960 | sim_fpu_status_invalid_isi | | |
961 | sim_fpu_status_invalid_idi | | |
962 | sim_fpu_status_invalid_zdz | | |
963 | sim_fpu_status_invalid_imz | | |
964 | sim_fpu_status_invalid_cvi | | |
965 | sim_fpu_status_invalid_cmp | | |
966 | sim_fpu_status_invalid_sqrt)) | |
967 | fp_info.fsr_mask |= FSR_INVALID_OPERATION; | |
968 | ||
969 | if (status & sim_fpu_status_invalid_div0) | |
970 | fp_info.fsr_mask |= FSR_DIVISION_BY_ZERO; | |
971 | ||
972 | if (status & sim_fpu_status_inexact) | |
973 | fp_info.fsr_mask |= FSR_INEXACT; | |
974 | ||
975 | if (status & sim_fpu_status_overflow) | |
976 | fp_info.fsr_mask |= FSR_OVERFLOW; | |
977 | ||
978 | if (status & sim_fpu_status_underflow) | |
979 | fp_info.fsr_mask |= FSR_UNDERFLOW; | |
980 | ||
981 | if (status & sim_fpu_status_denorm) | |
982 | { | |
983 | fp_info.fsr_mask |= FSR_DENORMAL_INPUT; | |
984 | fp_info.ftt = FTT_DENORMAL_INPUT; | |
985 | } | |
986 | ||
987 | if (fp_info.fsr_mask != FSR_NO_EXCEPTION) | |
988 | { | |
989 | SIM_CPU *current_cpu = (SIM_CPU *)fpu->owner; | |
990 | frv_queue_fp_exception_interrupt (current_cpu, & fp_info); | |
991 | } | |
992 | } |