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19139515 SC |
1 | /* H8/300 simulator |
2 | Copyright 1992 Free Software Foundation, Inc. | |
3 | ||
4 | Contributed by Cygnus Support. | |
5 | Written by Steve Chamberlain (sac@cygnus.com). | |
6 | ||
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; if not, write to the Free Software | |
20 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ | |
21 | ||
22 | #include <stdio.h> | |
23 | #include <stdlib.h> | |
24 | #include <signal.h> | |
62b66d6d | 25 | #include "state.h" |
19139515 SC |
26 | |
27 | #define V (v!=0) | |
28 | #define C (c!=0) | |
29 | #define N (n!=0) | |
30 | #define Z (z!=0) | |
31 | ||
62b66d6d SC |
32 | #define SET_CCR(x) n = x & 0x8; v = x & 0x2; z = x & 0x4; c = x & 0x1;saved_state.ienable=x&0x80; |
33 | #define GET_CCR() ((N << 3) | (Z<<2) | (V<<1) | C) | ((!saved_state.ienable)<<7) | |
19139515 | 34 | |
19139515 | 35 | |
19139515 SC |
36 | |
37 | static union | |
38 | { | |
39 | short int i; | |
40 | struct | |
41 | { | |
42 | char low; | |
43 | char high; | |
44 | } | |
45 | ||
46 | u; | |
47 | } | |
48 | ||
49 | littleendian; | |
50 | ||
51 | static void | |
52 | meminit () | |
53 | { | |
a082325b | 54 | if (saved_state.mem == 0) |
19139515 SC |
55 | { |
56 | int tmp; | |
57 | ||
a082325b | 58 | saved_state.mem = (unsigned short *)calloc (1024, 64); |
19139515 | 59 | littleendian.i = 1; |
19139515 SC |
60 | /* initialze the array of pointers to byte registers */ |
61 | for (tmp = 0; tmp < 8; tmp++) | |
62 | { | |
63 | if (littleendian.u.high) | |
64 | { | |
65 | saved_state.bregp[tmp] = (unsigned char *) (saved_state.reg + tmp); | |
66 | saved_state.bregp[tmp + 8] = saved_state.bregp[tmp] + 1; | |
62b66d6d SC |
67 | if (HOST_IS_LITTLE_ENDIAN) |
68 | abort(); | |
19139515 SC |
69 | } |
70 | else | |
71 | { | |
72 | saved_state.bregp[tmp + 8] = (unsigned char *) (saved_state.reg + tmp); | |
73 | saved_state.bregp[tmp] = saved_state.bregp[tmp + 8] + 1; | |
62b66d6d SC |
74 | if (!HOST_IS_LITTLE_ENDIAN) |
75 | abort(); | |
19139515 SC |
76 | } |
77 | } | |
78 | ||
79 | /* we keep two 256 sized pointers to byte regs, one for when we | |
80 | want to look at the reg descibed by bits NNNNxxxx and one for | |
81 | when we want to look at xxxxNNNN */ | |
82 | for (tmp = 0; tmp < 256; tmp++) | |
83 | { | |
84 | saved_state.bregp_NNNNxxxx[tmp] = saved_state.bregp[(tmp >> 4) & 0xf]; | |
85 | saved_state.bregp_xxxxNNNN[tmp] = saved_state.bregp[tmp & 0xf]; | |
86 | } | |
87 | /* We keep two 256 sized pointers to word regs, one for regs in | |
88 | xNNNxxxx and one for regs in xxxxxNNNN */ | |
89 | for (tmp = 0; tmp < 256; tmp++) | |
90 | { | |
91 | saved_state.wregp_xNNNxxxx[tmp] = &saved_state.reg[(tmp >> 4) & 0x7]; | |
92 | saved_state.wregp_xxxxxNNN[tmp] = &saved_state.reg[tmp & 0x7]; | |
93 | } | |
94 | ||
62b66d6d SC |
95 | saved_state.reg[HCHECK] = 10000000; /* don't check the hardware |
96 | often */ | |
19139515 | 97 | } |
62b66d6d | 98 | |
19139515 SC |
99 | } |
100 | ||
06137fcb SC |
101 | |
102 | void | |
103 | control_c (sig, code, scp, addr) | |
104 | int sig; | |
105 | int code; | |
106 | char *scp; | |
107 | char *addr; | |
108 | { | |
62b66d6d | 109 | saved_state.exception = SIGINT; |
06137fcb SC |
110 | } |
111 | ||
112 | void | |
113 | sim_store_register (reg, val) | |
114 | int reg; | |
115 | int val; | |
116 | { | |
117 | saved_state.reg[reg] = val; | |
118 | } | |
119 | ||
120 | void | |
121 | sim_fetch_register (reg, buf) | |
122 | int reg; | |
123 | char *buf; | |
124 | { | |
125 | meminit(); | |
126 | buf[0] = saved_state.reg[reg] >> 8; | |
127 | buf[1] = saved_state.reg[reg]; | |
128 | } | |
129 | ||
19139515 SC |
130 | void |
131 | sim_write (to, from, len) | |
132 | int to; | |
133 | char *from; | |
134 | int len; | |
135 | { | |
62b66d6d | 136 | int i; |
19139515 | 137 | meminit (); |
62b66d6d SC |
138 | |
139 | for ( i = 0; i < len; i++) | |
140 | SET_BYTE_MEM(to + i, from[i]); | |
19139515 SC |
141 | } |
142 | ||
143 | void | |
144 | sim_read (from, to, len) | |
145 | int from; | |
146 | char *to; | |
147 | ||
148 | int len; | |
149 | { | |
62b66d6d | 150 | int i; |
19139515 | 151 | meminit (); |
62b66d6d SC |
152 | for (i = 0; i < len; i++) { |
153 | to[i] = BYTE_MEM(from + i); | |
154 | } | |
19139515 SC |
155 | } |
156 | ||
157 | int | |
158 | sim_stop_signal () | |
159 | { | |
62b66d6d SC |
160 | return saved_state.exception; |
161 | } | |
162 | ||
163 | void | |
164 | load_timer_state_from_mem() | |
165 | { | |
166 | ||
167 | saved_state.reg[TIER] = BYTE_MEM(0xff90); | |
168 | saved_state.reg[TCSR] = BYTE_MEM(0xff91); | |
169 | saved_state.reg[FRC] = WORD_MEM(0xff92); | |
170 | saved_state.reg[TCR] = BYTE_MEM(0xff96); | |
171 | saved_state.reg[TOCR] = BYTE_MEM(0xff97); | |
172 | ||
173 | ||
174 | if ((saved_state.reg[TOCR] & OCRS) == 0) | |
175 | { | |
176 | saved_state.reg[OCRA] = WORD_MEM(0xff94); | |
177 | } | |
178 | else | |
179 | { | |
180 | saved_state.reg[OCRB] = WORD_MEM(0xff94); | |
181 | } | |
182 | } | |
183 | ||
184 | void | |
185 | store_timer_state_to_mem() | |
186 | { | |
187 | ||
188 | BYTE_MEM(0xff91) = saved_state.reg[TCSR]; | |
189 | SET_WORD_MEM(0xff92, saved_state.reg[FRC]); | |
19139515 SC |
190 | } |
191 | ||
192 | void | |
193 | sim_resume (step, sig) | |
194 | int step; | |
195 | int sig; | |
196 | { | |
197 | int lval; | |
198 | int tmp; | |
199 | int b0; | |
200 | int b1; | |
62b66d6d SC |
201 | int checkfreq; |
202 | int ni; /* Number of insts to execute before checking hw state */ | |
19139515 SC |
203 | unsigned char **blow; |
204 | unsigned char **bhigh; | |
205 | unsigned short **wlow; | |
206 | unsigned short **whigh; | |
62b66d6d | 207 | unsigned short *npc; |
19139515 SC |
208 | int rn; |
209 | unsigned short int *reg; | |
210 | unsigned char **bregp; | |
211 | void (*prev) (); | |
62b66d6d | 212 | unsigned short *pc; |
19139515 SC |
213 | |
214 | int srca; | |
215 | int srcb; | |
216 | int dst; | |
62b66d6d | 217 | int cycles ; |
19139515 SC |
218 | |
219 | int n; | |
220 | int v; | |
221 | int z; | |
222 | int c; | |
223 | ||
19139515 | 224 | |
62b66d6d | 225 | /* Set up pointers to areas */ |
19139515 SC |
226 | reg = saved_state.reg; |
227 | bregp = saved_state.bregp; | |
228 | blow = saved_state.bregp_xxxxNNNN; | |
229 | bhigh = saved_state.bregp_NNNNxxxx; | |
230 | ||
231 | wlow = saved_state.wregp_xxxxxNNN; | |
232 | whigh = saved_state.wregp_xNNNxxxx; | |
233 | ||
62b66d6d | 234 | |
19139515 SC |
235 | prev = signal (SIGINT, control_c); |
236 | meminit(); | |
62b66d6d | 237 | LOAD_INTERPRETER_STATE(); |
19139515 | 238 | if (step) |
62b66d6d | 239 | saved_state.exception = SIGTRAP; |
19139515 SC |
240 | else |
241 | { | |
62b66d6d | 242 | saved_state.exception = sig; |
19139515 SC |
243 | } |
244 | do | |
245 | { | |
62b66d6d SC |
246 | b1 = pc[0]; |
247 | b0 = b1>> 8; | |
248 | b1 &= 0xff; | |
249 | ||
19139515 SC |
250 | |
251 |