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Merge tag 'loongarch-kvm-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhu...
[thirdparty/kernel/stable.git] / sound / pci / hda / hda_intel.c
CommitLineData
1a59d1b8 1// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4
LT		 2/*
3 *
d01ce99f
TI		 4 * hda_intel.c - Implementation of primary alsa driver code base
5 * for Intel HD Audio.
1da177e4
LT		 6 *
7 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 *
9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
10 * PeiSen Hou <pshou@realtek.com.tw>
11 *
1da177e4
LT		 12 * CONTACTS:
13 *
14 * Matt Jared matt.jared@intel.com
15 * Andy Kopp andy.kopp@intel.com
16 * Dan Kogan dan.d.kogan@intel.com
17 *
18 * CHANGES:
19 *
20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
1da177e4
LT		 21 */
22
1da177e4
LT		 23#include <linux/delay.h>
24#include <linux/interrupt.h>
362775e2 25#include <linux/kernel.h>
1da177e4 26#include <linux/module.h>
24982c5f 27#include <linux/dma-mapping.h>
1da177e4
LT		 28#include <linux/moduleparam.h>
29#include <linux/init.h>
30#include <linux/slab.h>
31#include <linux/pci.h>
62932df8 32#include <linux/mutex.h>
27fe48d9 33#include <linux/io.h>
b8dfc462 34#include <linux/pm_runtime.h>
5d890f59
PLB		 35#include <linux/clocksource.h>
36#include <linux/time.h>
f4c482a4 37#include <linux/completion.h>
586bc4aa 38#include <linux/acpi.h>
65fddcfc 39#include <linux/pgtable.h>
5d890f59 40
27fe48d9
TI		 41#ifdef CONFIG_X86
42/* for snoop control */
7f80f513 43#include <asm/set_memory.h>
50279d9b 44#include <asm/cpufeature.h>
27fe48d9 45#endif
1da177e4
LT		 46#include <sound/core.h>
47#include <sound/initval.h>
98d8fc6c
ML		 48#include <sound/hdaudio.h>
49#include <sound/hda_i915.h>
82d9d54a 50#include <sound/intel-dsp-config.h>
9121947d 51#include <linux/vgaarb.h>
a82d51ed 52#include <linux/vga_switcheroo.h>
5beb5627 53#include <linux/apple-gmux.h>
4918cdab 54#include <linux/firmware.h>
be57bfff 55#include <sound/hda_codec.h>
05e84878 56#include "hda_controller.h"
347de1f8 57#include "hda_intel.h"
1da177e4 58
785d8c4b
LY		 59#define CREATE_TRACE_POINTS
60#include "hda_intel_trace.h"
61
b6050ef6
TI		 62/* position fix mode */
63enum {
64 POS_FIX_AUTO,
65 POS_FIX_LPIB,
66 POS_FIX_POSBUF,
67 POS_FIX_VIACOMBO,
68 POS_FIX_COMBO,
f87e7f25 69 POS_FIX_SKL,
c02f77d3 70 POS_FIX_FIFO,
b6050ef6
TI		 71};
72
9a34af4a
TI		 73/* Defines for ATI HD Audio support in SB450 south bridge */
74#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
75#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
76
77/* Defines for Nvidia HDA support */
78#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
79#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
80#define NVIDIA_HDA_ISTRM_COH 0x4d
81#define NVIDIA_HDA_OSTRM_COH 0x4c
82#define NVIDIA_HDA_ENABLE_COHBIT 0x01
83
84/* Defines for Intel SCH HDA snoop control */
6639484d
LY		 85#define INTEL_HDA_CGCTL 0x48
86#define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
9a34af4a
TI		 87#define INTEL_SCH_HDA_DEVC 0x78
88#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
89
33124929
TI		 90/* max number of SDs */
91/* ICH, ATI and VIA have 4 playback and 4 capture */
92#define ICH6_NUM_CAPTURE 4
93#define ICH6_NUM_PLAYBACK 4
94
95/* ULI has 6 playback and 5 capture */
96#define ULI_NUM_CAPTURE 5
97#define ULI_NUM_PLAYBACK 6
98
99/* ATI HDMI may have up to 8 playbacks and 0 capture */
100#define ATIHDMI_NUM_CAPTURE 0
101#define ATIHDMI_NUM_PLAYBACK 8
102
1da177e4 103
5aba4f8e
TI		 104static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
105static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 106static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 107static char *model[SNDRV_CARDS];
1dac6695 108static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 109static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 110static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 111static int probe_only[SNDRV_CARDS];
26a6cb6c 112static int jackpoll_ms[SNDRV_CARDS];
41438f13 113static int single_cmd = -1;
71623855 114static int enable_msi = -1;
4ea6fbc8
TI		 115#ifdef CONFIG_SND_HDA_PATCH_LOADER
116static char *patch[SNDRV_CARDS];
117#endif
2dca0bba 118#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 119static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 120 CONFIG_SND_HDA_INPUT_BEEP_MODE};
121#endif
7fba6aea 122static bool dmic_detect = 1;
d045bcef 123static bool ctl_dev_id = IS_ENABLED(CONFIG_SND_HDA_CTL_DEV_ID) ? 1 : 0;
1da177e4 124
5aba4f8e 125module_param_array(index, int, NULL, 0444);
1da177e4 126MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 127module_param_array(id, charp, NULL, 0444);
1da177e4 128MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 129module_param_array(enable, bool, NULL, 0444);
130MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
131module_param_array(model, charp, NULL, 0444);
1da177e4 132MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 133module_param_array(position_fix, int, NULL, 0444);
4cb36310 134MODULE_PARM_DESC(position_fix, "DMA pointer read method."
c02f77d3 135 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO).");
555e219f
TI		 136module_param_array(bdl_pos_adj, int, NULL, 0644);
137MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 138module_param_array(probe_mask, int, NULL, 0444);
606ad75f 139MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 140module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 141MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 142module_param_array(jackpoll_ms, int, NULL, 0444);
143MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
41438f13 144module_param(single_cmd, bint, 0444);
d01ce99f
TI		 145MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
146 "(for debugging only).");
ac9ef6cf 147module_param(enable_msi, bint, 0444);
134a11f0 148MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 149#ifdef CONFIG_SND_HDA_PATCH_LOADER
150module_param_array(patch, charp, NULL, 0444);
151MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
152#endif
2dca0bba 153#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 154module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 155MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 156 "(0=off, 1=on) (default=1).");
2dca0bba 157#endif
7fba6aea
TI		 158module_param(dmic_detect, bool, 0444);
159MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) "
160 "(0=off, 1=on) (default=1); "
161 "deprecated, use snd-intel-dspcfg.dsp_driver option instead");
d045bcef
JK		 162module_param(ctl_dev_id, bool, 0444);
163MODULE_PARM_DESC(ctl_dev_id, "Use control device identifier (based on codec address).");
606ad75f 164
83012a7c 165#ifdef CONFIG_PM
65fcd41d 166static int param_set_xint(const char *val, const struct kernel_param *kp);
9c27847d 167static const struct kernel_param_ops param_ops_xint = {
65fcd41d
TI		 168 .set = param_set_xint,
169 .get = param_get_int,
170};
171#define param_check_xint param_check_int
172
fee2fba3 173static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
65fcd41d 174module_param(power_save, xint, 0644);
fee2fba3
TI		 175MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
176 "(in second, 0 = disable).");
1da177e4 177
40088dc4
TI		 178static bool pm_blacklist = true;
179module_param(pm_blacklist, bool, 0644);
6317e5eb 180MODULE_PARM_DESC(pm_blacklist, "Enable power-management denylist");
40088dc4 181
dee1b66c
TI		 182/* reset the HD-audio controller in power save mode.
183 * this may give more power-saving, but will take longer time to
184 * wake up.
185 */
8fc24426
TI		 186static bool power_save_controller = 1;
187module_param(power_save_controller, bool, 0644);
dee1b66c 188MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
e62a42ae 189#else
bb573928 190#define power_save 0
83012a7c 191#endif /* CONFIG_PM */
dee1b66c 192
7bfe059e
TI		 193static int align_buffer_size = -1;
194module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 195MODULE_PARM_DESC(align_buffer_size,
196 "Force buffer and period sizes to be multiple of 128 bytes.");
197
27fe48d9 198#ifdef CONFIG_X86
7c732015
TI		 199static int hda_snoop = -1;
200module_param_named(snoop, hda_snoop, bint, 0444);
27fe48d9 201MODULE_PARM_DESC(snoop, "Enable/disable snooping");
27fe48d9
TI		 202#else
203#define hda_snoop true
27fe48d9
TI		 204#endif
205
206
1da177e4 207MODULE_LICENSE("GPL");
1da177e4
LT		 208MODULE_DESCRIPTION("Intel HDA driver");
209
a82d51ed 210#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
f8f1becf 211#if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
a82d51ed
TI		 212#define SUPPORT_VGA_SWITCHEROO
213#endif
214#endif
215
216
1da177e4 217/*
1da177e4 218 */
1da177e4 219
07e4ca50
TI		 220/* driver types */
221enum {
222 AZX_DRIVER_ICH,
32679f95 223 AZX_DRIVER_PCH,
4979bca9 224 AZX_DRIVER_SCH,
a4b4793f 225 AZX_DRIVER_SKL,
fab1285a 226 AZX_DRIVER_HDMI,
07e4ca50 227 AZX_DRIVER_ATI,
778b6e1b 228 AZX_DRIVER_ATIHDMI,
1815b34a 229 AZX_DRIVER_ATIHDMI_NS,
c51e4310 230 AZX_DRIVER_GFHDMI,
07e4ca50
TI		 231 AZX_DRIVER_VIA,
232 AZX_DRIVER_SIS,
233 AZX_DRIVER_ULI,
da3fca21 234 AZX_DRIVER_NVIDIA,
f269002e 235 AZX_DRIVER_TERA,
14d34f16 236 AZX_DRIVER_CTX,
5ae763b1 237 AZX_DRIVER_CTHDA,
c563f473 238 AZX_DRIVER_CMEDIA,
b6fcab14 239 AZX_DRIVER_ZHAOXIN,
28bd137a 240 AZX_DRIVER_LOONGSON,
c4da29ca 241 AZX_DRIVER_GENERIC,
2f5983f2 242 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 243};
244
37e661ee
TI		 245#define azx_get_snoop_type(chip) \
246 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
247#define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
248
b42b4afb
TI		 249/* quirks for old Intel chipsets */
250#define AZX_DCAPS_INTEL_ICH \
f34a4c9d 251 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
b42b4afb 252
2ea3c6a2 253/* quirks for Intel PCH */
6603249d 254#define AZX_DCAPS_INTEL_PCH_BASE \
103884a3 255 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
f34a4c9d 256 AZX_DCAPS_SNOOP_TYPE(SCH))
d7dab4db 257
dba9b7b6 258/* PCH up to IVB; no runtime PM; bind with i915 gfx */
6603249d 259#define AZX_DCAPS_INTEL_PCH_NOPM \
dba9b7b6 260 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
6603249d 261
55913110 262/* PCH for HSW/BDW; with runtime PM */
dba9b7b6 263/* no i915 binding for this as HSW/BDW has another controller for HDMI */
d7dab4db 264#define AZX_DCAPS_INTEL_PCH \
f5dac54d 265 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
9477c58e 266
6603249d 267/* HSW HDMI */
33499a15 268#define AZX_DCAPS_INTEL_HASWELL \
103884a3 269 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
dba9b7b6 270 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
f34a4c9d 271 AZX_DCAPS_SNOOP_TYPE(SCH))
33499a15 272
54a0405d
LY		 273/* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
274#define AZX_DCAPS_INTEL_BROADWELL \
103884a3 275 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
dba9b7b6 276 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
f34a4c9d 277 AZX_DCAPS_SNOOP_TYPE(SCH))
54a0405d 278
40cc2392 279#define AZX_DCAPS_INTEL_BAYTRAIL \
e454ff8e 280 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
40cc2392 281
2d846c74 282#define AZX_DCAPS_INTEL_BRASWELL \
dba9b7b6 283 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
e454ff8e 284 AZX_DCAPS_I915_COMPONENT)
2d846c74 285
d6795827 286#define AZX_DCAPS_INTEL_SKYLAKE \
dba9b7b6 287 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
e454ff8e 288 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
d6795827 289
2756d914 290#define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE
c87693da 291
9477c58e
TI		 292/* quirks for ATI SB / AMD Hudson */
293#define AZX_DCAPS_PRESET_ATI_SB \
f34a4c9d 294 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB |\
37e661ee 295 AZX_DCAPS_SNOOP_TYPE(ATI))
9477c58e
TI		 296
297/* quirks for ATI/AMD HDMI */
298#define AZX_DCAPS_PRESET_ATI_HDMI \
f34a4c9d 299 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB|\
db79afa1 300 AZX_DCAPS_NO_MSI64)
9477c58e 301
37e661ee
TI		 302/* quirks for ATI HDMI with snoop off */
303#define AZX_DCAPS_PRESET_ATI_HDMI_NS \
304 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
305
c02f77d3
TI		 306/* quirks for AMD SB */
307#define AZX_DCAPS_PRESET_AMD_SB \
f34a4c9d 308 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_AMD_WORKAROUND |\
c0f1886d
TI		 309 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME |\
310 AZX_DCAPS_RETRY_PROBE)
c02f77d3 311
9477c58e
TI		 312/* quirks for Nvidia */
313#define AZX_DCAPS_PRESET_NVIDIA \
3ab7511e 314 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
37e661ee 315 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
9477c58e 316
5ae763b1 317#define AZX_DCAPS_PRESET_CTHDA \
37e661ee 318 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
cadd16ea 319 AZX_DCAPS_NO_64BIT |\
37e661ee 320 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
5ae763b1 321
a82d51ed 322/*
2b760d88 323 * vga_switcheroo support
a82d51ed
TI		 324 */
325#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db 326#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
dd23e1d5 327#define needs_eld_notify_link(chip) ((chip)->bus.keep_power)
5cb543db
TI		 328#else
329#define use_vga_switcheroo(chip) 0
37a3a98e 330#define needs_eld_notify_link(chip) false
5cb543db
TI		 331#endif
332
bf82326f 333static const char * const driver_short_names[] = {
07e4ca50 334 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 335 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 336 [AZX_DRIVER_SCH] = "HDA Intel MID",
a4b4793f 337 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
fab1285a 338 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
07e4ca50 339 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 340 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 341 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
c51e4310 342 [AZX_DRIVER_GFHDMI] = "HDA GF HDMI",
07e4ca50
TI		 343 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
344 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 345 [AZX_DRIVER_ULI] = "HDA ULI M5461",
346 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 347 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 348 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 349 [AZX_DRIVER_CTHDA] = "HDA Creative",
c563f473 350 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
b6fcab14 351 [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin",
28bd137a 352 [AZX_DRIVER_LOONGSON] = "HDA Loongson",
c4da29ca 353 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 354};
355
68e7fffc 356static int azx_acquire_irq(struct azx *chip, int do_disconnect);
37a3a98e 357static void set_default_power_save(struct azx *chip);
111d3af5 358
cb53c626
TI		 359/*
360 * initialize the PCI registers
361 */
362/* update bits in a PCI register byte */
363static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
364 unsigned char mask, unsigned char val)
365{
366 unsigned char data;
367
368 pci_read_config_byte(pci, reg, &data);
369 data &= ~mask;
370 data |= (val & mask);
371 pci_write_config_byte(pci, reg, data);
372}
373
374static void azx_init_pci(struct azx *chip)
375{
37e661ee
TI		 376 int snoop_type = azx_get_snoop_type(chip);
377
cb53c626
TI		 378 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
379 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
380 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 381 * codecs.
382 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 383 */
46f2cc80 384 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
4e76a883 385 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
fb1d8ac2 386 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
9477c58e 387 }
cb53c626 388
9477c58e
TI		 389 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
390 * we need to enable snoop.
391 */
37e661ee 392 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
4e76a883
TI		 393 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
394 azx_snoop(chip));
cb53c626 395 update_pci_byte(chip->pci,
27fe48d9
TI		 396 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
397 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 398 }
399
400 /* For NVIDIA HDA, enable snoop */
37e661ee 401 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
4e76a883
TI		 402 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
403 azx_snoop(chip));
cb53c626
TI		 404 update_pci_byte(chip->pci,
405 NVIDIA_HDA_TRANSREG_ADDR,
406 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 407 update_pci_byte(chip->pci,
408 NVIDIA_HDA_ISTRM_COH,
409 0x01, NVIDIA_HDA_ENABLE_COHBIT);
410 update_pci_byte(chip->pci,
411 NVIDIA_HDA_OSTRM_COH,
412 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 413 }
414
415 /* Enable SCH/PCH snoop if needed */
37e661ee 416 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
27fe48d9 417 unsigned short snoop;
90a5ad52 418 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 419 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
420 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
421 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
422 if (!azx_snoop(chip))
423 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
424 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 425 pci_read_config_word(chip->pci,
426 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 427 }
4e76a883
TI		 428 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
429 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
430 "Disabled" : "Enabled");
da3fca21 431 }
1da177e4
LT		 432}
433
7c23b7c1
LH		 434/*
435 * In BXT-P A0, HD-Audio DMA requests is later than expected,
436 * and makes an audio stream sensitive to system latencies when
437 * 24/32 bits are playing.
438 * Adjusting threshold of DMA fifo to force the DMA request
439 * sooner to improve latency tolerance at the expense of power.
440 */
441static void bxt_reduce_dma_latency(struct azx *chip)
442{
443 u32 val;
444
70eafad8 445 val = azx_readl(chip, VS_EM4L);
7c23b7c1 446 val &= (0x3 << 20);
70eafad8 447 azx_writel(chip, VS_EM4L, val);
7c23b7c1
LH		 448}
449
1f9d3d98
LY		 450/*
451 * ML_LCAP bits:
452 * bit 0: 6 MHz Supported
453 * bit 1: 12 MHz Supported
454 * bit 2: 24 MHz Supported
455 * bit 3: 48 MHz Supported
456 * bit 4: 96 MHz Supported
457 * bit 5: 192 MHz Supported
458 */
459static int intel_get_lctl_scf(struct azx *chip)
460{
461 struct hdac_bus *bus = azx_bus(chip);
bf82326f 462 static const int preferred_bits[] = { 2, 3, 1, 4, 5 };
1f9d3d98
LY		 463 u32 val, t;
464 int i;
465
466 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
467
468 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
469 t = preferred_bits[i];
470 if (val & (1 << t))
471 return t;
472 }
473
474 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
475 return 0;
476}
477
478static int intel_ml_lctl_set_power(struct azx *chip, int state)
479{
480 struct hdac_bus *bus = azx_bus(chip);
481 u32 val;
482 int timeout;
483
484 /*
10e794bd
PLB		 485 * Changes to LCTL.SCF are only needed for the first multi-link dealing
486 * with external codecs
1f9d3d98
LY		 487 */
488 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
18afcf90
PLB		 489 val &= ~AZX_ML_LCTL_SPA;
490 val |= state << AZX_ML_LCTL_SPA_SHIFT;
1f9d3d98
LY		 491 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
492 /* wait for CPA */
493 timeout = 50;
494 while (timeout) {
495 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
18afcf90 496 AZX_ML_LCTL_CPA) == (state << AZX_ML_LCTL_CPA_SHIFT))
1f9d3d98
LY		 497 return 0;
498 timeout--;
499 udelay(10);
500 }
501
502 return -1;
503}
504
505static void intel_init_lctl(struct azx *chip)
506{
507 struct hdac_bus *bus = azx_bus(chip);
508 u32 val;
509 int ret;
510
511 /* 0. check lctl register value is correct or not */
512 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
10e794bd 513 /* only perform additional configurations if the SCF is initially based on 6MHz */
18afcf90 514 if ((val & AZX_ML_LCTL_SCF) != 0)
1f9d3d98
LY		 515 return;
516
517 /*
518 * Before operating on SPA, CPA must match SPA.
519 * Any deviation may result in undefined behavior.
520 */
18afcf90
PLB		 521 if (((val & AZX_ML_LCTL_SPA) >> AZX_ML_LCTL_SPA_SHIFT) !=
522 ((val & AZX_ML_LCTL_CPA) >> AZX_ML_LCTL_CPA_SHIFT))
1f9d3d98
LY		 523 return;
524
525 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
526 ret = intel_ml_lctl_set_power(chip, 0);
527 udelay(100);
528 if (ret)
529 goto set_spa;
530
10e794bd 531 /* 2. update SCF to select an audio clock different from 6MHz */
18afcf90 532 val &= ~AZX_ML_LCTL_SCF;
1f9d3d98
LY		 533 val |= intel_get_lctl_scf(chip);
534 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
535
536set_spa:
537 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
538 intel_ml_lctl_set_power(chip, 1);
539 udelay(100);
540}
541
0a673521
LH		 542static void hda_intel_init_chip(struct azx *chip, bool full_reset)
543{
98d8fc6c 544 struct hdac_bus *bus = azx_bus(chip);
7c23b7c1 545 struct pci_dev *pci = chip->pci;
6639484d 546 u32 val;
0a673521 547
e454ff8e 548 snd_hdac_set_codec_wakeup(bus, true);
a4b4793f 549 if (chip->driver_type == AZX_DRIVER_SKL) {
6639484d
LY		 550 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
551 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
552 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
553 }
0a673521 554 azx_init_chip(chip, full_reset);
a4b4793f 555 if (chip->driver_type == AZX_DRIVER_SKL) {
6639484d
LY		 556 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
557 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
558 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
559 }
e454ff8e
TI		 560
561 snd_hdac_set_codec_wakeup(bus, false);
7c23b7c1
LH		 562
563 /* reduce dma latency to avoid noise */
1b21bd7a 564 if (HDA_CONTROLLER_IS_APL(pci))
7c23b7c1 565 bxt_reduce_dma_latency(chip);
1f9d3d98
LY		 566
567 if (bus->mlcap != NULL)
568 intel_init_lctl(chip);
0a673521
LH		 569}
570
b6050ef6
TI		 571/* calculate runtime delay from LPIB */
572static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
573 unsigned int pos)
574{
7833c3f8 575 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6
TI		 576 int stream = substream->stream;
577 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
578 int delay;
579
580 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
581 delay = pos - lpib_pos;
582 else
583 delay = lpib_pos - pos;
584 if (delay < 0) {
7833c3f8 585 if (delay >= azx_dev->core.delay_negative_threshold)
b6050ef6
TI		 586 delay = 0;
587 else
7833c3f8 588 delay += azx_dev->core.bufsize;
b6050ef6
TI		 589 }
590
7833c3f8 591 if (delay >= azx_dev->core.period_bytes) {
b6050ef6
TI		 592 dev_info(chip->card->dev,
593 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
7833c3f8 594 delay, azx_dev->core.period_bytes);
b6050ef6
TI		 595 delay = 0;
596 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
597 chip->get_delay[stream] = NULL;
598 }
599
600 return bytes_to_frames(substream->runtime, delay);
601}
602
9ad593f6
TI		 603static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
604
7ca954a8
DR		 605/* called from IRQ */
606static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
607{
9a34af4a 608 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
7ca954a8
DR		 609 int ok;
610
611 ok = azx_position_ok(chip, azx_dev);
612 if (ok == 1) {
613 azx_dev->irq_pending = 0;
614 return ok;
2f35c630 615 } else if (ok == 0) {
7ca954a8
DR		 616 /* bogus IRQ, process it later */
617 azx_dev->irq_pending = 1;
2f35c630 618 schedule_work(&hda->irq_pending_work);
7ca954a8
DR		 619 }
620 return 0;
621}
622
029d92c2
TI		 623#define display_power(chip, enable) \
624 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
17eccb27 625
9ad593f6
TI		 626/*
627 * Check whether the current DMA position is acceptable for updating
628 * periods. Returns non-zero if it's OK.
629 *
630 * Many HD-audio controllers appear pretty inaccurate about
631 * the update-IRQ timing. The IRQ is issued before actually the
632 * data is processed. So, we need to process it afterwords in a
633 * workqueue.
46243b85
TI		 634 *
635 * Returns 1 if OK to proceed, 0 for delay handling, -1 for skipping update
9ad593f6
TI		 636 */
637static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
638{
7833c3f8 639 struct snd_pcm_substream *substream = azx_dev->core.substream;
46243b85 640 struct snd_pcm_runtime *runtime = substream->runtime;
b6050ef6 641 int stream = substream->stream;
e5463720 642 u32 wallclk;
9ad593f6 643 unsigned int pos;
46243b85 644 snd_pcm_uframes_t hwptr, target;
9ad593f6 645
a4d2b853
YS		 646 /*
647 * The value of the WALLCLK register is always 0
648 * on the Loongson controller, so we return directly.
649 */
650 if (chip->driver_type == AZX_DRIVER_LOONGSON)
651 return 1;
652
7833c3f8
TI		 653 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
654 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
fa00e046 655 return -1; /* bogus (too early) interrupt */
fa00e046 656
b6050ef6
TI		 657 if (chip->get_position[stream])
658 pos = chip->get_position[stream](chip, azx_dev);
659 else { /* use the position buffer as default */
660 pos = azx_get_pos_posbuf(chip, azx_dev);
661 if (!pos || pos == (u32)-1) {
662 dev_info(chip->card->dev,
663 "Invalid position buffer, using LPIB read method instead.\n");
664 chip->get_position[stream] = azx_get_pos_lpib;
ccc98865
TI		 665 if (chip->get_position[0] == azx_get_pos_lpib &&
666 chip->get_position[1] == azx_get_pos_lpib)
667 azx_bus(chip)->use_posbuf = false;
b6050ef6
TI		 668 pos = azx_get_pos_lpib(chip, azx_dev);
669 chip->get_delay[stream] = NULL;
670 } else {
671 chip->get_position[stream] = azx_get_pos_posbuf;
672 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
673 chip->get_delay[stream] = azx_get_delay_from_lpib;
674 }
675 }
676
7833c3f8 677 if (pos >= azx_dev->core.bufsize)
b6050ef6 678 pos = 0;
9ad593f6 679
7833c3f8 680 if (WARN_ONCE(!azx_dev->core.period_bytes,
d6d8bf54 681 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 682 return -1; /* this shouldn't happen! */
7833c3f8
TI		 683 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
684 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
f48f606d 685 /* NG - it's below the first next period boundary */
4f0189be 686 return chip->bdl_pos_adj ? 0 : -1;
7833c3f8 687 azx_dev->core.start_wallclk += wallclk;
46243b85
TI		 688
689 if (azx_dev->core.no_period_wakeup)
690 return 1; /* OK, no need to check period boundary */
691
692 if (runtime->hw_ptr_base != runtime->hw_ptr_interrupt)
693 return 1; /* OK, already in hwptr updating process */
694
695 /* check whether the period gets really elapsed */
696 pos = bytes_to_frames(runtime, pos);
697 hwptr = runtime->hw_ptr_base + pos;
698 if (hwptr < runtime->status->hw_ptr)
699 hwptr += runtime->buffer_size;
700 target = runtime->hw_ptr_interrupt + runtime->period_size;
701 if (hwptr < target) {
702 /* too early wakeup, process it later */
703 return chip->bdl_pos_adj ? 0 : -1;
704 }
705
9ad593f6
TI		 706 return 1; /* OK, it's fine */
707}
708
709/*
710 * The work for pending PCM period updates.
711 */
712static void azx_irq_pending_work(struct work_struct *work)
713{
9a34af4a
TI		 714 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
715 struct azx *chip = &hda->chip;
7833c3f8
TI		 716 struct hdac_bus *bus = azx_bus(chip);
717 struct hdac_stream *s;
718 int pending, ok;
9ad593f6 719
9a34af4a 720 if (!hda->irq_pending_warned) {
4e76a883
TI		 721 dev_info(chip->card->dev,
722 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
723 chip->card->number);
9a34af4a 724 hda->irq_pending_warned = 1;
a6a950a8
TI		 725 }
726
9ad593f6
TI		 727 for (;;) {
728 pending = 0;
a41d1224 729 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 730 list_for_each_entry(s, &bus->stream_list, list) {
731 struct azx_dev *azx_dev = stream_to_azx_dev(s);
9ad593f6 732 if (!azx_dev->irq_pending ||
7833c3f8
TI		 733 !s->substream ||
734 !s->running)
9ad593f6 735 continue;
e5463720
JK		 736 ok = azx_position_ok(chip, azx_dev);
737 if (ok > 0) {
9ad593f6 738 azx_dev->irq_pending = 0;
a41d1224 739 spin_unlock(&bus->reg_lock);
7833c3f8 740 snd_pcm_period_elapsed(s->substream);
a41d1224 741 spin_lock(&bus->reg_lock);
e5463720
JK		 742 } else if (ok < 0) {
743 pending = 0; /* too early */
9ad593f6
TI		 744 } else
745 pending++;
746 }
a41d1224 747 spin_unlock_irq(&bus->reg_lock);
9ad593f6
TI		 748 if (!pending)
749 return;
08af495f 750 msleep(1);
9ad593f6
TI		 751 }
752}
753
754/* clear irq_pending flags and assure no on-going workq */
755static void azx_clear_irq_pending(struct azx *chip)
756{
7833c3f8
TI		 757 struct hdac_bus *bus = azx_bus(chip);
758 struct hdac_stream *s;
9ad593f6 759
a41d1224 760 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 761 list_for_each_entry(s, &bus->stream_list, list) {
762 struct azx_dev *azx_dev = stream_to_azx_dev(s);
763 azx_dev->irq_pending = 0;
764 }
a41d1224 765 spin_unlock_irq(&bus->reg_lock);
1da177e4
LT		 766}
767
68e7fffc
TI		 768static int azx_acquire_irq(struct azx *chip, int do_disconnect)
769{
a41d1224
TI		 770 struct hdac_bus *bus = azx_bus(chip);
771
437a5a46
TI		 772 if (request_irq(chip->pci->irq, azx_interrupt,
773 chip->msi ? 0 : IRQF_SHARED,
de65360b 774 chip->card->irq_descr, chip)) {
4e76a883
TI		 775 dev_err(chip->card->dev,
776 "unable to grab IRQ %d, disabling device\n",
777 chip->pci->irq);
68e7fffc
TI		 778 if (do_disconnect)
779 snd_card_disconnect(chip->card);
780 return -1;
781 }
a41d1224 782 bus->irq = chip->pci->irq;
f36da940 783 chip->card->sync_irq = bus->irq;
69e13418 784 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 785 return 0;
786}
787
b6050ef6
TI		 788/* get the current DMA position with correction on VIA chips */
789static unsigned int azx_via_get_position(struct azx *chip,
790 struct azx_dev *azx_dev)
791{
792 unsigned int link_pos, mini_pos, bound_pos;
793 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
794 unsigned int fifo_size;
795
1604eeee 796 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
7833c3f8 797 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
b6050ef6
TI		 798 /* Playback, no problem using link position */
799 return link_pos;
800 }
801
802 /* Capture */
803 /* For new chipset,
804 * use mod to get the DMA position just like old chipset
805 */
7833c3f8
TI		 806 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
807 mod_dma_pos %= azx_dev->core.period_bytes;
b6050ef6 808
956b610c 809 fifo_size = azx_stream(azx_dev)->fifo_size;
b6050ef6
TI		 810
811 if (azx_dev->insufficient) {
812 /* Link position never gather than FIFO size */
813 if (link_pos <= fifo_size)
814 return 0;
815
816 azx_dev->insufficient = 0;
817 }
818
819 if (link_pos <= fifo_size)
7833c3f8 820 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
b6050ef6
TI		 821 else
822 mini_pos = link_pos - fifo_size;
823
824 /* Find nearest previous boudary */
7833c3f8
TI		 825 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
826 mod_link_pos = link_pos % azx_dev->core.period_bytes;
b6050ef6
TI		 827 if (mod_link_pos >= fifo_size)
828 bound_pos = link_pos - mod_link_pos;
829 else if (mod_dma_pos >= mod_mini_pos)
830 bound_pos = mini_pos - mod_mini_pos;
831 else {
7833c3f8
TI		 832 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
833 if (bound_pos >= azx_dev->core.bufsize)
b6050ef6
TI		 834 bound_pos = 0;
835 }
836
837 /* Calculate real DMA position we want */
838 return bound_pos + mod_dma_pos;
839}
840
c02f77d3
TI		 841#define AMD_FIFO_SIZE 32
842
843/* get the current DMA position with FIFO size correction */
844static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev)
845{
846 struct snd_pcm_substream *substream = azx_dev->core.substream;
847 struct snd_pcm_runtime *runtime = substream->runtime;
848 unsigned int pos, delay;
849
850 pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
851 if (!runtime)
852 return pos;
853
854 runtime->delay = AMD_FIFO_SIZE;
855 delay = frames_to_bytes(runtime, AMD_FIFO_SIZE);
856 if (azx_dev->insufficient) {
857 if (pos < delay) {
858 delay = pos;
859 runtime->delay = bytes_to_frames(runtime, pos);
860 } else {
861 azx_dev->insufficient = 0;
862 }
863 }
864
865 /* correct the DMA position for capture stream */
866 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
867 if (pos < delay)
868 pos += azx_dev->core.bufsize;
869 pos -= delay;
870 }
871
872 return pos;
873}
874
875static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev,
876 unsigned int pos)
877{
878 struct snd_pcm_substream *substream = azx_dev->core.substream;
879
880 /* just read back the calculated value in the above */
881 return substream->runtime->delay;
882}
883
6f445784 884static void __azx_shutdown_chip(struct azx *chip, bool skip_link_reset)
472e18f6
ID		 885{
886 azx_stop_chip(chip);
6f445784
TI		 887 if (!skip_link_reset)
888 azx_enter_link_reset(chip);
472e18f6
ID		 889 azx_clear_irq_pending(chip);
890 display_power(chip, false);
891}
892
83012a7c 893#ifdef CONFIG_PM
65fcd41d
TI		 894static DEFINE_MUTEX(card_list_lock);
895static LIST_HEAD(card_list);
896
6f445784
TI		 897static void azx_shutdown_chip(struct azx *chip)
898{
899 __azx_shutdown_chip(chip, false);
900}
901
65fcd41d
TI		 902static void azx_add_card_list(struct azx *chip)
903{
9a34af4a 904 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 905 mutex_lock(&card_list_lock);
9a34af4a 906 list_add(&hda->list, &card_list);
65fcd41d
TI		 907 mutex_unlock(&card_list_lock);
908}
909
910static void azx_del_card_list(struct azx *chip)
911{
9a34af4a 912 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 913 mutex_lock(&card_list_lock);
9a34af4a 914 list_del_init(&hda->list);
65fcd41d
TI		 915 mutex_unlock(&card_list_lock);
916}
917
918/* trigger power-save check at writing parameter */
919static int param_set_xint(const char *val, const struct kernel_param *kp)
920{
9a34af4a 921 struct hda_intel *hda;
65fcd41d 922 struct azx *chip;
65fcd41d
TI		 923 int prev = power_save;
924 int ret = param_set_int(val, kp);
925
926 if (ret || prev == power_save)
927 return ret;
928
929 mutex_lock(&card_list_lock);
9a34af4a
TI		 930 list_for_each_entry(hda, &card_list, list) {
931 chip = &hda->chip;
a41d1224 932 if (!hda->probe_continued || chip->disabled)
65fcd41d 933 continue;
a41d1224 934 snd_hda_set_power_save(&chip->bus, power_save * 1000);
65fcd41d
TI		 935 }
936 mutex_unlock(&card_list_lock);
937 return 0;
938}
5c0b9bec 939
5c0b9bec
TI		 940/*
941 * power management
942 */
3baffc4a 943static bool azx_is_pm_ready(struct snd_card *card)
1da177e4 944{
2d9772ef
TI		 945 struct azx *chip;
946 struct hda_intel *hda;
1da177e4 947
2d9772ef 948 if (!card)
3baffc4a 949 return false;
2d9772ef
TI		 950 chip = card->private_data;
951 hda = container_of(chip, struct hda_intel, chip);
342e8449 952 if (chip->disabled || hda->init_failed || !chip->running)
3baffc4a
TI		 953 return false;
954 return true;
955}
956
f5dac54d 957static void __azx_runtime_resume(struct azx *chip)
3baffc4a
TI		 958{
959 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
960 struct hdac_bus *bus = azx_bus(chip);
961 struct hda_codec *codec;
962 int status;
963
e454ff8e
TI		 964 display_power(chip, true);
965 if (hda->need_i915_power)
966 snd_hdac_i915_set_bclk(bus);
3baffc4a
TI		 967
968 /* Read STATESTS before controller reset */
969 status = azx_readw(chip, STATESTS);
970
971 azx_init_pci(chip);
972 hda_intel_init_chip(chip, true);
973
f5dac54d
KHF		 974 /* Avoid codec resume if runtime resume is for system suspend */
975 if (!chip->pm_prepared) {
a6e7d0a4
KV		 976 list_for_each_codec(codec, &chip->bus) {
977 if (codec->relaxed_resume)
978 continue;
979
980 if (codec->forced_resume || (status & (1 << codec->addr)))
981 pm_request_resume(hda_codec_dev(codec));
982 }
3baffc4a
TI		 983 }
984
985 /* power down again for link-controlled chips */
e454ff8e 986 if (!hda->need_i915_power)
029d92c2 987 display_power(chip, false);
3baffc4a
TI		 988}
989
990#ifdef CONFIG_PM_SLEEP
f5dac54d
KHF		 991static int azx_prepare(struct device *dev)
992{
993 struct snd_card *card = dev_get_drvdata(dev);
994 struct azx *chip;
995
66affb7b
TI		 996 if (!azx_is_pm_ready(card))
997 return 0;
998
f5dac54d
KHF		 999 chip = card->private_data;
1000 chip->pm_prepared = 1;
c8f79808 1001 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
f5dac54d 1002
13661fc4
TI		 1003 flush_work(&azx_bus(chip)->unsol_work);
1004
f5dac54d
KHF		 1005 /* HDA controller always requires different WAKEEN for runtime suspend
1006 * and system suspend, so don't use direct-complete here.
1007 */
1008 return 0;
1009}
1010
1011static void azx_complete(struct device *dev)
1012{
1013 struct snd_card *card = dev_get_drvdata(dev);
1014 struct azx *chip;
1015
66affb7b
TI		 1016 if (!azx_is_pm_ready(card))
1017 return;
1018
f5dac54d 1019 chip = card->private_data;
c8f79808 1020 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
f5dac54d
KHF		 1021 chip->pm_prepared = 0;
1022}
1023
3baffc4a
TI		 1024static int azx_suspend(struct device *dev)
1025{
1026 struct snd_card *card = dev_get_drvdata(dev);
1027 struct azx *chip;
1028 struct hdac_bus *bus;
1029
1030 if (!azx_is_pm_ready(card))
c5c21523
TI		 1031 return 0;
1032
3baffc4a 1033 chip = card->private_data;
a41d1224 1034 bus = azx_bus(chip);
472e18f6 1035 azx_shutdown_chip(chip);
a41d1224
TI		 1036 if (bus->irq >= 0) {
1037 free_irq(bus->irq, chip);
1038 bus->irq = -1;
f36da940 1039 chip->card->sync_irq = -1;
30b35399 1040 }
a07187c9 1041
68e7fffc 1042 if (chip->msi)
43001c95 1043 pci_disable_msi(chip->pci);
785d8c4b
LY		 1044
1045 trace_azx_suspend(chip);
1da177e4
LT		 1046 return 0;
1047}
1048
68cb2b55 1049static int azx_resume(struct device *dev)
1da177e4 1050{
68cb2b55 1051 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef 1052 struct azx *chip;
2d9772ef 1053
3baffc4a 1054 if (!azx_is_pm_ready(card))
2d9772ef 1055 return 0;
1da177e4 1056
2d9772ef 1057 chip = card->private_data;
68e7fffc 1058 if (chip->msi)
3baffc4a 1059 if (pci_enable_msi(chip->pci) < 0)
68e7fffc
TI		 1060 chip->msi = 0;
1061 if (azx_acquire_irq(chip, 1) < 0)
30b35399 1062 return -EIO;
c4c8dd6e 1063
f5dac54d 1064 __azx_runtime_resume(chip);
785d8c4b
LY		 1065
1066 trace_azx_resume(chip);
1da177e4
LT		 1067 return 0;
1068}
b8dfc462 1069
3e6db33a
XZ		 1070/* put codec down to D3 at hibernation for Intel SKL+;
1071 * otherwise BIOS may still access the codec and screw up the driver
1072 */
3e6db33a
XZ		 1073static int azx_freeze_noirq(struct device *dev)
1074{
a4b4793f
TI		 1075 struct snd_card *card = dev_get_drvdata(dev);
1076 struct azx *chip = card->private_data;
3e6db33a
XZ		 1077 struct pci_dev *pci = to_pci_dev(dev);
1078
10db5bcc
TI		 1079 if (!azx_is_pm_ready(card))
1080 return 0;
a4b4793f 1081 if (chip->driver_type == AZX_DRIVER_SKL)
3e6db33a
XZ		 1082 pci_set_power_state(pci, PCI_D3hot);
1083
1084 return 0;
1085}
1086
1087static int azx_thaw_noirq(struct device *dev)
1088{
a4b4793f
TI		 1089 struct snd_card *card = dev_get_drvdata(dev);
1090 struct azx *chip = card->private_data;
3e6db33a
XZ		 1091 struct pci_dev *pci = to_pci_dev(dev);
1092
10db5bcc
TI		 1093 if (!azx_is_pm_ready(card))
1094 return 0;
a4b4793f 1095 if (chip->driver_type == AZX_DRIVER_SKL)
3e6db33a
XZ		 1096 pci_set_power_state(pci, PCI_D0);
1097
1098 return 0;
1099}
1100#endif /* CONFIG_PM_SLEEP */
1101
b8dfc462
ML		 1102static int azx_runtime_suspend(struct device *dev)
1103{
1104 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef 1105 struct azx *chip;
b8dfc462 1106
3baffc4a 1107 if (!azx_is_pm_ready(card))
2d9772ef 1108 return 0;
2d9772ef 1109 chip = card->private_data;
246efa4a 1110
7d4f606c 1111 /* enable controller wake up event */
f5dac54d 1112 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | STATESTS_INT_MASK);
7d4f606c 1113
472e18f6 1114 azx_shutdown_chip(chip);
785d8c4b 1115 trace_azx_runtime_suspend(chip);
b8dfc462
ML		 1116 return 0;
1117}
1118
1119static int azx_runtime_resume(struct device *dev)
1120{
1121 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef 1122 struct azx *chip;
b8dfc462 1123
3baffc4a 1124 if (!azx_is_pm_ready(card))
2d9772ef 1125 return 0;
2d9772ef 1126 chip = card->private_data;
f5dac54d 1127 __azx_runtime_resume(chip);
7d4f606c
WX		 1128
1129 /* disable controller Wake Up event*/
f5dac54d 1130 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & ~STATESTS_INT_MASK);
7d4f606c 1131
785d8c4b 1132 trace_azx_runtime_resume(chip);
b8dfc462
ML		 1133 return 0;
1134}
6eb827d2
TI		 1135
1136static int azx_runtime_idle(struct device *dev)
1137{
1138 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 1139 struct azx *chip;
1140 struct hda_intel *hda;
1141
1142 if (!card)
1143 return 0;
6eb827d2 1144
2d9772ef
TI		 1145 chip = card->private_data;
1146 hda = container_of(chip, struct hda_intel, chip);
1618e84a 1147 if (chip->disabled || hda->init_failed)
246efa4a
DA		 1148 return 0;
1149
55ed9cd1 1150 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
342e8449 1151 azx_bus(chip)->codec_powered || !chip->running)
6eb827d2
TI		 1152 return -EBUSY;
1153
37a3a98e 1154 /* ELD notification gets broken when HD-audio bus is off */
dd23e1d5 1155 if (needs_eld_notify_link(chip))
37a3a98e
TI		 1156 return -EBUSY;
1157
6eb827d2
TI		 1158 return 0;
1159}
1160
b8dfc462
ML		 1161static const struct dev_pm_ops azx_pm = {
1162 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
3e6db33a 1163#ifdef CONFIG_PM_SLEEP
f5dac54d
KHF		 1164 .prepare = azx_prepare,
1165 .complete = azx_complete,
3e6db33a
XZ		 1166 .freeze_noirq = azx_freeze_noirq,
1167 .thaw_noirq = azx_thaw_noirq,
1168#endif
6eb827d2 1169 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
b8dfc462
ML		 1170};
1171
68cb2b55
TI		 1172#define AZX_PM_OPS &azx_pm
1173#else
3baffc4a
TI		 1174#define azx_add_card_list(chip) /* NOP */
1175#define azx_del_card_list(chip) /* NOP */
68cb2b55 1176#define AZX_PM_OPS NULL
b8dfc462 1177#endif /* CONFIG_PM */
1da177e4
LT		 1178
1179
48c8b0eb 1180static int azx_probe_continue(struct azx *chip);
a82d51ed 1181
8393ec4a 1182#ifdef SUPPORT_VGA_SWITCHEROO
e23e7a14 1183static struct pci_dev *get_bound_vga(struct pci_dev *pci);
a82d51ed 1184
a82d51ed
TI		 1185static void azx_vs_set_state(struct pci_dev *pci,
1186 enum vga_switcheroo_state state)
1187{
1188 struct snd_card *card = pci_get_drvdata(pci);
1189 struct azx *chip = card->private_data;
9a34af4a 1190 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
07f4f97d 1191 struct hda_codec *codec;
a82d51ed
TI		 1192 bool disabled;
1193
9a34af4a
TI		 1194 wait_for_completion(&hda->probe_wait);
1195 if (hda->init_failed)
a82d51ed
TI		 1196 return;
1197
1198 disabled = (state == VGA_SWITCHEROO_OFF);
1199 if (chip->disabled == disabled)
1200 return;
1201
a41d1224 1202 if (!hda->probe_continued) {
a82d51ed
TI		 1203 chip->disabled = disabled;
1204 if (!disabled) {
4e76a883
TI		 1205 dev_info(chip->card->dev,
1206 "Start delayed initialization\n");
2393e755 1207 if (azx_probe_continue(chip) < 0)
4e76a883 1208 dev_err(chip->card->dev, "initialization error\n");
a82d51ed
TI		 1209 }
1210 } else {
2b760d88 1211 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
4e76a883 1212 disabled ? "Disabling" : "Enabling");
a82d51ed 1213 if (disabled) {
07f4f97d
LW		 1214 list_for_each_codec(codec, &chip->bus) {
1215 pm_runtime_suspend(hda_codec_dev(codec));
1216 pm_runtime_disable(hda_codec_dev(codec));
1217 }
1218 pm_runtime_suspend(card->dev);
1219 pm_runtime_disable(card->dev);
2b760d88 1220 /* when we get suspended by vga_switcheroo we end up in D3cold,
246efa4a
DA		 1221 * however we have no ACPI handle, so pci/acpi can't put us there,
1222 * put ourselves there */
1223 pci->current_state = PCI_D3cold;
a82d51ed 1224 chip->disabled = true;
a41d1224 1225 if (snd_hda_lock_devices(&chip->bus))
4e76a883
TI		 1226 dev_warn(chip->card->dev,
1227 "Cannot lock devices!\n");
a82d51ed 1228 } else {
a41d1224 1229 snd_hda_unlock_devices(&chip->bus);
a82d51ed 1230 chip->disabled = false;
07f4f97d
LW		 1231 pm_runtime_enable(card->dev);
1232 list_for_each_codec(codec, &chip->bus) {
1233 pm_runtime_enable(hda_codec_dev(codec));
1234 pm_runtime_resume(hda_codec_dev(codec));
1235 }
a82d51ed
TI		 1236 }
1237 }
1238}
1239
1240static bool azx_vs_can_switch(struct pci_dev *pci)
1241{
1242 struct snd_card *card = pci_get_drvdata(pci);
1243 struct azx *chip = card->private_data;
9a34af4a 1244 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed 1245
9a34af4a
TI		 1246 wait_for_completion(&hda->probe_wait);
1247 if (hda->init_failed)
a82d51ed 1248 return false;
a41d1224 1249 if (chip->disabled || !hda->probe_continued)
a82d51ed 1250 return true;
a41d1224 1251 if (snd_hda_lock_devices(&chip->bus))
a82d51ed 1252 return false;
a41d1224 1253 snd_hda_unlock_devices(&chip->bus);
a82d51ed
TI		 1254 return true;
1255}
1256
37a3a98e
TI		 1257/*
1258 * The discrete GPU cannot power down unless the HDA controller runtime
1259 * suspends, so activate runtime PM on codecs even if power_save == 0.
1260 */
1261static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1262{
1263 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1264 struct hda_codec *codec;
1265
dd23e1d5 1266 if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) {
37a3a98e
TI		 1267 list_for_each_codec(codec, &chip->bus)
1268 codec->auto_runtime_pm = 1;
1269 /* reset the power save setup */
1270 if (chip->running)
1271 set_default_power_save(chip);
1272 }
1273}
1274
1275static void azx_vs_gpu_bound(struct pci_dev *pci,
1276 enum vga_switcheroo_client_id client_id)
1277{
1278 struct snd_card *card = pci_get_drvdata(pci);
1279 struct azx *chip = card->private_data;
37a3a98e
TI		 1280
1281 if (client_id == VGA_SWITCHEROO_DIS)
dd23e1d5 1282 chip->bus.keep_power = 0;
37a3a98e
TI		 1283 setup_vga_switcheroo_runtime_pm(chip);
1284}
1285
e23e7a14 1286static void init_vga_switcheroo(struct azx *chip)
a82d51ed 1287{
9a34af4a 1288 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed 1289 struct pci_dev *p = get_bound_vga(chip->pci);
bacd8614 1290 struct pci_dev *parent;
a82d51ed 1291 if (p) {
4e76a883 1292 dev_info(chip->card->dev,
2b760d88 1293 "Handle vga_switcheroo audio client\n");
9a34af4a 1294 hda->use_vga_switcheroo = 1;
bacd8614
KHF		 1295
1296 /* cleared in either gpu_bound op or codec probe, or when its
1297 * upstream port has _PR3 (i.e. dGPU).
1298 */
1299 parent = pci_upstream_bridge(p);
1300 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1;
07f4f97d 1301 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
a82d51ed
TI		 1302 pci_dev_put(p);
1303 }
1304}
1305
1306static const struct vga_switcheroo_client_ops azx_vs_ops = {
1307 .set_gpu_state = azx_vs_set_state,
1308 .can_switch = azx_vs_can_switch,
37a3a98e 1309 .gpu_bound = azx_vs_gpu_bound,
a82d51ed
TI		 1310};
1311
e23e7a14 1312static int register_vga_switcheroo(struct azx *chip)
a82d51ed 1313{
9a34af4a 1314 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
4aaf448f 1315 struct pci_dev *p;
128960a9
TI		 1316 int err;
1317
9a34af4a 1318 if (!hda->use_vga_switcheroo)
a82d51ed 1319 return 0;
4aaf448f
JQ		 1320
1321 p = get_bound_vga(chip->pci);
1322 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1323 pci_dev_put(p);
1324
128960a9
TI		 1325 if (err < 0)
1326 return err;
9a34af4a 1327 hda->vga_switcheroo_registered = 1;
246efa4a 1328
128960a9 1329 return 0;
a82d51ed
TI		 1330}
1331#else
1332#define init_vga_switcheroo(chip) /* NOP */
1333#define register_vga_switcheroo(chip) 0
8393ec4a 1334#define check_hdmi_disabled(pci) false
37a3a98e 1335#define setup_vga_switcheroo_runtime_pm(chip) /* NOP */
a82d51ed
TI		 1336#endif /* SUPPORT_VGA_SWITCHER */
1337
1da177e4
LT		 1338/*
1339 * destructor
1340 */
2393e755 1341static void azx_free(struct azx *chip)
1da177e4 1342{
c67e2228 1343 struct pci_dev *pci = chip->pci;
a07187c9 1344 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a41d1224 1345 struct hdac_bus *bus = azx_bus(chip);
4ce107b9 1346
2393e755
TI		 1347 if (hda->freed)
1348 return;
1349
4f66a9ef 1350 if (azx_has_pm_runtime(chip) && chip->running) {
c67e2228 1351 pm_runtime_get_noresume(&pci->dev);
4f66a9ef
TI		 1352 pm_runtime_forbid(&pci->dev);
1353 pm_runtime_dont_use_autosuspend(&pci->dev);
1354 }
1355
37a3a98e 1356 chip->running = 0;
c67e2228 1357
65fcd41d
TI		 1358 azx_del_card_list(chip);
1359
9a34af4a
TI		 1360 hda->init_failed = 1; /* to be sure */
1361 complete_all(&hda->probe_wait);
f4c482a4 1362
9a34af4a 1363 if (use_vga_switcheroo(hda)) {
a41d1224
TI		 1364 if (chip->disabled && hda->probe_continued)
1365 snd_hda_unlock_devices(&chip->bus);
07f4f97d 1366 if (hda->vga_switcheroo_registered)
128960a9 1367 vga_switcheroo_unregister_client(chip->pci);
a82d51ed
TI		 1368 }
1369
a41d1224 1370 if (bus->chip_init) {
9ad593f6 1371 azx_clear_irq_pending(chip);
7833c3f8 1372 azx_stop_all_streams(chip);
1a7f60b9 1373 azx_stop_chip(chip);
1da177e4
LT		 1374 }
1375
a41d1224
TI		 1376 if (bus->irq >= 0)
1377 free_irq(bus->irq, (void*)chip);
1da177e4 1378
67908994 1379 azx_free_stream_pages(chip);
a41d1224
TI		 1380 azx_free_streams(chip);
1381 snd_hdac_bus_exit(bus);
1382
4918cdab 1383#ifdef CONFIG_SND_HDA_PATCH_LOADER
f0acd28c 1384 release_firmware(chip->fw);
4918cdab 1385#endif
e454ff8e 1386 display_power(chip, false);
98d8fc6c 1387
fc18282c 1388 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
fcc88d91 1389 snd_hdac_i915_exit(bus);
1da177e4 1390
2393e755 1391 hda->freed = 1;
1da177e4
LT		 1392}
1393
a41d1224
TI		 1394static int azx_dev_disconnect(struct snd_device *device)
1395{
1396 struct azx *chip = device->device_data;
ca58f551 1397 struct hdac_bus *bus = azx_bus(chip);
a41d1224
TI		 1398
1399 chip->bus.shutdown = 1;
ca58f551
TI		 1400 cancel_work_sync(&bus->unsol_work);
1401
a41d1224
TI		 1402 return 0;
1403}
1404
a98f90fd 1405static int azx_dev_free(struct snd_device *device)
1da177e4 1406{
2393e755
TI		 1407 azx_free(device->device_data);
1408 return 0;
1da177e4
LT		 1409}
1410
8393ec4a 1411#ifdef SUPPORT_VGA_SWITCHEROO
586bc4aa
AD		 1412#ifdef CONFIG_ACPI
1413/* ATPX is in the integrated GPU's namespace */
1414static bool atpx_present(void)
1415{
1416 struct pci_dev *pdev = NULL;
1417 acpi_handle dhandle, atpx_handle;
1418 acpi_status status;
1419
9ed8fcfd
SJ		 1420 while ((pdev = pci_get_base_class(PCI_BASE_CLASS_DISPLAY, pdev))) {
1421 if ((pdev->class != PCI_CLASS_DISPLAY_VGA << 8) &&
1422 (pdev->class != PCI_CLASS_DISPLAY_OTHER << 8))
1423 continue;
1424
586bc4aa
AD		 1425 dhandle = ACPI_HANDLE(&pdev->dev);
1426 if (dhandle) {
1427 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
10e92724 1428 if (ACPI_SUCCESS(status)) {
586bc4aa
AD		 1429 pci_dev_put(pdev);
1430 return true;
1431 }
1432 }
586bc4aa
AD		 1433 }
1434 return false;
1435}
1436#else
1437static bool atpx_present(void)
1438{
1439 return false;
1440}
1441#endif
1442
9121947d 1443/*
2b760d88 1444 * Check of disabled HDMI controller by vga_switcheroo
9121947d 1445 */
e23e7a14 1446static struct pci_dev *get_bound_vga(struct pci_dev *pci)
9121947d
TI		 1447{
1448 struct pci_dev *p;
1449
1450 /* check only discrete GPU */
1451 switch (pci->vendor) {
1452 case PCI_VENDOR_ID_ATI:
1453 case PCI_VENDOR_ID_AMD:
586bc4aa
AD		 1454 if (pci->devfn == 1) {
1455 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1456 pci->bus->number, 0);
1457 if (p) {
1458 /* ATPX is in the integrated GPU's ACPI namespace
1459 * rather than the dGPU's namespace. However,
1460 * the dGPU is the one who is involved in
1461 * vgaswitcheroo.
1462 */
1463 if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) &&
5beb5627 1464 (atpx_present() || apple_gmux_detect(NULL, NULL)))
586bc4aa
AD		 1465 return p;
1466 pci_dev_put(p);
1467 }
1468 }
1469 break;
9121947d
TI		 1470 case PCI_VENDOR_ID_NVIDIA:
1471 if (pci->devfn == 1) {
1472 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1473 pci->bus->number, 0);
1474 if (p) {
b6d7b362 1475 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
9121947d
TI		 1476 return p;
1477 pci_dev_put(p);
1478 }
1479 }
1480 break;
1481 }
1482 return NULL;
1483}
1484
e23e7a14 1485static bool check_hdmi_disabled(struct pci_dev *pci)
9121947d
TI		 1486{
1487 bool vga_inactive = false;
1488 struct pci_dev *p = get_bound_vga(pci);
1489
1490 if (p) {
12b78a7f 1491 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 1492 vga_inactive = true;
1493 pci_dev_put(p);
1494 }
1495 return vga_inactive;
1496}
8393ec4a 1497#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 1498
3372a153 1499/*
6317e5eb 1500 * allow/deny-listing for position_fix
3372a153 1501 */
a5dc05e4 1502static const struct snd_pci_quirk position_fix_list[] = {
d2e1c973
TI		 1503 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1504 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 1505 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 1506 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 1507 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 1508 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 1509 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 1510 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 1511 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 1512 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 1513 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 1514 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 1515 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 1516 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 1517 {}
1518};
1519
e23e7a14 1520static int check_position_fix(struct azx *chip, int fix)
3372a153
TI		 1521{
1522 const struct snd_pci_quirk *q;
1523
c673ba1c 1524 switch (fix) {
1dac6695 1525 case POS_FIX_AUTO:
c673ba1c
TI		 1526 case POS_FIX_LPIB:
1527 case POS_FIX_POSBUF:
4cb36310 1528 case POS_FIX_VIACOMBO:
a6f2fd55 1529 case POS_FIX_COMBO:
f87e7f25 1530 case POS_FIX_SKL:
c02f77d3 1531 case POS_FIX_FIFO:
c673ba1c
TI		 1532 return fix;
1533 }
1534
c673ba1c
TI		 1535 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1536 if (q) {
4e76a883
TI		 1537 dev_info(chip->card->dev,
1538 "position_fix set to %d for device %04x:%04x\n",
1539 q->value, q->subvendor, q->subdevice);
c673ba1c 1540 return q->value;
3372a153 1541 }
bdd9ef24
DH		 1542
1543 /* Check VIA/ATI HD Audio Controller exist */
26f05717 1544 if (chip->driver_type == AZX_DRIVER_VIA) {
4e76a883 1545 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
bdd9ef24 1546 return POS_FIX_VIACOMBO;
9477c58e 1547 }
c02f77d3
TI		 1548 if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) {
1549 dev_dbg(chip->card->dev, "Using FIFO position fix\n");
1550 return POS_FIX_FIFO;
1551 }
9477c58e 1552 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
4e76a883 1553 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
50e3bbf9 1554 return POS_FIX_LPIB;
bdd9ef24 1555 }
a4b4793f 1556 if (chip->driver_type == AZX_DRIVER_SKL) {
f87e7f25
TI		 1557 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1558 return POS_FIX_SKL;
1559 }
c673ba1c 1560 return POS_FIX_AUTO;
3372a153
TI		 1561}
1562
b6050ef6
TI		 1563static void assign_position_fix(struct azx *chip, int fix)
1564{
bf82326f 1565 static const azx_get_pos_callback_t callbacks[] = {
b6050ef6
TI		 1566 [POS_FIX_AUTO] = NULL,
1567 [POS_FIX_LPIB] = azx_get_pos_lpib,
1568 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1569 [POS_FIX_VIACOMBO] = azx_via_get_position,
1570 [POS_FIX_COMBO] = azx_get_pos_lpib,
c4ca3871 1571 [POS_FIX_SKL] = azx_get_pos_posbuf,
c02f77d3 1572 [POS_FIX_FIFO] = azx_get_pos_fifo,
b6050ef6
TI		 1573 };
1574
1575 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1576
1577 /* combo mode uses LPIB only for playback */
1578 if (fix == POS_FIX_COMBO)
1579 chip->get_position[1] = NULL;
1580
f87e7f25 1581 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
b6050ef6
TI		 1582 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1583 chip->get_delay[0] = chip->get_delay[1] =
1584 azx_get_delay_from_lpib;
1585 }
1586
c02f77d3
TI		 1587 if (fix == POS_FIX_FIFO)
1588 chip->get_delay[0] = chip->get_delay[1] =
1589 azx_get_delay_from_fifo;
b6050ef6
TI		 1590}
1591
669ba27a 1592/*
6317e5eb 1593 * deny-lists for probe_mask
669ba27a 1594 */
a5dc05e4 1595static const struct snd_pci_quirk probe_mask_list[] = {
669ba27a
TI		 1596 /* Thinkpad often breaks the controller communication when accessing
1597 * to the non-working (or non-existing) modem codec slot.
1598 */
1599 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1600 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1601 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 1602 /* broken BIOS */
1603 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 1604 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1605 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 1606 /* forced codec slots */
93574844 1607 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 1608 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
dd8e5b16 1609 SND_PCI_QUIRK(0x1558, 0x0351, "Schenker Dock 15", 0x105),
f3af9051
JK		 1610 /* WinFast VP200 H (Teradici) user reported broken communication */
1611 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 1612 {}
1613};
1614
f1eaaeec
TI		 1615#define AZX_FORCE_CODEC_MASK 0x100
1616
e23e7a14 1617static void check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 1618{
1619 const struct snd_pci_quirk *q;
1620
f1eaaeec
TI		 1621 chip->codec_probe_mask = probe_mask[dev];
1622 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 1623 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1624 if (q) {
4e76a883
TI		 1625 dev_info(chip->card->dev,
1626 "probe_mask set to 0x%x for device %04x:%04x\n",
1627 q->value, q->subvendor, q->subdevice);
f1eaaeec 1628 chip->codec_probe_mask = q->value;
669ba27a
TI		 1629 }
1630 }
f1eaaeec
TI		 1631
1632 /* check forced option */
1633 if (chip->codec_probe_mask != -1 &&
1634 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
a41d1224 1635 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
4e76a883 1636 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
a41d1224 1637 (int)azx_bus(chip)->codec_mask);
f1eaaeec 1638 }
669ba27a
TI		 1639}
1640
4d8e22e0 1641/*
6317e5eb 1642 * allow/deny-list for enable_msi
4d8e22e0 1643 */
6317e5eb 1644static const struct snd_pci_quirk msi_deny_list[] = {
693e0cb0
DH		 1645 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1646 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1647 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1648 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
9dc8398b 1649 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 1650 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 1651 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
83f72151 1652 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
4193d13b 1653 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 1654 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 1655 {}
1656};
1657
e23e7a14 1658static void check_msi(struct azx *chip)
4d8e22e0
TI		 1659{
1660 const struct snd_pci_quirk *q;
1661
71623855
TI		 1662 if (enable_msi >= 0) {
1663 chip->msi = !!enable_msi;
4d8e22e0 1664 return;
71623855
TI		 1665 }
1666 chip->msi = 1; /* enable MSI as default */
6317e5eb 1667 q = snd_pci_quirk_lookup(chip->pci, msi_deny_list);
4d8e22e0 1668 if (q) {
4e76a883
TI		 1669 dev_info(chip->card->dev,
1670 "msi for device %04x:%04x set to %d\n",
1671 q->subvendor, q->subdevice, q->value);
4d8e22e0 1672 chip->msi = q->value;
80c43ed7
TI		 1673 return;
1674 }
1675
1676 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e 1677 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
4e76a883 1678 dev_info(chip->card->dev, "Disabling MSI\n");
80c43ed7 1679 chip->msi = 0;
4d8e22e0
TI		 1680 }
1681}
1682
a1585d76 1683/* check the snoop mode availability */
e23e7a14 1684static void azx_check_snoop_available(struct azx *chip)
a1585d76 1685{
7c732015 1686 int snoop = hda_snoop;
a1585d76 1687
7c732015
TI		 1688 if (snoop >= 0) {
1689 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1690 snoop ? "snoop" : "non-snoop");
1691 chip->snoop = snoop;
78c9be61 1692 chip->uc_buffer = !snoop;
7c732015
TI		 1693 return;
1694 }
1695
1696 snoop = true;
37e661ee
TI		 1697 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1698 chip->driver_type == AZX_DRIVER_VIA) {
a1585d76
TI		 1699 /* force to non-snoop mode for a new VIA controller
1700 * when BIOS is set
1701 */
7c732015
TI		 1702 u8 val;
1703 pci_read_config_byte(chip->pci, 0x42, &val);
af52f998
DW		 1704 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1705 chip->pci->revision == 0x20))
7c732015 1706 snoop = false;
a1585d76
TI		 1707 }
1708
37e661ee
TI		 1709 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1710 snoop = false;
1711
7c732015 1712 chip->snoop = snoop;
78c9be61 1713 if (!snoop) {
7c732015 1714 dev_info(chip->card->dev, "Force to non-snoop mode\n");
78c9be61
TI		 1715 /* C-Media requires non-cached pages only for CORB/RIRB */
1716 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1717 chip->uc_buffer = true;
1718 }
a1585d76 1719}
669ba27a 1720
99a2008d
WX		 1721static void azx_probe_work(struct work_struct *work)
1722{
c0f1886d 1723 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work.work);
9a34af4a 1724 azx_probe_continue(&hda->chip);
99a2008d 1725}
99a2008d 1726
4f0189be
TI		 1727static int default_bdl_pos_adj(struct azx *chip)
1728{
2cf721db
TI		 1729 /* some exceptions: Atoms seem problematic with value 1 */
1730 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1731 switch (chip->pci->device) {
1732 case 0x0f04: /* Baytrail */
1733 case 0x2284: /* Braswell */
1734 return 32;
1735 }
1736 }
1737
4f0189be 1738 switch (chip->driver_type) {
c51e4310 1739 /*
1740 * increase the bdl size for Glenfly Gpus for hardware
1741 * limitation on hdac interrupt interval
1742 */
1743 case AZX_DRIVER_GFHDMI:
1744 return 128;
4f0189be
TI		 1745 case AZX_DRIVER_ICH:
1746 case AZX_DRIVER_PCH:
1747 return 1;
1748 default:
1749 return 32;
1750 }
1751}
1752
1da177e4
LT		 1753/*
1754 * constructor
1755 */
a43ff5ba
TI		 1756static const struct hda_controller_ops pci_hda_ops;
1757
e23e7a14
BP		 1758static int azx_create(struct snd_card *card, struct pci_dev *pci,
1759 int dev, unsigned int driver_caps,
1760 struct azx **rchip)
1da177e4 1761{
41f394a8 1762 static const struct snd_device_ops ops = {
a41d1224 1763 .dev_disconnect = azx_dev_disconnect,
1da177e4
LT		 1764 .dev_free = azx_dev_free,
1765 };
a07187c9 1766 struct hda_intel *hda;
a82d51ed
TI		 1767 struct azx *chip;
1768 int err;
1da177e4
LT		 1769
1770 *rchip = NULL;
bcd72003 1771
3fcaf24e 1772 err = pcim_enable_device(pci);
927fc866 1773 if (err < 0)
1da177e4
LT		 1774 return err;
1775
2393e755 1776 hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL);
3fcaf24e 1777 if (!hda)
1da177e4 1778 return -ENOMEM;
1da177e4 1779
a07187c9 1780 chip = &hda->chip;
62932df8 1781 mutex_init(&chip->open_mutex);
1da177e4
LT		 1782 chip->card = card;
1783 chip->pci = pci;
a43ff5ba 1784 chip->ops = &pci_hda_ops;
9477c58e
TI		 1785 chip->driver_caps = driver_caps;
1786 chip->driver_type = driver_caps & 0xff;
4d8e22e0 1787 check_msi(chip);
555e219f 1788 chip->dev_index = dev;
3a182c84
TI		 1789 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1790 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
01b65bfb 1791 INIT_LIST_HEAD(&chip->pcm_list);
9a34af4a
TI		 1792 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1793 INIT_LIST_HEAD(&hda->list);
a82d51ed 1794 init_vga_switcheroo(chip);
9a34af4a 1795 init_completion(&hda->probe_wait);
1da177e4 1796
b6050ef6 1797 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
a6f2fd55 1798
41438f13
TI		 1799 if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1800 chip->fallback_to_single_cmd = 1;
1801 else /* explicitly set to single_cmd or not */
1802 chip->single_cmd = single_cmd;
1803
a1585d76 1804 azx_check_snoop_available(chip);
c74db86b 1805
4f0189be
TI		 1806 if (bdl_pos_adj[dev] < 0)
1807 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1808 else
1809 chip->bdl_pos_adj = bdl_pos_adj[dev];
5c0d7bc1 1810
19abfefd 1811 err = azx_bus_init(chip, model[dev]);
3fcaf24e 1812 if (err < 0)
a41d1224 1813 return err;
a41d1224 1814
619a1f19
TI		 1815 /* use the non-cached pages in non-snoop mode */
1816 if (!azx_snoop(chip))
37137ec2 1817 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_WC_SG;
619a1f19 1818
7d9a1808
TI		 1819 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1820 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
5f2cb361 1821 chip->bus.core.needs_damn_long_delay = 1;
7d9a1808
TI		 1822 }
1823
6317f744
TI		 1824 check_probe_mask(chip, dev);
1825
a82d51ed
TI		 1826 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1827 if (err < 0) {
4e76a883 1828 dev_err(card->dev, "Error creating device [card]!\n");
a82d51ed
TI		 1829 azx_free(chip);
1830 return err;
1831 }
1832
99a2008d 1833 /* continue probing in work context as may trigger request module */
c0f1886d 1834 INIT_DELAYED_WORK(&hda->probe_work, azx_probe_work);
99a2008d 1835
a82d51ed 1836 *rchip = chip;
99a2008d 1837
a82d51ed
TI		 1838 return 0;
1839}
1840
48c8b0eb 1841static int azx_first_init(struct azx *chip)
a82d51ed
TI		 1842{
1843 int dev = chip->dev_index;
1844 struct pci_dev *pci = chip->pci;
1845 struct snd_card *card = chip->card;
a41d1224 1846 struct hdac_bus *bus = azx_bus(chip);
67908994 1847 int err;
a82d51ed 1848 unsigned short gcap;
413cbf46 1849 unsigned int dma_bits = 64;
a82d51ed 1850
07e4ca50
TI		 1851#if BITS_PER_LONG != 64
1852 /* Fix up base address on ULI M5461 */
1853 if (chip->driver_type == AZX_DRIVER_ULI) {
1854 u16 tmp3;
1855 pci_read_config_word(pci, 0x40, &tmp3);
1856 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1857 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1858 }
1859#endif
c51e4310 1860 /*
1861 * Fix response write request not synced to memory when handle
1862 * hdac interrupt on Glenfly Gpus
1863 */
1864 if (chip->driver_type == AZX_DRIVER_GFHDMI)
1865 bus->polling_mode = 1;
07e4ca50 1866
cbc3e98a
YS		 1867 if (chip->driver_type == AZX_DRIVER_LOONGSON) {
1868 bus->polling_mode = 1;
1869 bus->not_use_interrupts = 1;
942ccdd8 1870 bus->access_sdnctl_in_dword = 1;
cbc3e98a
YS		 1871 }
1872
3fcaf24e 1873 err = pcim_iomap_regions(pci, 1 << 0, "ICH HD audio");
a82d51ed 1874 if (err < 0)
1da177e4 1875 return err;
1da177e4 1876
a41d1224 1877 bus->addr = pci_resource_start(pci, 0);
3fcaf24e 1878 bus->remap_addr = pcim_iomap_table(pci)[0];
1da177e4 1879
a4b4793f 1880 if (chip->driver_type == AZX_DRIVER_SKL)
50279d9b
GS		 1881 snd_hdac_bus_parse_capabilities(bus);
1882
1883 /*
1884 * Some Intel CPUs has always running timer (ART) feature and
1885 * controller may have Global time sync reporting capability, so
1886 * check both of these before declaring synchronized time reporting
1887 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1888 */
1889 chip->gts_present = false;
1890
1891#ifdef CONFIG_X86
1892 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1893 chip->gts_present = true;
1894#endif
1895
db79afa1
BH		 1896 if (chip->msi) {
1897 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1898 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1899 pci->no_64bit_msi = true;
1900 }
68e7fffc
TI		 1901 if (pci_enable_msi(pci) < 0)
1902 chip->msi = 0;
db79afa1 1903 }
7376d013 1904
1da177e4 1905 pci_set_master(pci);
1da177e4 1906
bcd72003 1907 gcap = azx_readw(chip, GCAP);
4e76a883 1908 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
bcd72003 1909
413cbf46
TI		 1910 /* AMD devices support 40 or 48bit DMA, take the safe one */
1911 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1912 dma_bits = 40;
1913
dc4c2e6b 1914 /* disable SB600 64bit support for safety */
9477c58e 1915 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b 1916 struct pci_dev *p_smbus;
413cbf46 1917 dma_bits = 40;
dc4c2e6b
AB		 1918 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1919 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1920 NULL);
1921 if (p_smbus) {
1922 if (p_smbus->revision < 0x30)
fb1d8ac2 1923 gcap &= ~AZX_GCAP_64OK;
dc4c2e6b
AB		 1924 pci_dev_put(p_smbus);
1925 }
1926 }
09240cf4 1927
3ab7511e
AB		 1928 /* NVidia hardware normally only supports up to 40 bits of DMA */
1929 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1930 dma_bits = 40;
1931
9477c58e
TI		 1932 /* disable 64bit DMA address on some devices */
1933 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
4e76a883 1934 dev_dbg(card->dev, "Disabling 64bit DMA\n");
fb1d8ac2 1935 gcap &= ~AZX_GCAP_64OK;
9477c58e 1936 }
396087ea 1937
2ae66c26 1938 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 1939 if (align_buffer_size >= 0)
1940 chip->align_buffer_size = !!align_buffer_size;
1941 else {
103884a3 1942 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
7bfe059e 1943 chip->align_buffer_size = 0;
7bfe059e
TI		 1944 else
1945 chip->align_buffer_size = 1;
1946 }
2ae66c26 1947
cf7aaca8 1948 /* allow 64bit DMA address if supported by H/W */
413cbf46
TI		 1949 if (!(gcap & AZX_GCAP_64OK))
1950 dma_bits = 32;
669f65ea
TI		 1951 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(dma_bits)))
1952 dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32));
acd289e0 1953 dma_set_max_seg_size(&pci->dev, UINT_MAX);
cf7aaca8 1954
8b6ed8e7
TI		 1955 /* read number of streams from GCAP register instead of using
1956 * hardcoded value
1957 */
1958 chip->capture_streams = (gcap >> 8) & 0x0f;
1959 chip->playback_streams = (gcap >> 12) & 0x0f;
1960 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 1961 /* gcap didn't give any info, switching to old method */
1962
1963 switch (chip->driver_type) {
1964 case AZX_DRIVER_ULI:
1965 chip->playback_streams = ULI_NUM_PLAYBACK;
1966 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 1967 break;
1968 case AZX_DRIVER_ATIHDMI:
1815b34a 1969 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 1970 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1971 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 1972 break;
c51e4310 1973 case AZX_DRIVER_GFHDMI:
c4da29ca 1974 case AZX_DRIVER_GENERIC:
bcd72003
TD		 1975 default:
1976 chip->playback_streams = ICH6_NUM_PLAYBACK;
1977 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 1978 break;
1979 }
07e4ca50 1980 }
8b6ed8e7
TI		 1981 chip->capture_index_offset = 0;
1982 chip->playback_index_offset = chip->capture_streams;
07e4ca50 1983 chip->num_streams = chip->playback_streams + chip->capture_streams;
07e4ca50 1984
df56c3db
JK		 1985 /* sanity check for the SDxCTL.STRM field overflow */
1986 if (chip->num_streams > 15 &&
1987 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1988 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1989 "forcing separate stream tags", chip->num_streams);
1990 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1991 }
1992
a41d1224
TI		 1993 /* initialize streams */
1994 err = azx_init_streams(chip);
81740861 1995 if (err < 0)
a82d51ed 1996 return err;
1da177e4 1997
a41d1224
TI		 1998 err = azx_alloc_stream_pages(chip);
1999 if (err < 0)
2000 return err;
1da177e4
LT		 2001
2002 /* initialize chip */
cb53c626 2003 azx_init_pci(chip);
e4d9e513 2004
e454ff8e 2005 snd_hdac_i915_set_bclk(bus);
e4d9e513 2006
0a673521 2007 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 2008
2009 /* codec detection */
a41d1224 2010 if (!azx_bus(chip)->codec_mask) {
4e76a883 2011 dev_err(card->dev, "no codecs found!\n");
9479e75f 2012 /* keep running the rest for the runtime PM */
1da177e4
LT		 2013 }
2014
f495222e
TI		 2015 if (azx_acquire_irq(chip, 0) < 0)
2016 return -EBUSY;
2017
07e4ca50 2018 strcpy(card->driver, "HDA-Intel");
75b1a8f9 2019 strscpy(card->shortname, driver_short_names[chip->driver_type],
18cb7109
TI		 2020 sizeof(card->shortname));
2021 snprintf(card->longname, sizeof(card->longname),
2022 "%s at 0x%lx irq %i",
a41d1224 2023 card->shortname, bus->addr, bus->irq);
07e4ca50 2024
1da177e4 2025 return 0;
1da177e4
LT		 2026}
2027
97c6a3d1 2028#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 2029/* callback from request_firmware_nowait() */
2030static void azx_firmware_cb(const struct firmware *fw, void *context)
2031{
2032 struct snd_card *card = context;
2033 struct azx *chip = card->private_data;
5cb543db 2034
25faa4bd
TI		 2035 if (fw)
2036 chip->fw = fw;
2037 else
2038 dev_err(card->dev, "Cannot load firmware, continue without patching\n");
5cb543db
TI		 2039 if (!chip->disabled) {
2040 /* continue probing */
25faa4bd 2041 azx_probe_continue(chip);
5cb543db 2042 }
5cb543db 2043}
97c6a3d1 2044#endif
5cb543db 2045
f46ea609
DR		 2046static int disable_msi_reset_irq(struct azx *chip)
2047{
a41d1224 2048 struct hdac_bus *bus = azx_bus(chip);
f46ea609
DR		 2049 int err;
2050
a41d1224
TI		 2051 free_irq(bus->irq, chip);
2052 bus->irq = -1;
f36da940 2053 chip->card->sync_irq = -1;
f46ea609
DR		 2054 pci_disable_msi(chip->pci);
2055 chip->msi = 0;
2056 err = azx_acquire_irq(chip, 1);
2057 if (err < 0)
2058 return err;
2059
2060 return 0;
2061}
2062
6317e5eb 2063/* Denylist for skipping the whole probe:
3c6fd1f0
TI		 2064 * some HD-audio PCI entries are exposed without any codecs, and such devices
2065 * should be ignored from the beginning.
2066 */
6317e5eb 2067static const struct pci_device_id driver_denylist[] = {
977dfef4
TI		 2068 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */
2069 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */
2070 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */
df42ee7e 2071 { PCI_DEVICE_SUB(0x1022, 0x15e3, 0x1022, 0xd601) }, /* ASRock X670E Taichi */
3c6fd1f0
TI		 2072 {}
2073};
2074
a43ff5ba
TI		 2075static const struct hda_controller_ops pci_hda_ops = {
2076 .disable_msi_reset_irq = disable_msi_reset_irq,
7ca954a8 2077 .position_check = azx_position_check,
40830813
DR		 2078};
2079
69458e2c
TI		 2080static DECLARE_BITMAP(probed_devs, SNDRV_CARDS);
2081
e23e7a14
BP		 2082static int azx_probe(struct pci_dev *pci,
2083 const struct pci_device_id *pci_id)
1da177e4 2084{
a98f90fd 2085 struct snd_card *card;
9a34af4a 2086 struct hda_intel *hda;
a98f90fd 2087 struct azx *chip;
aad730d0 2088 bool schedule_probe;
69458e2c 2089 int dev;
927fc866 2090 int err;
1da177e4 2091
6317e5eb
TI		 2092 if (pci_match_id(driver_denylist, pci)) {
2093 dev_info(&pci->dev, "Skipping the device on the denylist\n");
3c6fd1f0
TI		 2094 return -ENODEV;
2095 }
2096
69458e2c 2097 dev = find_first_zero_bit(probed_devs, SNDRV_CARDS);
5aba4f8e
TI		 2098 if (dev >= SNDRV_CARDS)
2099 return -ENODEV;
2100 if (!enable[dev]) {
69458e2c 2101 set_bit(dev, probed_devs);
5aba4f8e
TI		 2102 return -ENOENT;
2103 }
2104
82d9d54a
JK		 2105 /*
2106 * stop probe if another Intel's DSP driver should be activated
2107 */
7fba6aea 2108 if (dmic_detect) {
82d9d54a 2109 err = snd_intel_dsp_driver_probe(pci);
ae035947
PLB		 2110 if (err != SND_INTEL_DSP_DRIVER_ANY && err != SND_INTEL_DSP_DRIVER_LEGACY) {
2111 dev_dbg(&pci->dev, "HDAudio driver not selected, aborting probe\n");
82d9d54a 2112 return -ENODEV;
ae035947 2113 }
7fba6aea
TI		 2114 } else {
2115 dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n");
82d9d54a
JK		 2116 }
2117
60c5772b
TI		 2118 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2119 0, &card);
e58de7ba 2120 if (err < 0) {
4e76a883 2121 dev_err(&pci->dev, "Error creating card!\n");
e58de7ba 2122 return err;
1da177e4
LT		 2123 }
2124
a43ff5ba 2125 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 2126 if (err < 0)
2127 goto out_free;
421a1252 2128 card->private_data = chip;
9a34af4a 2129 hda = container_of(chip, struct hda_intel, chip);
f4c482a4
TI		 2130
2131 pci_set_drvdata(pci, card);
2132
65cbbfa4
ML		 2133#ifdef CONFIG_SND_HDA_I915
2134 /* bind with i915 if needed */
2135 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
e6d0c13e 2136 err = snd_hdac_i915_init(azx_bus(chip));
65cbbfa4 2137 if (err < 0) {
9e88b493
ML		 2138 if (err == -EPROBE_DEFER)
2139 goto out_free;
2140
65cbbfa4
ML		 2141 /* if the controller is bound only with HDMI/DP
2142 * (for HSW and BDW), we need to abort the probe;
2143 * for other chips, still continue probing as other
2144 * codecs can be on the same link.
2145 */
2146 if (HDA_CONTROLLER_IN_GPU(pci)) {
2147 dev_err_probe(card->dev, err,
2148 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2149
2150 goto out_free;
2151 } else {
2152 /* don't bother any longer */
2153 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
2154 }
2155 }
2156
2157 /* HSW/BDW controllers need this power */
2158 if (HDA_CONTROLLER_IN_GPU(pci))
2159 hda->need_i915_power = true;
2160 }
2161#else
2162 if (HDA_CONTROLLER_IN_GPU(pci))
2163 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2164#endif
2165
f4c482a4
TI		 2166 err = register_vga_switcheroo(chip);
2167 if (err < 0) {
2b760d88 2168 dev_err(card->dev, "Error registering vga_switcheroo client\n");
f4c482a4
TI		 2169 goto out_free;
2170 }
2171
2172 if (check_hdmi_disabled(pci)) {
4e76a883
TI		 2173 dev_info(card->dev, "VGA controller is disabled\n");
2174 dev_info(card->dev, "Delaying initialization\n");
f4c482a4
TI		 2175 chip->disabled = true;
2176 }
2177
aad730d0 2178 schedule_probe = !chip->disabled;
1da177e4 2179
4918cdab
TI		 2180#ifdef CONFIG_SND_HDA_PATCH_LOADER
2181 if (patch[dev] && *patch[dev]) {
4e76a883
TI		 2182 dev_info(card->dev, "Applying patch firmware '%s'\n",
2183 patch[dev]);
5cb543db
TI		 2184 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2185 &pci->dev, GFP_KERNEL, card,
2186 azx_firmware_cb);
4918cdab
TI		 2187 if (err < 0)
2188 goto out_free;
aad730d0 2189 schedule_probe = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 2190 }
2191#endif /* CONFIG_SND_HDA_PATCH_LOADER */
2192
aad730d0 2193 if (schedule_probe)
c0f1886d 2194 schedule_delayed_work(&hda->probe_work, 0);
a82d51ed 2195
69458e2c 2196 set_bit(dev, probed_devs);
88d071fc 2197 if (chip->disabled)
9a34af4a 2198 complete_all(&hda->probe_wait);
a82d51ed
TI		 2199 return 0;
2200
2201out_free:
ad6413bc 2202 pci_set_drvdata(pci, NULL);
a82d51ed
TI		 2203 snd_card_free(card);
2204 return err;
2205}
2206
1ba8f9d3
HG		 2207#ifdef CONFIG_PM
2208/* On some boards setting power_save to a non 0 value leads to clicking /
2209 * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2210 * figure out how to avoid these sounds, but that is not always feasible.
2211 * So we keep a list of devices where we disable powersaving as its known
2212 * to causes problems on these devices.
2213 */
6317e5eb 2214static const struct snd_pci_quirk power_save_denylist[] = {
1ba8f9d3 2215 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
8e82a728 2216 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
1ba8f9d3 2217 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
39070a98
HG		 2218 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2219 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
45e5fbc2
HG		 2220 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2221 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
1ba8f9d3 2222 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
38d9c12c 2223 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
5cb6b5fc
HG		 2224 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2225 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
38d9c12c
HG		 2226 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2227 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
5cb6b5fc
HG		 2228 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2229 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
f91f1806
HG		 2230 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2231 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
cae30527
HW		 2232 /* https://bugs.launchpad.net/bugs/1821663 */
2233 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
dd6dd536
HG		 2234 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2235 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
1ba8f9d3
HG		 2236 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2237 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
057a28ef 2238 SND_PCI_QUIRK(0x17aa, 0x316e, "Lenovo ThinkCentre M70q", 0),
721f1e6c
JK		 2239 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2240 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2241 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2242 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
cae30527
HW		 2243 /* https://bugs.launchpad.net/bugs/1821663 */
2244 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
a337c355
TI		 2245 /* KONTRON SinglePC may cause a stall at runtime resume */
2246 SND_PCI_QUIRK(0x1734, 0x1232, "KONTRON SinglePC", 0),
1ba8f9d3
HG		 2247 {}
2248};
2249#endif /* CONFIG_PM */
2250
37a3a98e
TI		 2251static void set_default_power_save(struct azx *chip)
2252{
2253 int val = power_save;
2254
2255#ifdef CONFIG_PM
2256 if (pm_blacklist) {
2257 const struct snd_pci_quirk *q;
2258
6317e5eb 2259 q = snd_pci_quirk_lookup(chip->pci, power_save_denylist);
37a3a98e 2260 if (q && val) {
6317e5eb 2261 dev_info(chip->card->dev, "device %04x:%04x is on the power_save denylist, forcing power_save to 0\n",
37a3a98e
TI		 2262 q->subvendor, q->subdevice);
2263 val = 0;
2264 }
2265 }
2266#endif /* CONFIG_PM */
2267 snd_hda_set_power_save(&chip->bus, val * 1000);
2268}
2269
e62a42ae 2270/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
bf82326f 2271static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
e62a42ae
DR		 2272 [AZX_DRIVER_NVIDIA] = 8,
2273 [AZX_DRIVER_TERA] = 1,
2274};
2275
48c8b0eb 2276static int azx_probe_continue(struct azx *chip)
a82d51ed 2277{
9a34af4a 2278 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
98d8fc6c 2279 struct hdac_bus *bus = azx_bus(chip);
c67e2228 2280 struct pci_dev *pci = chip->pci;
a82d51ed
TI		 2281 int dev = chip->dev_index;
2282 int err;
2283
c0f1886d
TI		 2284 if (chip->disabled || hda->init_failed)
2285 return -EIO;
2286 if (hda->probe_retry)
2287 goto probe_retry;
2288
305a0ade 2289 to_hda_bus(bus)->bus_probing = 1;
a41d1224 2290 hda->probe_continued = 1;
795614dd 2291
fcc88d91
TI		 2292 /* Request display power well for the HDA controller or codec. For
2293 * Haswell/Broadwell, both the display HDA controller and codec need
2294 * this power. For other platforms, like Baytrail/Braswell, only the
2295 * display codec needs the power and it can be released after probe.
2296 */
4f799e73 2297 display_power(chip, true);
99a2008d 2298
5c90680e
TI		 2299 err = azx_first_init(chip);
2300 if (err < 0)
2301 goto out_free;
2302
2dca0bba
JK		 2303#ifdef CONFIG_SND_HDA_INPUT_BEEP
2304 chip->beep_mode = beep_mode[dev];
2305#endif
2306
d045bcef
JK		 2307 chip->ctl_dev_id = ctl_dev_id;
2308
1da177e4 2309 /* create codec instances */
9479e75f
TI		 2310 if (bus->codec_mask) {
2311 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2312 if (err < 0)
2313 goto out_free;
2314 }
96d2bd6e 2315
4ea6fbc8 2316#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab 2317 if (chip->fw) {
a41d1224 2318 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
4918cdab 2319 chip->fw->data);
4ea6fbc8
TI		 2320 if (err < 0)
2321 goto out_free;
e39ae856 2322#ifndef CONFIG_PM
4918cdab
TI		 2323 release_firmware(chip->fw); /* no longer needed */
2324 chip->fw = NULL;
e39ae856 2325#endif
4ea6fbc8
TI		 2326 }
2327#endif
c0f1886d
TI		 2328
2329 probe_retry:
9479e75f 2330 if (bus->codec_mask && !(probe_only[dev] & 1)) {
a1e21c90 2331 err = azx_codec_configure(chip);
c0f1886d
TI		 2332 if (err) {
2333 if ((chip->driver_caps & AZX_DCAPS_RETRY_PROBE) &&
2334 ++hda->probe_retry < 60) {
2335 schedule_delayed_work(&hda->probe_work,
2336 msecs_to_jiffies(1000));
2337 return 0; /* keep things up */
2338 }
2339 dev_err(chip->card->dev, "Cannot probe codecs, giving up\n");
a1e21c90 2340 goto out_free;
c0f1886d 2341 }
a1e21c90 2342 }
1da177e4 2343
a82d51ed 2344 err = snd_card_register(chip->card);
41dda0fd
WF		 2345 if (err < 0)
2346 goto out_free;
1da177e4 2347
37a3a98e
TI		 2348 setup_vga_switcheroo_runtime_pm(chip);
2349
cb53c626 2350 chip->running = 1;
65fcd41d 2351 azx_add_card_list(chip);
07f4f97d 2352
37a3a98e 2353 set_default_power_save(chip);
07f4f97d 2354
3ba21113
RS		 2355 if (azx_has_pm_runtime(chip)) {
2356 pm_runtime_use_autosuspend(&pci->dev);
9fc149c3 2357 pm_runtime_allow(&pci->dev);
30ff5957 2358 pm_runtime_put_autosuspend(&pci->dev);
3ba21113 2359 }
1da177e4 2360
41dda0fd 2361out_free:
2393e755 2362 if (err < 0) {
39173303
TI		 2363 pci_set_drvdata(pci, NULL);
2364 snd_card_free(chip->card);
2393e755
TI		 2365 return err;
2366 }
2367
2368 if (!hda->need_i915_power)
029d92c2 2369 display_power(chip, false);
9a34af4a 2370 complete_all(&hda->probe_wait);
305a0ade 2371 to_hda_bus(bus)->bus_probing = 0;
c0f1886d 2372 hda->probe_retry = 0;
2393e755 2373 return 0;
1da177e4
LT		 2374}
2375
e23e7a14 2376static void azx_remove(struct pci_dev *pci)
1da177e4 2377{
9121947d 2378 struct snd_card *card = pci_get_drvdata(pci);
991f86d7
TI		 2379 struct azx *chip;
2380 struct hda_intel *hda;
2381
2382 if (card) {
0b8c8219 2383 /* cancel the pending probing work */
991f86d7
TI		 2384 chip = card->private_data;
2385 hda = container_of(chip, struct hda_intel, chip);
ab949d51
TI		 2386 /* FIXME: below is an ugly workaround.
2387 * Both device_release_driver() and driver_probe_device()
2388 * take *both* the device's and its parent's lock before
2389 * calling the remove() and probe() callbacks. The codec
2390 * probe takes the locks of both the codec itself and its
2391 * parent, i.e. the PCI controller dev. Meanwhile, when
2392 * the PCI controller is unbound, it takes its lock, too
2393 * ==> ouch, a deadlock!
2394 * As a workaround, we unlock temporarily here the controller
2395 * device during cancel_work_sync() call.
2396 */
2397 device_unlock(&pci->dev);
c0f1886d 2398 cancel_delayed_work_sync(&hda->probe_work);
ab949d51 2399 device_lock(&pci->dev);
b8dfc462 2400
69458e2c 2401 clear_bit(chip->dev_index, probed_devs);
e81478bb 2402 pci_set_drvdata(pci, NULL);
9121947d 2403 snd_card_free(card);
991f86d7 2404 }
1da177e4
LT		 2405}
2406
b2a0bafa
TI		 2407static void azx_shutdown(struct pci_dev *pci)
2408{
2409 struct snd_card *card = pci_get_drvdata(pci);
2410 struct azx *chip;
2411
2412 if (!card)
2413 return;
2414 chip = card->private_data;
2415 if (chip && chip->running)
6f445784 2416 __azx_shutdown_chip(chip, true);
b2a0bafa
TI		 2417}
2418
1da177e4 2419/* PCI IDs */
6f51f6cf 2420static const struct pci_device_id azx_ids[] = {
d2f2fcd2 2421 /* CPT */
e6232c80 2422 { PCI_DEVICE_DATA(INTEL, HDA_CPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) },
cea310e8 2423 /* PBG */
e6232c80 2424 { PCI_DEVICE_DATA(INTEL, HDA_PBG, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) },
d2edeb7c 2425 /* Panther Point */
e6232c80 2426 { PCI_DEVICE_DATA(INTEL, HDA_PPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) },
8bc039a1 2427 /* Lynx Point */
e6232c80 2428 { PCI_DEVICE_DATA(INTEL, HDA_LPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
77f07800 2429 /* 9 Series */
e6232c80 2430 { PCI_DEVICE_DATA(INTEL, HDA_9_SERIES, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
884b088f 2431 /* Wellsburg */
e6232c80
AS		 2432 { PCI_DEVICE_DATA(INTEL, HDA_WBG_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2433 { PCI_DEVICE_DATA(INTEL, HDA_WBG_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
5cf92c8b 2434 /* Lewisburg */
e6232c80
AS		 2435 { PCI_DEVICE_DATA(INTEL, HDA_LBG_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE) },
2436 { PCI_DEVICE_DATA(INTEL, HDA_LBG_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE) },
144dad99 2437 /* Lynx Point-LP */
e6232c80 2438 { PCI_DEVICE_DATA(INTEL, HDA_LPT_LP_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
144dad99 2439 /* Lynx Point-LP */
e6232c80 2440 { PCI_DEVICE_DATA(INTEL, HDA_LPT_LP_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
4eeca499 2441 /* Wildcat Point-LP */
e6232c80
AS		 2442 { PCI_DEVICE_DATA(INTEL, HDA_WPT_LP, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2443 /* Skylake (Sunrise Point) */
2444 { PCI_DEVICE_DATA(INTEL, HDA_SKL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2445 /* Skylake-LP (Sunrise Point-LP) */
2446 { PCI_DEVICE_DATA(INTEL, HDA_SKL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
35639a0e 2447 /* Kabylake */
e6232c80 2448 { PCI_DEVICE_DATA(INTEL, HDA_KBL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
35639a0e 2449 /* Kabylake-LP */
e6232c80 2450 { PCI_DEVICE_DATA(INTEL, HDA_KBL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
6858107e 2451 /* Kabylake-H */
e6232c80 2452 { PCI_DEVICE_DATA(INTEL, HDA_KBL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
e79b0006 2453 /* Coffelake */
e6232c80 2454 { PCI_DEVICE_DATA(INTEL, HDA_CNL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2357f6f0 2455 /* Cannonlake */
e6232c80 2456 { PCI_DEVICE_DATA(INTEL, HDA_CNL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
d4c2ccdb 2457 /* CometLake-LP */
e6232c80 2458 { PCI_DEVICE_DATA(INTEL, HDA_CML_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
d4c2ccdb 2459 /* CometLake-H */
e6232c80
AS		 2460 { PCI_DEVICE_DATA(INTEL, HDA_CML_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2461 { PCI_DEVICE_DATA(INTEL, HDA_RKL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
b73a5854 2462 /* CometLake-S */
e6232c80 2463 { PCI_DEVICE_DATA(INTEL, HDA_CML_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
f84d3a1e 2464 /* CometLake-R */
e6232c80 2465 { PCI_DEVICE_DATA(INTEL, HDA_CML_R, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
491f8331 2466 /* Icelake */
e6232c80 2467 { PCI_DEVICE_DATA(INTEL, HDA_ICL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
d50313a5 2468 /* Icelake-H */
e6232c80 2469 { PCI_DEVICE_DATA(INTEL, HDA_ICL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
4750c212 2470 /* Jasperlake */
e6232c80
AS		 2471 { PCI_DEVICE_DATA(INTEL, HDA_ICL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2472 { PCI_DEVICE_DATA(INTEL, HDA_JSL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
4750c212 2473 /* Tigerlake */
e6232c80 2474 { PCI_DEVICE_DATA(INTEL, HDA_TGL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
d50313a5 2475 /* Tigerlake-H */
e6232c80 2476 { PCI_DEVICE_DATA(INTEL, HDA_TGL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
69b08bdf 2477 /* DG1 */
e6232c80 2478 { PCI_DEVICE_DATA(INTEL, HDA_DG1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
d85ffff5 2479 /* DG2 */
e6232c80
AS		 2480 { PCI_DEVICE_DATA(INTEL, HDA_DG2_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2481 { PCI_DEVICE_DATA(INTEL, HDA_DG2_1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2482 { PCI_DEVICE_DATA(INTEL, HDA_DG2_2, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
d78359b2 2483 /* Alderlake-S */
e6232c80 2484 { PCI_DEVICE_DATA(INTEL, HDA_ADL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
5e941fc0 2485 /* Alderlake-P */
e6232c80
AS		 2486 { PCI_DEVICE_DATA(INTEL, HDA_ADL_P, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2487 { PCI_DEVICE_DATA(INTEL, HDA_ADL_PS, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2488 { PCI_DEVICE_DATA(INTEL, HDA_ADL_PX, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
4ad7935d 2489 /* Alderlake-M */
e6232c80 2490 { PCI_DEVICE_DATA(INTEL, HDA_ADL_M, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
4d5a628d 2491 /* Alderlake-N */
e6232c80 2492 { PCI_DEVICE_DATA(INTEL, HDA_ADL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
f94287b6 2493 /* Elkhart Lake */
e6232c80
AS		 2494 { PCI_DEVICE_DATA(INTEL, HDA_EHL_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2495 { PCI_DEVICE_DATA(INTEL, HDA_EHL_3, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
a531caa5 2496 /* Raptor Lake */
e6232c80
AS		 2497 { PCI_DEVICE_DATA(INTEL, HDA_RPL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2498 { PCI_DEVICE_DATA(INTEL, HDA_RPL_P_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2499 { PCI_DEVICE_DATA(INTEL, HDA_RPL_P_1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2500 { PCI_DEVICE_DATA(INTEL, HDA_RPL_M, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2501 { PCI_DEVICE_DATA(INTEL, HDA_RPL_PX, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2502 { PCI_DEVICE_DATA(INTEL, HDA_MTL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
714b2f02 2503 /* Lunarlake-P */
e6232c80 2504 { PCI_DEVICE_DATA(INTEL, HDA_LNL_P, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
3bef0681
KV		 2505 /* Arrow Lake-S */
2506 { PCI_DEVICE_DATA(INTEL, HDA_ARL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
e6232c80
AS		 2507 /* Apollolake (Broxton-P) */
2508 { PCI_DEVICE_DATA(INTEL, HDA_APL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON) },
44b46d73 2509 /* Gemini-Lake */
e6232c80 2510 { PCI_DEVICE_DATA(INTEL, HDA_GML, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON) },
e926f2c8 2511 /* Haswell */
e6232c80
AS		 2512 { PCI_DEVICE_DATA(INTEL, HDA_HSW_0, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) },
2513 { PCI_DEVICE_DATA(INTEL, HDA_HSW_2, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) },
2514 { PCI_DEVICE_DATA(INTEL, HDA_HSW_3, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) },
862d7618 2515 /* Broadwell */
e6232c80 2516 { PCI_DEVICE_DATA(INTEL, HDA_BDW, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL) },
99df18b3 2517 /* 5 Series/3400 */
e6232c80
AS		 2518 { PCI_DEVICE_DATA(INTEL, HDA_5_3400_SERIES_0, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM) },
2519 { PCI_DEVICE_DATA(INTEL, HDA_5_3400_SERIES_1, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM) },
f748abcc 2520 /* Poulsbo */
e6232c80
AS		 2521 { PCI_DEVICE_DATA(INTEL, HDA_POULSBO, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE |
2522 AZX_DCAPS_POSFIX_LPIB) },
f748abcc 2523 /* Oaktrail */
e6232c80 2524 { PCI_DEVICE_DATA(INTEL, HDA_OAKTRAIL, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE) },
e44007e0 2525 /* BayTrail */
e6232c80 2526 { PCI_DEVICE_DATA(INTEL, HDA_BYT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL) },
f31b2ffc 2527 /* Braswell */
e6232c80 2528 { PCI_DEVICE_DATA(INTEL, HDA_BSW, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL) },
b42b4afb 2529 /* ICH6 */
e6232c80 2530 { PCI_DEVICE_DATA(INTEL, HDA_ICH6, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
b42b4afb 2531 /* ICH7 */
e6232c80 2532 { PCI_DEVICE_DATA(INTEL, HDA_ICH7, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
b42b4afb 2533 /* ESB2 */
e6232c80 2534 { PCI_DEVICE_DATA(INTEL, HDA_ESB2, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
b42b4afb 2535 /* ICH8 */
e6232c80 2536 { PCI_DEVICE_DATA(INTEL, HDA_ICH8, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
b42b4afb 2537 /* ICH9 */
e6232c80 2538 { PCI_DEVICE_DATA(INTEL, HDA_ICH9_0, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
b42b4afb 2539 /* ICH9 */
e6232c80 2540 { PCI_DEVICE_DATA(INTEL, HDA_ICH9_1, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
b42b4afb 2541 /* ICH10 */
e6232c80 2542 { PCI_DEVICE_DATA(INTEL, HDA_ICH10_0, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
b42b4afb 2543 /* ICH10 */
e6232c80 2544 { PCI_DEVICE_DATA(INTEL, HDA_ICH10_1, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
b6864535
TI		 2545 /* Generic Intel */
2546 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2547 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2548 .class_mask = 0xffffff,
103884a3 2549 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
9477c58e 2550 /* ATI SB 450/600/700/800/900 */
e6232c80 2551 { PCI_VDEVICE(ATI, 0x437b),
9477c58e 2552 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
e6232c80 2553 { PCI_VDEVICE(ATI, 0x4383),
9477c58e
TI		 2554 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2555 /* AMD Hudson */
e6232c80 2556 { PCI_VDEVICE(AMD, 0x780d),
9477c58e 2557 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
c02f77d3 2558 /* AMD, X370 & co */
e6232c80 2559 { PCI_VDEVICE(AMD, 0x1457),
c02f77d3 2560 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
de768ce4 2561 /* AMD, X570 & co */
e6232c80 2562 { PCI_VDEVICE(AMD, 0x1487),
de768ce4 2563 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
3deef52c 2564 /* AMD Stoney */
e6232c80 2565 { PCI_VDEVICE(AMD, 0x157a),
3deef52c
KHF		 2566 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2567 AZX_DCAPS_PM_RUNTIME },
9ceace3c 2568 /* AMD Raven */
e6232c80 2569 { PCI_VDEVICE(AMD, 0x15e3),
d2c63b7d 2570 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
87218e9c 2571 /* ATI HDMI */
e6232c80 2572 { PCI_VDEVICE(ATI, 0x0002),
20c7842e
AD		 2573 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2574 AZX_DCAPS_PM_RUNTIME },
e6232c80 2575 { PCI_VDEVICE(ATI, 0x1308),
650474fb 2576 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
e6232c80 2577 { PCI_VDEVICE(ATI, 0x157a),
5022813d 2578 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
e6232c80 2579 { PCI_VDEVICE(ATI, 0x15b3),
d716fb03 2580 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
e6232c80 2581 { PCI_VDEVICE(ATI, 0x793b),
9477c58e 2582 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2583 { PCI_VDEVICE(ATI, 0x7919),
9477c58e 2584 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2585 { PCI_VDEVICE(ATI, 0x960f),
9477c58e 2586 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2587 { PCI_VDEVICE(ATI, 0x970f),
9477c58e 2588 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2589 { PCI_VDEVICE(ATI, 0x9840),
650474fb 2590 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
e6232c80 2591 { PCI_VDEVICE(ATI, 0xaa00),
9477c58e 2592 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2593 { PCI_VDEVICE(ATI, 0xaa08),
9477c58e 2594 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2595 { PCI_VDEVICE(ATI, 0xaa10),
9477c58e 2596 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2597 { PCI_VDEVICE(ATI, 0xaa18),
9477c58e 2598 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2599 { PCI_VDEVICE(ATI, 0xaa20),
9477c58e 2600 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2601 { PCI_VDEVICE(ATI, 0xaa28),
9477c58e 2602 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2603 { PCI_VDEVICE(ATI, 0xaa30),
9477c58e 2604 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2605 { PCI_VDEVICE(ATI, 0xaa38),
9477c58e 2606 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2607 { PCI_VDEVICE(ATI, 0xaa40),
9477c58e 2608 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2609 { PCI_VDEVICE(ATI, 0xaa48),
9477c58e 2610 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2611 { PCI_VDEVICE(ATI, 0xaa50),
bbaa0d66 2612 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2613 { PCI_VDEVICE(ATI, 0xaa58),
bbaa0d66 2614 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2615 { PCI_VDEVICE(ATI, 0xaa60),
bbaa0d66 2616 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2617 { PCI_VDEVICE(ATI, 0xaa68),
bbaa0d66 2618 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2619 { PCI_VDEVICE(ATI, 0xaa80),
bbaa0d66 2620 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2621 { PCI_VDEVICE(ATI, 0xaa88),
bbaa0d66 2622 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2623 { PCI_VDEVICE(ATI, 0xaa90),
bbaa0d66 2624 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2625 { PCI_VDEVICE(ATI, 0xaa98),
bbaa0d66 2626 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
e6232c80 2627 { PCI_VDEVICE(ATI, 0x9902),
37e661ee 2628 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
e6232c80 2629 { PCI_VDEVICE(ATI, 0xaaa0),
37e661ee 2630 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
e6232c80 2631 { PCI_VDEVICE(ATI, 0xaaa8),
37e661ee 2632 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
e6232c80 2633 { PCI_VDEVICE(ATI, 0xaab0),
37e661ee 2634 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
e6232c80 2635 { PCI_VDEVICE(ATI, 0xaac0),
20c7842e
AD		 2636 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2637 AZX_DCAPS_PM_RUNTIME },
e6232c80 2638 { PCI_VDEVICE(ATI, 0xaac8),
20c7842e
AD		 2639 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2640 AZX_DCAPS_PM_RUNTIME },
e6232c80 2641 { PCI_VDEVICE(ATI, 0xaad8),
73b1422b
AD		 2642 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2643 AZX_DCAPS_PM_RUNTIME },
e6232c80 2644 { PCI_VDEVICE(ATI, 0xaae0),
73b1422b
AD		 2645 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2646 AZX_DCAPS_PM_RUNTIME },
e6232c80 2647 { PCI_VDEVICE(ATI, 0xaae8),
73b1422b
AD		 2648 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2649 AZX_DCAPS_PM_RUNTIME },
e6232c80 2650 { PCI_VDEVICE(ATI, 0xaaf0),
73b1422b
AD		 2651 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2652 AZX_DCAPS_PM_RUNTIME },
e6232c80 2653 { PCI_VDEVICE(ATI, 0xaaf8),
73b1422b
AD		 2654 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2655 AZX_DCAPS_PM_RUNTIME },
e6232c80 2656 { PCI_VDEVICE(ATI, 0xab00),
73b1422b
AD		 2657 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2658 AZX_DCAPS_PM_RUNTIME },
e6232c80 2659 { PCI_VDEVICE(ATI, 0xab08),
73b1422b
AD		 2660 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2661 AZX_DCAPS_PM_RUNTIME },
e6232c80 2662 { PCI_VDEVICE(ATI, 0xab10),
73b1422b
AD		 2663 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2664 AZX_DCAPS_PM_RUNTIME },
e6232c80 2665 { PCI_VDEVICE(ATI, 0xab18),
73b1422b
AD		 2666 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2667 AZX_DCAPS_PM_RUNTIME },
e6232c80 2668 { PCI_VDEVICE(ATI, 0xab20),
73b1422b 2669 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
27a7c670 2670 AZX_DCAPS_PM_RUNTIME },
e6232c80 2671 { PCI_VDEVICE(ATI, 0xab28),
27a7c670 2672 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
fdcc4c22 2673 AZX_DCAPS_PM_RUNTIME },
e6232c80 2674 { PCI_VDEVICE(ATI, 0xab30),
fdcc4c22 2675 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
73b1422b 2676 AZX_DCAPS_PM_RUNTIME },
e6232c80 2677 { PCI_VDEVICE(ATI, 0xab38),
73b1422b
AD		 2678 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2679 AZX_DCAPS_PM_RUNTIME },
c51e4310 2680 /* GLENFLY */
2681 { PCI_DEVICE(0x6766, PCI_ANY_ID),
2682 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2683 .class_mask = 0xffffff,
2684 .driver_data = AZX_DRIVER_GFHDMI | AZX_DCAPS_POSFIX_LPIB |
2685 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT },
87218e9c 2686 /* VIA VT8251/VT8237A */
e6232c80 2687 { PCI_VDEVICE(VIA, 0x3288), .driver_data = AZX_DRIVER_VIA },
754fdff8 2688 /* VIA GFX VT7122/VX900 */
e6232c80 2689 { PCI_VDEVICE(VIA, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
754fdff8 2690 /* VIA GFX VT6122/VX11 */
e6232c80 2691 { PCI_VDEVICE(VIA, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c 2692 /* SIS966 */
e6232c80 2693 { PCI_VDEVICE(SI, 0x7502), .driver_data = AZX_DRIVER_SIS },
87218e9c 2694 /* ULI M5461 */
e6232c80 2695 { PCI_VDEVICE(AL, 0x5461), .driver_data = AZX_DRIVER_ULI },
87218e9c 2696 /* NVIDIA MCP */
0c2fd1bf
TI		 2697 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2698 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2699 .class_mask = 0xffffff,
9477c58e 2700 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 2701 /* Teradici */
9477c58e
TI		 2702 { PCI_DEVICE(0x6549, 0x1200),
2703 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 2704 { PCI_DEVICE(0x6549, 0x2200),
2705 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 2706 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf 2707 /* CTHDA chips */
e6232c80 2708 { PCI_VDEVICE(CREATIVE, 0x0010),
f2a8ecaf 2709 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
e6232c80 2710 { PCI_VDEVICE(CREATIVE, 0x0012),
f2a8ecaf 2711 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
8eeaa2f9 2712#if !IS_ENABLED(CONFIG_SND_CTXFI)
313f6e2d
TI		 2713 /* the following entry conflicts with snd-ctxfi driver,
2714 * as ctxfi driver mutates from HD-audio to native mode with
2715 * a special command sequence.
2716 */
4e01f54b
TI		 2717 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2718 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2719 .class_mask = 0xffffff,
9477c58e 2720 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
ef85f299 2721 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 2722#else
2723 /* this entry seems still valid -- i.e. without emu20kx chip */
e6232c80 2724 { PCI_VDEVICE(CREATIVE, 0x0009),
9477c58e 2725 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
ef85f299 2726 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 2727#endif
c563f473 2728 /* CM8888 */
e6232c80 2729 { PCI_VDEVICE(CMEDIA, 0x5011),
c563f473 2730 .driver_data = AZX_DRIVER_CMEDIA |
37e661ee 2731 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
e35d4b11 2732 /* Vortex86MX */
e6232c80 2733 { PCI_VDEVICE(RDC, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5 2734 /* VMware HDAudio */
e6232c80 2735 { PCI_VDEVICE(VMWARE, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 2736 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 2737 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2738 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2739 .class_mask = 0xffffff,
9477c58e 2740 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 2741 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2742 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2743 .class_mask = 0xffffff,
9477c58e 2744 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
b6fcab14 2745 /* Zhaoxin */
e6232c80 2746 { PCI_VDEVICE(ZHAOXIN, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN },
28bd137a 2747 /* Loongson HDAudio*/
e6232c80 2748 { PCI_VDEVICE(LOONGSON, PCI_DEVICE_ID_LOONGSON_HDA),
28bd137a 2749 .driver_data = AZX_DRIVER_LOONGSON },
e6232c80 2750 { PCI_VDEVICE(LOONGSON, PCI_DEVICE_ID_LOONGSON_HDMI),
28bd137a 2751 .driver_data = AZX_DRIVER_LOONGSON },
1da177e4
LT		 2752 { 0, }
2753};
2754MODULE_DEVICE_TABLE(pci, azx_ids);
2755
2756/* pci_driver definition */
e9f66d9b 2757static struct pci_driver azx_driver = {
3733e424 2758 .name = KBUILD_MODNAME,
1da177e4
LT		 2759 .id_table = azx_ids,
2760 .probe = azx_probe,
e23e7a14 2761 .remove = azx_remove,
b2a0bafa 2762 .shutdown = azx_shutdown,
68cb2b55
TI		 2763 .driver = {
2764 .pm = AZX_PM_OPS,
2765 },
1da177e4
LT		 2766};
2767
e9f66d9b 2768module_pci_driver(azx_driver);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git