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Merge tag 'drm/tegra/for-5.7-fixes' of git://anongit.freedesktop.org/tegra/linux...
[thirdparty/linux.git] / sound / pci / hda / hda_intel.c
CommitLineData
1a59d1b8 1// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4
LT		 2/*
3 *
d01ce99f
TI		 4 * hda_intel.c - Implementation of primary alsa driver code base
5 * for Intel HD Audio.
1da177e4
LT		 6 *
7 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 *
9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
10 * PeiSen Hou <pshou@realtek.com.tw>
11 *
1da177e4
LT		 12 * CONTACTS:
13 *
14 * Matt Jared matt.jared@intel.com
15 * Andy Kopp andy.kopp@intel.com
16 * Dan Kogan dan.d.kogan@intel.com
17 *
18 * CHANGES:
19 *
20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
1da177e4
LT		 21 */
22
1da177e4
LT		 23#include <linux/delay.h>
24#include <linux/interrupt.h>
362775e2 25#include <linux/kernel.h>
1da177e4 26#include <linux/module.h>
24982c5f 27#include <linux/dma-mapping.h>
1da177e4
LT		 28#include <linux/moduleparam.h>
29#include <linux/init.h>
30#include <linux/slab.h>
31#include <linux/pci.h>
62932df8 32#include <linux/mutex.h>
27fe48d9 33#include <linux/io.h>
b8dfc462 34#include <linux/pm_runtime.h>
5d890f59
PLB		 35#include <linux/clocksource.h>
36#include <linux/time.h>
f4c482a4 37#include <linux/completion.h>
586bc4aa 38#include <linux/acpi.h>
5d890f59 39
27fe48d9
TI		 40#ifdef CONFIG_X86
41/* for snoop control */
42#include <asm/pgtable.h>
7f80f513 43#include <asm/set_memory.h>
50279d9b 44#include <asm/cpufeature.h>
27fe48d9 45#endif
1da177e4
LT		 46#include <sound/core.h>
47#include <sound/initval.h>
98d8fc6c
ML		 48#include <sound/hdaudio.h>
49#include <sound/hda_i915.h>
82d9d54a 50#include <sound/intel-dsp-config.h>
9121947d 51#include <linux/vgaarb.h>
a82d51ed 52#include <linux/vga_switcheroo.h>
4918cdab 53#include <linux/firmware.h>
be57bfff 54#include <sound/hda_codec.h>
05e84878 55#include "hda_controller.h"
347de1f8 56#include "hda_intel.h"
1da177e4 57
785d8c4b
LY		 58#define CREATE_TRACE_POINTS
59#include "hda_intel_trace.h"
60
b6050ef6
TI		 61/* position fix mode */
62enum {
63 POS_FIX_AUTO,
64 POS_FIX_LPIB,
65 POS_FIX_POSBUF,
66 POS_FIX_VIACOMBO,
67 POS_FIX_COMBO,
f87e7f25 68 POS_FIX_SKL,
c02f77d3 69 POS_FIX_FIFO,
b6050ef6
TI		 70};
71
9a34af4a
TI		 72/* Defines for ATI HD Audio support in SB450 south bridge */
73#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
74#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
75
76/* Defines for Nvidia HDA support */
77#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
78#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
79#define NVIDIA_HDA_ISTRM_COH 0x4d
80#define NVIDIA_HDA_OSTRM_COH 0x4c
81#define NVIDIA_HDA_ENABLE_COHBIT 0x01
82
83/* Defines for Intel SCH HDA snoop control */
6639484d
LY		 84#define INTEL_HDA_CGCTL 0x48
85#define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
9a34af4a
TI		 86#define INTEL_SCH_HDA_DEVC 0x78
87#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
88
9a34af4a
TI		 89/* Define VIA HD Audio Device ID*/
90#define VIA_HDAC_DEVICE_ID 0x3288
91
33124929
TI		 92/* max number of SDs */
93/* ICH, ATI and VIA have 4 playback and 4 capture */
94#define ICH6_NUM_CAPTURE 4
95#define ICH6_NUM_PLAYBACK 4
96
97/* ULI has 6 playback and 5 capture */
98#define ULI_NUM_CAPTURE 5
99#define ULI_NUM_PLAYBACK 6
100
101/* ATI HDMI may have up to 8 playbacks and 0 capture */
102#define ATIHDMI_NUM_CAPTURE 0
103#define ATIHDMI_NUM_PLAYBACK 8
104
105/* TERA has 4 playback and 3 capture */
106#define TERA_NUM_CAPTURE 3
107#define TERA_NUM_PLAYBACK 4
108
1da177e4 109
5aba4f8e
TI		 110static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
111static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 112static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 113static char *model[SNDRV_CARDS];
1dac6695 114static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 115static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 116static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 117static int probe_only[SNDRV_CARDS];
26a6cb6c 118static int jackpoll_ms[SNDRV_CARDS];
41438f13 119static int single_cmd = -1;
71623855 120static int enable_msi = -1;
4ea6fbc8
TI		 121#ifdef CONFIG_SND_HDA_PATCH_LOADER
122static char *patch[SNDRV_CARDS];
123#endif
2dca0bba 124#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 125static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 126 CONFIG_SND_HDA_INPUT_BEEP_MODE};
127#endif
7fba6aea 128static bool dmic_detect = 1;
1da177e4 129
5aba4f8e 130module_param_array(index, int, NULL, 0444);
1da177e4 131MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 132module_param_array(id, charp, NULL, 0444);
1da177e4 133MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 134module_param_array(enable, bool, NULL, 0444);
135MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
136module_param_array(model, charp, NULL, 0444);
1da177e4 137MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 138module_param_array(position_fix, int, NULL, 0444);
4cb36310 139MODULE_PARM_DESC(position_fix, "DMA pointer read method."
c02f77d3 140 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO).");
555e219f
TI		 141module_param_array(bdl_pos_adj, int, NULL, 0644);
142MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 143module_param_array(probe_mask, int, NULL, 0444);
606ad75f 144MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 145module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 146MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 147module_param_array(jackpoll_ms, int, NULL, 0444);
148MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
41438f13 149module_param(single_cmd, bint, 0444);
d01ce99f
TI		 150MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
151 "(for debugging only).");
ac9ef6cf 152module_param(enable_msi, bint, 0444);
134a11f0 153MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 154#ifdef CONFIG_SND_HDA_PATCH_LOADER
155module_param_array(patch, charp, NULL, 0444);
156MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
157#endif
2dca0bba 158#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 159module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 160MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 161 "(0=off, 1=on) (default=1).");
2dca0bba 162#endif
7fba6aea
TI		 163module_param(dmic_detect, bool, 0444);
164MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) "
165 "(0=off, 1=on) (default=1); "
166 "deprecated, use snd-intel-dspcfg.dsp_driver option instead");
606ad75f 167
83012a7c 168#ifdef CONFIG_PM
65fcd41d 169static int param_set_xint(const char *val, const struct kernel_param *kp);
9c27847d 170static const struct kernel_param_ops param_ops_xint = {
65fcd41d
TI		 171 .set = param_set_xint,
172 .get = param_get_int,
173};
174#define param_check_xint param_check_int
175
fee2fba3 176static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
65fcd41d 177module_param(power_save, xint, 0644);
fee2fba3
TI		 178MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
179 "(in second, 0 = disable).");
1da177e4 180
40088dc4
TI		 181static bool pm_blacklist = true;
182module_param(pm_blacklist, bool, 0644);
183MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist");
184
dee1b66c
TI		 185/* reset the HD-audio controller in power save mode.
186 * this may give more power-saving, but will take longer time to
187 * wake up.
188 */
8fc24426
TI		 189static bool power_save_controller = 1;
190module_param(power_save_controller, bool, 0644);
dee1b66c 191MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
e62a42ae 192#else
bb573928 193#define power_save 0
83012a7c 194#endif /* CONFIG_PM */
dee1b66c 195
7bfe059e
TI		 196static int align_buffer_size = -1;
197module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 198MODULE_PARM_DESC(align_buffer_size,
199 "Force buffer and period sizes to be multiple of 128 bytes.");
200
27fe48d9 201#ifdef CONFIG_X86
7c732015
TI		 202static int hda_snoop = -1;
203module_param_named(snoop, hda_snoop, bint, 0444);
27fe48d9 204MODULE_PARM_DESC(snoop, "Enable/disable snooping");
27fe48d9
TI		 205#else
206#define hda_snoop true
27fe48d9
TI		 207#endif
208
209
1da177e4
LT		 210MODULE_LICENSE("GPL");
211MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
212 "{Intel, ICH6M},"
2f1b3818 213 "{Intel, ICH7},"
f5d40b30 214 "{Intel, ESB2},"
d2981393 215 "{Intel, ICH8},"
f9cc8a8b 216 "{Intel, ICH9},"
c34f5a04 217 "{Intel, ICH10},"
b29c2360 218 "{Intel, PCH},"
d2f2fcd2 219 "{Intel, CPT},"
d2edeb7c 220 "{Intel, PPT},"
8bc039a1 221 "{Intel, LPT},"
144dad99 222 "{Intel, LPT_LP},"
4eeca499 223 "{Intel, WPT_LP},"
c8b00fd2 224 "{Intel, SPT},"
b4565913 225 "{Intel, SPT_LP},"
e926f2c8 226 "{Intel, HPT},"
cea310e8 227 "{Intel, PBG},"
4979bca9 228 "{Intel, SCH},"
fc20a562 229 "{ATI, SB450},"
89be83f8 230 "{ATI, SB600},"
778b6e1b 231 "{ATI, RS600},"
5b15c95f 232 "{ATI, RS690},"
e6db1119
WL		 233 "{ATI, RS780},"
234 "{ATI, R600},"
2797f724
HRK		 235 "{ATI, RV630},"
236 "{ATI, RV610},"
27da1834
WL		 237 "{ATI, RV670},"
238 "{ATI, RV635},"
239 "{ATI, RV620},"
240 "{ATI, RV770},"
fc20a562 241 "{VIA, VT8251},"
47672310 242 "{VIA, VT8237A},"
07e4ca50
TI		 243 "{SiS, SIS966},"
244 "{ULI, M5461}}");
1da177e4
LT		 245MODULE_DESCRIPTION("Intel HDA driver");
246
a82d51ed 247#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
f8f1becf 248#if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
a82d51ed
TI		 249#define SUPPORT_VGA_SWITCHEROO
250#endif
251#endif
252
253
1da177e4 254/*
1da177e4 255 */
1da177e4 256
07e4ca50
TI		 257/* driver types */
258enum {
259 AZX_DRIVER_ICH,
32679f95 260 AZX_DRIVER_PCH,
4979bca9 261 AZX_DRIVER_SCH,
a4b4793f 262 AZX_DRIVER_SKL,
fab1285a 263 AZX_DRIVER_HDMI,
07e4ca50 264 AZX_DRIVER_ATI,
778b6e1b 265 AZX_DRIVER_ATIHDMI,
1815b34a 266 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 267 AZX_DRIVER_VIA,
268 AZX_DRIVER_SIS,
269 AZX_DRIVER_ULI,
da3fca21 270 AZX_DRIVER_NVIDIA,
f269002e 271 AZX_DRIVER_TERA,
14d34f16 272 AZX_DRIVER_CTX,
5ae763b1 273 AZX_DRIVER_CTHDA,
c563f473 274 AZX_DRIVER_CMEDIA,
b6fcab14 275 AZX_DRIVER_ZHAOXIN,
c4da29ca 276 AZX_DRIVER_GENERIC,
2f5983f2 277 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 278};
279
37e661ee
TI		 280#define azx_get_snoop_type(chip) \
281 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
282#define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
283
b42b4afb
TI		 284/* quirks for old Intel chipsets */
285#define AZX_DCAPS_INTEL_ICH \
c366b3db
TI		 286 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE |\
287 AZX_DCAPS_SYNC_WRITE)
b42b4afb 288
2ea3c6a2 289/* quirks for Intel PCH */
6603249d 290#define AZX_DCAPS_INTEL_PCH_BASE \
103884a3 291 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
c366b3db 292 AZX_DCAPS_SNOOP_TYPE(SCH) | AZX_DCAPS_SYNC_WRITE)
d7dab4db 293
dba9b7b6 294/* PCH up to IVB; no runtime PM; bind with i915 gfx */
6603249d 295#define AZX_DCAPS_INTEL_PCH_NOPM \
dba9b7b6 296 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
6603249d 297
55913110 298/* PCH for HSW/BDW; with runtime PM */
dba9b7b6 299/* no i915 binding for this as HSW/BDW has another controller for HDMI */
d7dab4db 300#define AZX_DCAPS_INTEL_PCH \
6603249d 301 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
9477c58e 302
6603249d 303/* HSW HDMI */
33499a15 304#define AZX_DCAPS_INTEL_HASWELL \
103884a3 305 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
dba9b7b6 306 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
c366b3db 307 AZX_DCAPS_SNOOP_TYPE(SCH) | AZX_DCAPS_SYNC_WRITE)
33499a15 308
54a0405d
LY		 309/* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
310#define AZX_DCAPS_INTEL_BROADWELL \
103884a3 311 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
dba9b7b6 312 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
c366b3db 313 AZX_DCAPS_SNOOP_TYPE(SCH) | AZX_DCAPS_SYNC_WRITE)
54a0405d 314
40cc2392 315#define AZX_DCAPS_INTEL_BAYTRAIL \
e454ff8e 316 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
40cc2392 317
2d846c74 318#define AZX_DCAPS_INTEL_BRASWELL \
dba9b7b6 319 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
e454ff8e 320 AZX_DCAPS_I915_COMPONENT)
2d846c74 321
d6795827 322#define AZX_DCAPS_INTEL_SKYLAKE \
dba9b7b6 323 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
2756d914 324 AZX_DCAPS_SYNC_WRITE |\
e454ff8e 325 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
d6795827 326
2756d914 327#define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE
c87693da 328
9477c58e
TI		 329/* quirks for ATI SB / AMD Hudson */
330#define AZX_DCAPS_PRESET_ATI_SB \
37e661ee
TI		 331 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
332 AZX_DCAPS_SNOOP_TYPE(ATI))
9477c58e
TI		 333
334/* quirks for ATI/AMD HDMI */
335#define AZX_DCAPS_PRESET_ATI_HDMI \
db79afa1
BH		 336 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
337 AZX_DCAPS_NO_MSI64)
9477c58e 338
37e661ee
TI		 339/* quirks for ATI HDMI with snoop off */
340#define AZX_DCAPS_PRESET_ATI_HDMI_NS \
341 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
342
c02f77d3
TI		 343/* quirks for AMD SB */
344#define AZX_DCAPS_PRESET_AMD_SB \
345 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_AMD_WORKAROUND |\
346 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME)
347
9477c58e
TI		 348/* quirks for Nvidia */
349#define AZX_DCAPS_PRESET_NVIDIA \
3ab7511e 350 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
37e661ee 351 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
9477c58e 352
5ae763b1 353#define AZX_DCAPS_PRESET_CTHDA \
37e661ee 354 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
cadd16ea 355 AZX_DCAPS_NO_64BIT |\
37e661ee 356 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
5ae763b1 357
a82d51ed 358/*
2b760d88 359 * vga_switcheroo support
a82d51ed
TI		 360 */
361#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db 362#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
dd23e1d5 363#define needs_eld_notify_link(chip) ((chip)->bus.keep_power)
5cb543db
TI		 364#else
365#define use_vga_switcheroo(chip) 0
37a3a98e 366#define needs_eld_notify_link(chip) false
5cb543db
TI		 367#endif
368
03b135ce
LY		 369#define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
370 ((pci)->device == 0x0c0c) || \
371 ((pci)->device == 0x0d0c) || \
372 ((pci)->device == 0x160c))
373
7e31a015 374#define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
7c23b7c1 375
bf82326f 376static const char * const driver_short_names[] = {
07e4ca50 377 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 378 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 379 [AZX_DRIVER_SCH] = "HDA Intel MID",
a4b4793f 380 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
fab1285a 381 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
07e4ca50 382 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 383 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 384 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 385 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
386 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 387 [AZX_DRIVER_ULI] = "HDA ULI M5461",
388 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 389 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 390 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 391 [AZX_DRIVER_CTHDA] = "HDA Creative",
c563f473 392 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
b6fcab14 393 [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin",
c4da29ca 394 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 395};
396
68e7fffc 397static int azx_acquire_irq(struct azx *chip, int do_disconnect);
37a3a98e 398static void set_default_power_save(struct azx *chip);
111d3af5 399
cb53c626
TI		 400/*
401 * initialize the PCI registers
402 */
403/* update bits in a PCI register byte */
404static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
405 unsigned char mask, unsigned char val)
406{
407 unsigned char data;
408
409 pci_read_config_byte(pci, reg, &data);
410 data &= ~mask;
411 data |= (val & mask);
412 pci_write_config_byte(pci, reg, data);
413}
414
415static void azx_init_pci(struct azx *chip)
416{
37e661ee
TI		 417 int snoop_type = azx_get_snoop_type(chip);
418
cb53c626
TI		 419 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
420 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
421 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 422 * codecs.
423 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 424 */
46f2cc80 425 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
4e76a883 426 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
fb1d8ac2 427 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
9477c58e 428 }
cb53c626 429
9477c58e
TI		 430 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
431 * we need to enable snoop.
432 */
37e661ee 433 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
4e76a883
TI		 434 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
435 azx_snoop(chip));
cb53c626 436 update_pci_byte(chip->pci,
27fe48d9
TI		 437 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
438 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 439 }
440
441 /* For NVIDIA HDA, enable snoop */
37e661ee 442 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
4e76a883
TI		 443 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
444 azx_snoop(chip));
cb53c626
TI		 445 update_pci_byte(chip->pci,
446 NVIDIA_HDA_TRANSREG_ADDR,
447 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 448 update_pci_byte(chip->pci,
449 NVIDIA_HDA_ISTRM_COH,
450 0x01, NVIDIA_HDA_ENABLE_COHBIT);
451 update_pci_byte(chip->pci,
452 NVIDIA_HDA_OSTRM_COH,
453 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 454 }
455
456 /* Enable SCH/PCH snoop if needed */
37e661ee 457 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
27fe48d9 458 unsigned short snoop;
90a5ad52 459 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 460 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
461 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
462 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
463 if (!azx_snoop(chip))
464 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
465 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 466 pci_read_config_word(chip->pci,
467 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 468 }
4e76a883
TI		 469 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
470 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
471 "Disabled" : "Enabled");
da3fca21 472 }
1da177e4
LT		 473}
474
7c23b7c1
LH		 475/*
476 * In BXT-P A0, HD-Audio DMA requests is later than expected,
477 * and makes an audio stream sensitive to system latencies when
478 * 24/32 bits are playing.
479 * Adjusting threshold of DMA fifo to force the DMA request
480 * sooner to improve latency tolerance at the expense of power.
481 */
482static void bxt_reduce_dma_latency(struct azx *chip)
483{
484 u32 val;
485
70eafad8 486 val = azx_readl(chip, VS_EM4L);
7c23b7c1 487 val &= (0x3 << 20);
70eafad8 488 azx_writel(chip, VS_EM4L, val);
7c23b7c1
LH		 489}
490
1f9d3d98
LY		 491/*
492 * ML_LCAP bits:
493 * bit 0: 6 MHz Supported
494 * bit 1: 12 MHz Supported
495 * bit 2: 24 MHz Supported
496 * bit 3: 48 MHz Supported
497 * bit 4: 96 MHz Supported
498 * bit 5: 192 MHz Supported
499 */
500static int intel_get_lctl_scf(struct azx *chip)
501{
502 struct hdac_bus *bus = azx_bus(chip);
bf82326f 503 static const int preferred_bits[] = { 2, 3, 1, 4, 5 };
1f9d3d98
LY		 504 u32 val, t;
505 int i;
506
507 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
508
509 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
510 t = preferred_bits[i];
511 if (val & (1 << t))
512 return t;
513 }
514
515 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
516 return 0;
517}
518
519static int intel_ml_lctl_set_power(struct azx *chip, int state)
520{
521 struct hdac_bus *bus = azx_bus(chip);
522 u32 val;
523 int timeout;
524
525 /*
526 * the codecs are sharing the first link setting by default
527 * If other links are enabled for stream, they need similar fix
528 */
529 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
530 val &= ~AZX_MLCTL_SPA;
531 val |= state << AZX_MLCTL_SPA_SHIFT;
532 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
533 /* wait for CPA */
534 timeout = 50;
535 while (timeout) {
536 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
537 AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
538 return 0;
539 timeout--;
540 udelay(10);
541 }
542
543 return -1;
544}
545
546static void intel_init_lctl(struct azx *chip)
547{
548 struct hdac_bus *bus = azx_bus(chip);
549 u32 val;
550 int ret;
551
552 /* 0. check lctl register value is correct or not */
553 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
554 /* if SCF is already set, let's use it */
555 if ((val & ML_LCTL_SCF_MASK) != 0)
556 return;
557
558 /*
559 * Before operating on SPA, CPA must match SPA.
560 * Any deviation may result in undefined behavior.
561 */
562 if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
563 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
564 return;
565
566 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
567 ret = intel_ml_lctl_set_power(chip, 0);
568 udelay(100);
569 if (ret)
570 goto set_spa;
571
572 /* 2. update SCF to select a properly audio clock*/
573 val &= ~ML_LCTL_SCF_MASK;
574 val |= intel_get_lctl_scf(chip);
575 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
576
577set_spa:
578 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
579 intel_ml_lctl_set_power(chip, 1);
580 udelay(100);
581}
582
0a673521
LH		 583static void hda_intel_init_chip(struct azx *chip, bool full_reset)
584{
98d8fc6c 585 struct hdac_bus *bus = azx_bus(chip);
7c23b7c1 586 struct pci_dev *pci = chip->pci;
6639484d 587 u32 val;
0a673521 588
e454ff8e 589 snd_hdac_set_codec_wakeup(bus, true);
a4b4793f 590 if (chip->driver_type == AZX_DRIVER_SKL) {
6639484d
LY		 591 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
592 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
593 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
594 }
0a673521 595 azx_init_chip(chip, full_reset);
a4b4793f 596 if (chip->driver_type == AZX_DRIVER_SKL) {
6639484d
LY		 597 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
598 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
599 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
600 }
e454ff8e
TI		 601
602 snd_hdac_set_codec_wakeup(bus, false);
7c23b7c1
LH		 603
604 /* reduce dma latency to avoid noise */
7e31a015 605 if (IS_BXT(pci))
7c23b7c1 606 bxt_reduce_dma_latency(chip);
1f9d3d98
LY		 607
608 if (bus->mlcap != NULL)
609 intel_init_lctl(chip);
0a673521
LH		 610}
611
b6050ef6
TI		 612/* calculate runtime delay from LPIB */
613static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
614 unsigned int pos)
615{
7833c3f8 616 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6
TI		 617 int stream = substream->stream;
618 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
619 int delay;
620
621 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
622 delay = pos - lpib_pos;
623 else
624 delay = lpib_pos - pos;
625 if (delay < 0) {
7833c3f8 626 if (delay >= azx_dev->core.delay_negative_threshold)
b6050ef6
TI		 627 delay = 0;
628 else
7833c3f8 629 delay += azx_dev->core.bufsize;
b6050ef6
TI		 630 }
631
7833c3f8 632 if (delay >= azx_dev->core.period_bytes) {
b6050ef6
TI		 633 dev_info(chip->card->dev,
634 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
7833c3f8 635 delay, azx_dev->core.period_bytes);
b6050ef6
TI		 636 delay = 0;
637 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
638 chip->get_delay[stream] = NULL;
639 }
640
641 return bytes_to_frames(substream->runtime, delay);
642}
643
9ad593f6
TI		 644static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
645
7ca954a8
DR		 646/* called from IRQ */
647static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
648{
9a34af4a 649 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
7ca954a8
DR		 650 int ok;
651
652 ok = azx_position_ok(chip, azx_dev);
653 if (ok == 1) {
654 azx_dev->irq_pending = 0;
655 return ok;
2f35c630 656 } else if (ok == 0) {
7ca954a8
DR		 657 /* bogus IRQ, process it later */
658 azx_dev->irq_pending = 1;
2f35c630 659 schedule_work(&hda->irq_pending_work);
7ca954a8
DR		 660 }
661 return 0;
662}
663
029d92c2
TI		 664#define display_power(chip, enable) \
665 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
17eccb27 666
9ad593f6
TI		 667/*
668 * Check whether the current DMA position is acceptable for updating
669 * periods. Returns non-zero if it's OK.
670 *
671 * Many HD-audio controllers appear pretty inaccurate about
672 * the update-IRQ timing. The IRQ is issued before actually the
673 * data is processed. So, we need to process it afterwords in a
674 * workqueue.
675 */
676static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
677{
7833c3f8 678 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6 679 int stream = substream->stream;
e5463720 680 u32 wallclk;
9ad593f6
TI		 681 unsigned int pos;
682
7833c3f8
TI		 683 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
684 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
fa00e046 685 return -1; /* bogus (too early) interrupt */
fa00e046 686
b6050ef6
TI		 687 if (chip->get_position[stream])
688 pos = chip->get_position[stream](chip, azx_dev);
689 else { /* use the position buffer as default */
690 pos = azx_get_pos_posbuf(chip, azx_dev);
691 if (!pos || pos == (u32)-1) {
692 dev_info(chip->card->dev,
693 "Invalid position buffer, using LPIB read method instead.\n");
694 chip->get_position[stream] = azx_get_pos_lpib;
ccc98865
TI		 695 if (chip->get_position[0] == azx_get_pos_lpib &&
696 chip->get_position[1] == azx_get_pos_lpib)
697 azx_bus(chip)->use_posbuf = false;
b6050ef6
TI		 698 pos = azx_get_pos_lpib(chip, azx_dev);
699 chip->get_delay[stream] = NULL;
700 } else {
701 chip->get_position[stream] = azx_get_pos_posbuf;
702 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
703 chip->get_delay[stream] = azx_get_delay_from_lpib;
704 }
705 }
706
7833c3f8 707 if (pos >= azx_dev->core.bufsize)
b6050ef6 708 pos = 0;
9ad593f6 709
7833c3f8 710 if (WARN_ONCE(!azx_dev->core.period_bytes,
d6d8bf54 711 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 712 return -1; /* this shouldn't happen! */
7833c3f8
TI		 713 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
714 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
f48f606d 715 /* NG - it's below the first next period boundary */
4f0189be 716 return chip->bdl_pos_adj ? 0 : -1;
7833c3f8 717 azx_dev->core.start_wallclk += wallclk;
9ad593f6
TI		 718 return 1; /* OK, it's fine */
719}
720
721/*
722 * The work for pending PCM period updates.
723 */
724static void azx_irq_pending_work(struct work_struct *work)
725{
9a34af4a
TI		 726 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
727 struct azx *chip = &hda->chip;
7833c3f8
TI		 728 struct hdac_bus *bus = azx_bus(chip);
729 struct hdac_stream *s;
730 int pending, ok;
9ad593f6 731
9a34af4a 732 if (!hda->irq_pending_warned) {
4e76a883
TI		 733 dev_info(chip->card->dev,
734 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
735 chip->card->number);
9a34af4a 736 hda->irq_pending_warned = 1;
a6a950a8
TI		 737 }
738
9ad593f6
TI		 739 for (;;) {
740 pending = 0;
a41d1224 741 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 742 list_for_each_entry(s, &bus->stream_list, list) {
743 struct azx_dev *azx_dev = stream_to_azx_dev(s);
9ad593f6 744 if (!azx_dev->irq_pending ||
7833c3f8
TI		 745 !s->substream ||
746 !s->running)
9ad593f6 747 continue;
e5463720
JK		 748 ok = azx_position_ok(chip, azx_dev);
749 if (ok > 0) {
9ad593f6 750 azx_dev->irq_pending = 0;
a41d1224 751 spin_unlock(&bus->reg_lock);
7833c3f8 752 snd_pcm_period_elapsed(s->substream);
a41d1224 753 spin_lock(&bus->reg_lock);
e5463720
JK		 754 } else if (ok < 0) {
755 pending = 0; /* too early */
9ad593f6
TI		 756 } else
757 pending++;
758 }
a41d1224 759 spin_unlock_irq(&bus->reg_lock);
9ad593f6
TI		 760 if (!pending)
761 return;
08af495f 762 msleep(1);
9ad593f6
TI		 763 }
764}
765
766/* clear irq_pending flags and assure no on-going workq */
767static void azx_clear_irq_pending(struct azx *chip)
768{
7833c3f8
TI		 769 struct hdac_bus *bus = azx_bus(chip);
770 struct hdac_stream *s;
9ad593f6 771
a41d1224 772 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 773 list_for_each_entry(s, &bus->stream_list, list) {
774 struct azx_dev *azx_dev = stream_to_azx_dev(s);
775 azx_dev->irq_pending = 0;
776 }
a41d1224 777 spin_unlock_irq(&bus->reg_lock);
1da177e4
LT		 778}
779
68e7fffc
TI		 780static int azx_acquire_irq(struct azx *chip, int do_disconnect)
781{
a41d1224
TI		 782 struct hdac_bus *bus = azx_bus(chip);
783
437a5a46
TI		 784 if (request_irq(chip->pci->irq, azx_interrupt,
785 chip->msi ? 0 : IRQF_SHARED,
de65360b 786 chip->card->irq_descr, chip)) {
4e76a883
TI		 787 dev_err(chip->card->dev,
788 "unable to grab IRQ %d, disabling device\n",
789 chip->pci->irq);
68e7fffc
TI		 790 if (do_disconnect)
791 snd_card_disconnect(chip->card);
792 return -1;
793 }
a41d1224 794 bus->irq = chip->pci->irq;
f36da940 795 chip->card->sync_irq = bus->irq;
69e13418 796 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 797 return 0;
798}
799
b6050ef6
TI		 800/* get the current DMA position with correction on VIA chips */
801static unsigned int azx_via_get_position(struct azx *chip,
802 struct azx_dev *azx_dev)
803{
804 unsigned int link_pos, mini_pos, bound_pos;
805 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
806 unsigned int fifo_size;
807
1604eeee 808 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
7833c3f8 809 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
b6050ef6
TI		 810 /* Playback, no problem using link position */
811 return link_pos;
812 }
813
814 /* Capture */
815 /* For new chipset,
816 * use mod to get the DMA position just like old chipset
817 */
7833c3f8
TI		 818 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
819 mod_dma_pos %= azx_dev->core.period_bytes;
b6050ef6 820
7da20788 821 fifo_size = azx_stream(azx_dev)->fifo_size - 1;
b6050ef6
TI		 822
823 if (azx_dev->insufficient) {
824 /* Link position never gather than FIFO size */
825 if (link_pos <= fifo_size)
826 return 0;
827
828 azx_dev->insufficient = 0;
829 }
830
831 if (link_pos <= fifo_size)
7833c3f8 832 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
b6050ef6
TI		 833 else
834 mini_pos = link_pos - fifo_size;
835
836 /* Find nearest previous boudary */
7833c3f8
TI		 837 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
838 mod_link_pos = link_pos % azx_dev->core.period_bytes;
b6050ef6
TI		 839 if (mod_link_pos >= fifo_size)
840 bound_pos = link_pos - mod_link_pos;
841 else if (mod_dma_pos >= mod_mini_pos)
842 bound_pos = mini_pos - mod_mini_pos;
843 else {
7833c3f8
TI		 844 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
845 if (bound_pos >= azx_dev->core.bufsize)
b6050ef6
TI		 846 bound_pos = 0;
847 }
848
849 /* Calculate real DMA position we want */
850 return bound_pos + mod_dma_pos;
851}
852
c02f77d3
TI		 853#define AMD_FIFO_SIZE 32
854
855/* get the current DMA position with FIFO size correction */
856static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev)
857{
858 struct snd_pcm_substream *substream = azx_dev->core.substream;
859 struct snd_pcm_runtime *runtime = substream->runtime;
860 unsigned int pos, delay;
861
862 pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
863 if (!runtime)
864 return pos;
865
866 runtime->delay = AMD_FIFO_SIZE;
867 delay = frames_to_bytes(runtime, AMD_FIFO_SIZE);
868 if (azx_dev->insufficient) {
869 if (pos < delay) {
870 delay = pos;
871 runtime->delay = bytes_to_frames(runtime, pos);
872 } else {
873 azx_dev->insufficient = 0;
874 }
875 }
876
877 /* correct the DMA position for capture stream */
878 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
879 if (pos < delay)
880 pos += azx_dev->core.bufsize;
881 pos -= delay;
882 }
883
884 return pos;
885}
886
887static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev,
888 unsigned int pos)
889{
890 struct snd_pcm_substream *substream = azx_dev->core.substream;
891
892 /* just read back the calculated value in the above */
893 return substream->runtime->delay;
894}
895
f87e7f25
TI		 896static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
897 struct azx_dev *azx_dev)
898{
899 return _snd_hdac_chip_readl(azx_bus(chip),
900 AZX_REG_VS_SDXDPIB_XBASE +
901 (AZX_REG_VS_SDXDPIB_XINTERVAL *
902 azx_dev->core.index));
903}
904
905/* get the current DMA position with correction on SKL+ chips */
906static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
907{
908 /* DPIB register gives a more accurate position for playback */
909 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
910 return azx_skl_get_dpib_pos(chip, azx_dev);
911
912 /* For capture, we need to read posbuf, but it requires a delay
913 * for the possible boundary overlap; the read of DPIB fetches the
914 * actual posbuf
915 */
916 udelay(20);
917 azx_skl_get_dpib_pos(chip, azx_dev);
918 return azx_get_pos_posbuf(chip, azx_dev);
919}
920
83012a7c 921#ifdef CONFIG_PM
65fcd41d
TI		 922static DEFINE_MUTEX(card_list_lock);
923static LIST_HEAD(card_list);
924
925static void azx_add_card_list(struct azx *chip)
926{
9a34af4a 927 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 928 mutex_lock(&card_list_lock);
9a34af4a 929 list_add(&hda->list, &card_list);
65fcd41d
TI		 930 mutex_unlock(&card_list_lock);
931}
932
933static void azx_del_card_list(struct azx *chip)
934{
9a34af4a 935 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 936 mutex_lock(&card_list_lock);
9a34af4a 937 list_del_init(&hda->list);
65fcd41d
TI		 938 mutex_unlock(&card_list_lock);
939}
940
941/* trigger power-save check at writing parameter */
942static int param_set_xint(const char *val, const struct kernel_param *kp)
943{
9a34af4a 944 struct hda_intel *hda;
65fcd41d 945 struct azx *chip;
65fcd41d
TI		 946 int prev = power_save;
947 int ret = param_set_int(val, kp);
948
949 if (ret || prev == power_save)
950 return ret;
951
952 mutex_lock(&card_list_lock);
9a34af4a
TI		 953 list_for_each_entry(hda, &card_list, list) {
954 chip = &hda->chip;
a41d1224 955 if (!hda->probe_continued || chip->disabled)
65fcd41d 956 continue;
a41d1224 957 snd_hda_set_power_save(&chip->bus, power_save * 1000);
65fcd41d
TI		 958 }
959 mutex_unlock(&card_list_lock);
960 return 0;
961}
5c0b9bec 962
5c0b9bec
TI		 963/*
964 * power management
965 */
3baffc4a 966static bool azx_is_pm_ready(struct snd_card *card)
1da177e4 967{
2d9772ef
TI		 968 struct azx *chip;
969 struct hda_intel *hda;
1da177e4 970
2d9772ef 971 if (!card)
3baffc4a 972 return false;
2d9772ef
TI		 973 chip = card->private_data;
974 hda = container_of(chip, struct hda_intel, chip);
342e8449 975 if (chip->disabled || hda->init_failed || !chip->running)
3baffc4a
TI		 976 return false;
977 return true;
978}
979
980static void __azx_runtime_suspend(struct azx *chip)
981{
3baffc4a
TI		 982 azx_stop_chip(chip);
983 azx_enter_link_reset(chip);
984 azx_clear_irq_pending(chip);
e454ff8e 985 display_power(chip, false);
3baffc4a
TI		 986}
987
744c67ff 988static void __azx_runtime_resume(struct azx *chip, bool from_rt)
3baffc4a
TI		 989{
990 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
991 struct hdac_bus *bus = azx_bus(chip);
992 struct hda_codec *codec;
993 int status;
994
e454ff8e
TI		 995 display_power(chip, true);
996 if (hda->need_i915_power)
997 snd_hdac_i915_set_bclk(bus);
3baffc4a
TI		 998
999 /* Read STATESTS before controller reset */
1000 status = azx_readw(chip, STATESTS);
1001
1002 azx_init_pci(chip);
1003 hda_intel_init_chip(chip, true);
1004
744c67ff 1005 if (status && from_rt) {
3baffc4a 1006 list_for_each_codec(codec, &chip->bus)
8d6762af
TI		 1007 if (!codec->relaxed_resume &&
1008 (status & (1 << codec->addr)))
3baffc4a
TI		 1009 schedule_delayed_work(&codec->jackpoll_work,
1010 codec->jackpoll_interval);
1011 }
1012
1013 /* power down again for link-controlled chips */
e454ff8e 1014 if (!hda->need_i915_power)
029d92c2 1015 display_power(chip, false);
3baffc4a
TI		 1016}
1017
1018#ifdef CONFIG_PM_SLEEP
1019static int azx_suspend(struct device *dev)
1020{
1021 struct snd_card *card = dev_get_drvdata(dev);
1022 struct azx *chip;
1023 struct hdac_bus *bus;
1024
1025 if (!azx_is_pm_ready(card))
c5c21523
TI		 1026 return 0;
1027
3baffc4a 1028 chip = card->private_data;
a41d1224 1029 bus = azx_bus(chip);
421a1252 1030 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
c4c8dd6e 1031 pm_runtime_force_suspend(dev);
a41d1224
TI		 1032 if (bus->irq >= 0) {
1033 free_irq(bus->irq, chip);
1034 bus->irq = -1;
f36da940 1035 chip->card->sync_irq = -1;
30b35399 1036 }
a07187c9 1037
68e7fffc 1038 if (chip->msi)
43001c95 1039 pci_disable_msi(chip->pci);
785d8c4b
LY		 1040
1041 trace_azx_suspend(chip);
1da177e4
LT		 1042 return 0;
1043}
1044
68cb2b55 1045static int azx_resume(struct device *dev)
1da177e4 1046{
68cb2b55 1047 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef 1048 struct azx *chip;
2d9772ef 1049
3baffc4a 1050 if (!azx_is_pm_ready(card))
2d9772ef 1051 return 0;
1da177e4 1052
2d9772ef 1053 chip = card->private_data;
68e7fffc 1054 if (chip->msi)
3baffc4a 1055 if (pci_enable_msi(chip->pci) < 0)
68e7fffc
TI		 1056 chip->msi = 0;
1057 if (azx_acquire_irq(chip, 1) < 0)
30b35399 1058 return -EIO;
c4c8dd6e 1059
c4c8dd6e 1060 pm_runtime_force_resume(dev);
421a1252 1061 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
785d8c4b
LY		 1062
1063 trace_azx_resume(chip);
1da177e4
LT		 1064 return 0;
1065}
b8dfc462 1066
3e6db33a
XZ		 1067/* put codec down to D3 at hibernation for Intel SKL+;
1068 * otherwise BIOS may still access the codec and screw up the driver
1069 */
3e6db33a
XZ		 1070static int azx_freeze_noirq(struct device *dev)
1071{
a4b4793f
TI		 1072 struct snd_card *card = dev_get_drvdata(dev);
1073 struct azx *chip = card->private_data;
3e6db33a
XZ		 1074 struct pci_dev *pci = to_pci_dev(dev);
1075
10db5bcc
TI		 1076 if (!azx_is_pm_ready(card))
1077 return 0;
a4b4793f 1078 if (chip->driver_type == AZX_DRIVER_SKL)
3e6db33a
XZ		 1079 pci_set_power_state(pci, PCI_D3hot);
1080
1081 return 0;
1082}
1083
1084static int azx_thaw_noirq(struct device *dev)
1085{
a4b4793f
TI		 1086 struct snd_card *card = dev_get_drvdata(dev);
1087 struct azx *chip = card->private_data;
3e6db33a
XZ		 1088 struct pci_dev *pci = to_pci_dev(dev);
1089
10db5bcc
TI		 1090 if (!azx_is_pm_ready(card))
1091 return 0;
a4b4793f 1092 if (chip->driver_type == AZX_DRIVER_SKL)
3e6db33a
XZ		 1093 pci_set_power_state(pci, PCI_D0);
1094
1095 return 0;
1096}
1097#endif /* CONFIG_PM_SLEEP */
1098
b8dfc462
ML		 1099static int azx_runtime_suspend(struct device *dev)
1100{
1101 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef 1102 struct azx *chip;
b8dfc462 1103
3baffc4a 1104 if (!azx_is_pm_ready(card))
2d9772ef 1105 return 0;
2d9772ef 1106 chip = card->private_data;
246efa4a 1107
7d4f606c 1108 /* enable controller wake up event */
c4c8dd6e
TI		 1109 if (snd_power_get_state(card) == SNDRV_CTL_POWER_D0) {
1110 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1111 STATESTS_INT_MASK);
1112 }
7d4f606c 1113
3baffc4a 1114 __azx_runtime_suspend(chip);
785d8c4b 1115 trace_azx_runtime_suspend(chip);
b8dfc462
ML		 1116 return 0;
1117}
1118
1119static int azx_runtime_resume(struct device *dev)
1120{
1121 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef 1122 struct azx *chip;
c4c8dd6e 1123 bool from_rt = snd_power_get_state(card) == SNDRV_CTL_POWER_D0;
b8dfc462 1124
3baffc4a 1125 if (!azx_is_pm_ready(card))
2d9772ef 1126 return 0;
2d9772ef 1127 chip = card->private_data;
c4c8dd6e 1128 __azx_runtime_resume(chip, from_rt);
7d4f606c
WX		 1129
1130 /* disable controller Wake Up event*/
c4c8dd6e
TI		 1131 if (from_rt) {
1132 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1133 ~STATESTS_INT_MASK);
1134 }
7d4f606c 1135
785d8c4b 1136 trace_azx_runtime_resume(chip);
b8dfc462
ML		 1137 return 0;
1138}
6eb827d2
TI		 1139
1140static int azx_runtime_idle(struct device *dev)
1141{
1142 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 1143 struct azx *chip;
1144 struct hda_intel *hda;
1145
1146 if (!card)
1147 return 0;
6eb827d2 1148
2d9772ef
TI		 1149 chip = card->private_data;
1150 hda = container_of(chip, struct hda_intel, chip);
1618e84a 1151 if (chip->disabled || hda->init_failed)
246efa4a
DA		 1152 return 0;
1153
55ed9cd1 1154 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
342e8449 1155 azx_bus(chip)->codec_powered || !chip->running)
6eb827d2
TI		 1156 return -EBUSY;
1157
37a3a98e 1158 /* ELD notification gets broken when HD-audio bus is off */
dd23e1d5 1159 if (needs_eld_notify_link(chip))
37a3a98e
TI		 1160 return -EBUSY;
1161
6eb827d2
TI		 1162 return 0;
1163}
1164
b8dfc462
ML		 1165static const struct dev_pm_ops azx_pm = {
1166 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
3e6db33a
XZ		 1167#ifdef CONFIG_PM_SLEEP
1168 .freeze_noirq = azx_freeze_noirq,
1169 .thaw_noirq = azx_thaw_noirq,
1170#endif
6eb827d2 1171 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
b8dfc462
ML		 1172};
1173
68cb2b55
TI		 1174#define AZX_PM_OPS &azx_pm
1175#else
3baffc4a
TI		 1176#define azx_add_card_list(chip) /* NOP */
1177#define azx_del_card_list(chip) /* NOP */
68cb2b55 1178#define AZX_PM_OPS NULL
b8dfc462 1179#endif /* CONFIG_PM */
1da177e4
LT		 1180
1181
48c8b0eb 1182static int azx_probe_continue(struct azx *chip);
a82d51ed 1183
8393ec4a 1184#ifdef SUPPORT_VGA_SWITCHEROO
e23e7a14 1185static struct pci_dev *get_bound_vga(struct pci_dev *pci);
a82d51ed 1186
a82d51ed
TI		 1187static void azx_vs_set_state(struct pci_dev *pci,
1188 enum vga_switcheroo_state state)
1189{
1190 struct snd_card *card = pci_get_drvdata(pci);
1191 struct azx *chip = card->private_data;
9a34af4a 1192 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
07f4f97d 1193 struct hda_codec *codec;
a82d51ed
TI		 1194 bool disabled;
1195
9a34af4a
TI		 1196 wait_for_completion(&hda->probe_wait);
1197 if (hda->init_failed)
a82d51ed
TI		 1198 return;
1199
1200 disabled = (state == VGA_SWITCHEROO_OFF);
1201 if (chip->disabled == disabled)
1202 return;
1203
a41d1224 1204 if (!hda->probe_continued) {
a82d51ed
TI		 1205 chip->disabled = disabled;
1206 if (!disabled) {
4e76a883
TI		 1207 dev_info(chip->card->dev,
1208 "Start delayed initialization\n");
2393e755 1209 if (azx_probe_continue(chip) < 0)
4e76a883 1210 dev_err(chip->card->dev, "initialization error\n");
a82d51ed
TI		 1211 }
1212 } else {
2b760d88 1213 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
4e76a883 1214 disabled ? "Disabling" : "Enabling");
a82d51ed 1215 if (disabled) {
07f4f97d
LW		 1216 list_for_each_codec(codec, &chip->bus) {
1217 pm_runtime_suspend(hda_codec_dev(codec));
1218 pm_runtime_disable(hda_codec_dev(codec));
1219 }
1220 pm_runtime_suspend(card->dev);
1221 pm_runtime_disable(card->dev);
2b760d88 1222 /* when we get suspended by vga_switcheroo we end up in D3cold,
246efa4a
DA		 1223 * however we have no ACPI handle, so pci/acpi can't put us there,
1224 * put ourselves there */
1225 pci->current_state = PCI_D3cold;
a82d51ed 1226 chip->disabled = true;
a41d1224 1227 if (snd_hda_lock_devices(&chip->bus))
4e76a883
TI		 1228 dev_warn(chip->card->dev,
1229 "Cannot lock devices!\n");
a82d51ed 1230 } else {
a41d1224 1231 snd_hda_unlock_devices(&chip->bus);
a82d51ed 1232 chip->disabled = false;
07f4f97d
LW		 1233 pm_runtime_enable(card->dev);
1234 list_for_each_codec(codec, &chip->bus) {
1235 pm_runtime_enable(hda_codec_dev(codec));
1236 pm_runtime_resume(hda_codec_dev(codec));
1237 }
a82d51ed
TI		 1238 }
1239 }
1240}
1241
1242static bool azx_vs_can_switch(struct pci_dev *pci)
1243{
1244 struct snd_card *card = pci_get_drvdata(pci);
1245 struct azx *chip = card->private_data;
9a34af4a 1246 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed 1247
9a34af4a
TI		 1248 wait_for_completion(&hda->probe_wait);
1249 if (hda->init_failed)
a82d51ed 1250 return false;
a41d1224 1251 if (chip->disabled || !hda->probe_continued)
a82d51ed 1252 return true;
a41d1224 1253 if (snd_hda_lock_devices(&chip->bus))
a82d51ed 1254 return false;
a41d1224 1255 snd_hda_unlock_devices(&chip->bus);
a82d51ed
TI		 1256 return true;
1257}
1258
37a3a98e
TI		 1259/*
1260 * The discrete GPU cannot power down unless the HDA controller runtime
1261 * suspends, so activate runtime PM on codecs even if power_save == 0.
1262 */
1263static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1264{
1265 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1266 struct hda_codec *codec;
1267
dd23e1d5 1268 if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) {
37a3a98e
TI		 1269 list_for_each_codec(codec, &chip->bus)
1270 codec->auto_runtime_pm = 1;
1271 /* reset the power save setup */
1272 if (chip->running)
1273 set_default_power_save(chip);
1274 }
1275}
1276
1277static void azx_vs_gpu_bound(struct pci_dev *pci,
1278 enum vga_switcheroo_client_id client_id)
1279{
1280 struct snd_card *card = pci_get_drvdata(pci);
1281 struct azx *chip = card->private_data;
37a3a98e
TI		 1282
1283 if (client_id == VGA_SWITCHEROO_DIS)
dd23e1d5 1284 chip->bus.keep_power = 0;
37a3a98e
TI		 1285 setup_vga_switcheroo_runtime_pm(chip);
1286}
1287
e23e7a14 1288static void init_vga_switcheroo(struct azx *chip)
a82d51ed 1289{
9a34af4a 1290 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed 1291 struct pci_dev *p = get_bound_vga(chip->pci);
bacd8614 1292 struct pci_dev *parent;
a82d51ed 1293 if (p) {
4e76a883 1294 dev_info(chip->card->dev,
2b760d88 1295 "Handle vga_switcheroo audio client\n");
9a34af4a 1296 hda->use_vga_switcheroo = 1;
bacd8614
KHF		 1297
1298 /* cleared in either gpu_bound op or codec probe, or when its
1299 * upstream port has _PR3 (i.e. dGPU).
1300 */
1301 parent = pci_upstream_bridge(p);
1302 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1;
07f4f97d 1303 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
a82d51ed
TI		 1304 pci_dev_put(p);
1305 }
1306}
1307
1308static const struct vga_switcheroo_client_ops azx_vs_ops = {
1309 .set_gpu_state = azx_vs_set_state,
1310 .can_switch = azx_vs_can_switch,
37a3a98e 1311 .gpu_bound = azx_vs_gpu_bound,
a82d51ed
TI		 1312};
1313
e23e7a14 1314static int register_vga_switcheroo(struct azx *chip)
a82d51ed 1315{
9a34af4a 1316 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
4aaf448f 1317 struct pci_dev *p;
128960a9
TI		 1318 int err;
1319
9a34af4a 1320 if (!hda->use_vga_switcheroo)
a82d51ed 1321 return 0;
4aaf448f
JQ		 1322
1323 p = get_bound_vga(chip->pci);
1324 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1325 pci_dev_put(p);
1326
128960a9
TI		 1327 if (err < 0)
1328 return err;
9a34af4a 1329 hda->vga_switcheroo_registered = 1;
246efa4a 1330
128960a9 1331 return 0;
a82d51ed
TI		 1332}
1333#else
1334#define init_vga_switcheroo(chip) /* NOP */
1335#define register_vga_switcheroo(chip) 0
8393ec4a 1336#define check_hdmi_disabled(pci) false
37a3a98e 1337#define setup_vga_switcheroo_runtime_pm(chip) /* NOP */
a82d51ed
TI		 1338#endif /* SUPPORT_VGA_SWITCHER */
1339
1da177e4
LT		 1340/*
1341 * destructor
1342 */
2393e755 1343static void azx_free(struct azx *chip)
1da177e4 1344{
c67e2228 1345 struct pci_dev *pci = chip->pci;
a07187c9 1346 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a41d1224 1347 struct hdac_bus *bus = azx_bus(chip);
4ce107b9 1348
2393e755
TI		 1349 if (hda->freed)
1350 return;
1351
364aa716 1352 if (azx_has_pm_runtime(chip) && chip->running)
c67e2228 1353 pm_runtime_get_noresume(&pci->dev);
37a3a98e 1354 chip->running = 0;
c67e2228 1355
65fcd41d
TI		 1356 azx_del_card_list(chip);
1357
9a34af4a
TI		 1358 hda->init_failed = 1; /* to be sure */
1359 complete_all(&hda->probe_wait);
f4c482a4 1360
9a34af4a 1361 if (use_vga_switcheroo(hda)) {
a41d1224
TI		 1362 if (chip->disabled && hda->probe_continued)
1363 snd_hda_unlock_devices(&chip->bus);
07f4f97d 1364 if (hda->vga_switcheroo_registered)
128960a9 1365 vga_switcheroo_unregister_client(chip->pci);
a82d51ed
TI		 1366 }
1367
a41d1224 1368 if (bus->chip_init) {
9ad593f6 1369 azx_clear_irq_pending(chip);
7833c3f8 1370 azx_stop_all_streams(chip);
1a7f60b9 1371 azx_stop_chip(chip);
1da177e4
LT		 1372 }
1373
a41d1224
TI		 1374 if (bus->irq >= 0)
1375 free_irq(bus->irq, (void*)chip);
68e7fffc 1376 if (chip->msi)
30b35399 1377 pci_disable_msi(chip->pci);
a41d1224 1378 iounmap(bus->remap_addr);
1da177e4 1379
67908994 1380 azx_free_stream_pages(chip);
a41d1224
TI		 1381 azx_free_streams(chip);
1382 snd_hdac_bus_exit(bus);
1383
a82d51ed
TI		 1384 if (chip->region_requested)
1385 pci_release_regions(chip->pci);
a41d1224 1386
1da177e4 1387 pci_disable_device(chip->pci);
4918cdab 1388#ifdef CONFIG_SND_HDA_PATCH_LOADER
f0acd28c 1389 release_firmware(chip->fw);
4918cdab 1390#endif
e454ff8e 1391 display_power(chip, false);
98d8fc6c 1392
fc18282c 1393 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
fcc88d91 1394 snd_hdac_i915_exit(bus);
1da177e4 1395
2393e755 1396 hda->freed = 1;
1da177e4
LT		 1397}
1398
a41d1224
TI		 1399static int azx_dev_disconnect(struct snd_device *device)
1400{
1401 struct azx *chip = device->device_data;
ca58f551 1402 struct hdac_bus *bus = azx_bus(chip);
a41d1224
TI		 1403
1404 chip->bus.shutdown = 1;
ca58f551
TI		 1405 cancel_work_sync(&bus->unsol_work);
1406
a41d1224
TI		 1407 return 0;
1408}
1409
a98f90fd 1410static int azx_dev_free(struct snd_device *device)
1da177e4 1411{
2393e755
TI		 1412 azx_free(device->device_data);
1413 return 0;
1da177e4
LT		 1414}
1415
8393ec4a 1416#ifdef SUPPORT_VGA_SWITCHEROO
586bc4aa
AD		 1417#ifdef CONFIG_ACPI
1418/* ATPX is in the integrated GPU's namespace */
1419static bool atpx_present(void)
1420{
1421 struct pci_dev *pdev = NULL;
1422 acpi_handle dhandle, atpx_handle;
1423 acpi_status status;
1424
8cc0991c
AD		 1425 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
1426 dhandle = ACPI_HANDLE(&pdev->dev);
1427 if (dhandle) {
1428 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
1429 if (!ACPI_FAILURE(status)) {
1430 pci_dev_put(pdev);
1431 return true;
1432 }
1433 }
1434 }
1435 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
586bc4aa
AD		 1436 dhandle = ACPI_HANDLE(&pdev->dev);
1437 if (dhandle) {
1438 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
1439 if (!ACPI_FAILURE(status)) {
1440 pci_dev_put(pdev);
1441 return true;
1442 }
1443 }
586bc4aa
AD		 1444 }
1445 return false;
1446}
1447#else
1448static bool atpx_present(void)
1449{
1450 return false;
1451}
1452#endif
1453
9121947d 1454/*
2b760d88 1455 * Check of disabled HDMI controller by vga_switcheroo
9121947d 1456 */
e23e7a14 1457static struct pci_dev *get_bound_vga(struct pci_dev *pci)
9121947d
TI		 1458{
1459 struct pci_dev *p;
1460
1461 /* check only discrete GPU */
1462 switch (pci->vendor) {
1463 case PCI_VENDOR_ID_ATI:
1464 case PCI_VENDOR_ID_AMD:
586bc4aa
AD		 1465 if (pci->devfn == 1) {
1466 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1467 pci->bus->number, 0);
1468 if (p) {
1469 /* ATPX is in the integrated GPU's ACPI namespace
1470 * rather than the dGPU's namespace. However,
1471 * the dGPU is the one who is involved in
1472 * vgaswitcheroo.
1473 */
1474 if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) &&
1475 atpx_present())
1476 return p;
1477 pci_dev_put(p);
1478 }
1479 }
1480 break;
9121947d
TI		 1481 case PCI_VENDOR_ID_NVIDIA:
1482 if (pci->devfn == 1) {
1483 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1484 pci->bus->number, 0);
1485 if (p) {
b6d7b362 1486 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
9121947d
TI		 1487 return p;
1488 pci_dev_put(p);
1489 }
1490 }
1491 break;
1492 }
1493 return NULL;
1494}
1495
e23e7a14 1496static bool check_hdmi_disabled(struct pci_dev *pci)
9121947d
TI		 1497{
1498 bool vga_inactive = false;
1499 struct pci_dev *p = get_bound_vga(pci);
1500
1501 if (p) {
12b78a7f 1502 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 1503 vga_inactive = true;
1504 pci_dev_put(p);
1505 }
1506 return vga_inactive;
1507}
8393ec4a 1508#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 1509
3372a153
TI		 1510/*
1511 * white/black-listing for position_fix
1512 */
a5dc05e4 1513static const struct snd_pci_quirk position_fix_list[] = {
d2e1c973
TI		 1514 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1515 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 1516 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 1517 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 1518 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 1519 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 1520 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 1521 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 1522 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 1523 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 1524 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 1525 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 1526 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 1527 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 1528 {}
1529};
1530
e23e7a14 1531static int check_position_fix(struct azx *chip, int fix)
3372a153
TI		 1532{
1533 const struct snd_pci_quirk *q;
1534
c673ba1c 1535 switch (fix) {
1dac6695 1536 case POS_FIX_AUTO:
c673ba1c
TI		 1537 case POS_FIX_LPIB:
1538 case POS_FIX_POSBUF:
4cb36310 1539 case POS_FIX_VIACOMBO:
a6f2fd55 1540 case POS_FIX_COMBO:
f87e7f25 1541 case POS_FIX_SKL:
c02f77d3 1542 case POS_FIX_FIFO:
c673ba1c
TI		 1543 return fix;
1544 }
1545
c673ba1c
TI		 1546 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1547 if (q) {
4e76a883
TI		 1548 dev_info(chip->card->dev,
1549 "position_fix set to %d for device %04x:%04x\n",
1550 q->value, q->subvendor, q->subdevice);
c673ba1c 1551 return q->value;
3372a153 1552 }
bdd9ef24
DH		 1553
1554 /* Check VIA/ATI HD Audio Controller exist */
26f05717 1555 if (chip->driver_type == AZX_DRIVER_VIA) {
4e76a883 1556 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
bdd9ef24 1557 return POS_FIX_VIACOMBO;
9477c58e 1558 }
c02f77d3
TI		 1559 if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) {
1560 dev_dbg(chip->card->dev, "Using FIFO position fix\n");
1561 return POS_FIX_FIFO;
1562 }
9477c58e 1563 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
4e76a883 1564 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
50e3bbf9 1565 return POS_FIX_LPIB;
bdd9ef24 1566 }
a4b4793f 1567 if (chip->driver_type == AZX_DRIVER_SKL) {
f87e7f25
TI		 1568 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1569 return POS_FIX_SKL;
1570 }
c673ba1c 1571 return POS_FIX_AUTO;
3372a153
TI		 1572}
1573
b6050ef6
TI		 1574static void assign_position_fix(struct azx *chip, int fix)
1575{
bf82326f 1576 static const azx_get_pos_callback_t callbacks[] = {
b6050ef6
TI		 1577 [POS_FIX_AUTO] = NULL,
1578 [POS_FIX_LPIB] = azx_get_pos_lpib,
1579 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1580 [POS_FIX_VIACOMBO] = azx_via_get_position,
1581 [POS_FIX_COMBO] = azx_get_pos_lpib,
f87e7f25 1582 [POS_FIX_SKL] = azx_get_pos_skl,
c02f77d3 1583 [POS_FIX_FIFO] = azx_get_pos_fifo,
b6050ef6
TI		 1584 };
1585
1586 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1587
1588 /* combo mode uses LPIB only for playback */
1589 if (fix == POS_FIX_COMBO)
1590 chip->get_position[1] = NULL;
1591
f87e7f25 1592 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
b6050ef6
TI		 1593 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1594 chip->get_delay[0] = chip->get_delay[1] =
1595 azx_get_delay_from_lpib;
1596 }
1597
c02f77d3
TI		 1598 if (fix == POS_FIX_FIFO)
1599 chip->get_delay[0] = chip->get_delay[1] =
1600 azx_get_delay_from_fifo;
b6050ef6
TI		 1601}
1602
669ba27a
TI		 1603/*
1604 * black-lists for probe_mask
1605 */
a5dc05e4 1606static const struct snd_pci_quirk probe_mask_list[] = {
669ba27a
TI		 1607 /* Thinkpad often breaks the controller communication when accessing
1608 * to the non-working (or non-existing) modem codec slot.
1609 */
1610 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1611 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1612 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 1613 /* broken BIOS */
1614 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 1615 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1616 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 1617 /* forced codec slots */
93574844 1618 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 1619 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 1620 /* WinFast VP200 H (Teradici) user reported broken communication */
1621 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 1622 {}
1623};
1624
f1eaaeec
TI		 1625#define AZX_FORCE_CODEC_MASK 0x100
1626
e23e7a14 1627static void check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 1628{
1629 const struct snd_pci_quirk *q;
1630
f1eaaeec
TI		 1631 chip->codec_probe_mask = probe_mask[dev];
1632 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 1633 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1634 if (q) {
4e76a883
TI		 1635 dev_info(chip->card->dev,
1636 "probe_mask set to 0x%x for device %04x:%04x\n",
1637 q->value, q->subvendor, q->subdevice);
f1eaaeec 1638 chip->codec_probe_mask = q->value;
669ba27a
TI		 1639 }
1640 }
f1eaaeec
TI		 1641
1642 /* check forced option */
1643 if (chip->codec_probe_mask != -1 &&
1644 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
a41d1224 1645 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
4e76a883 1646 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
a41d1224 1647 (int)azx_bus(chip)->codec_mask);
f1eaaeec 1648 }
669ba27a
TI		 1649}
1650
4d8e22e0 1651/*
71623855 1652 * white/black-list for enable_msi
4d8e22e0 1653 */
a5dc05e4 1654static const struct snd_pci_quirk msi_black_list[] = {
693e0cb0
DH		 1655 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1656 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1657 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1658 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
9dc8398b 1659 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 1660 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 1661 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
83f72151 1662 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
4193d13b 1663 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 1664 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 1665 {}
1666};
1667
e23e7a14 1668static void check_msi(struct azx *chip)
4d8e22e0
TI		 1669{
1670 const struct snd_pci_quirk *q;
1671
71623855
TI		 1672 if (enable_msi >= 0) {
1673 chip->msi = !!enable_msi;
4d8e22e0 1674 return;
71623855
TI		 1675 }
1676 chip->msi = 1; /* enable MSI as default */
1677 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0 1678 if (q) {
4e76a883
TI		 1679 dev_info(chip->card->dev,
1680 "msi for device %04x:%04x set to %d\n",
1681 q->subvendor, q->subdevice, q->value);
4d8e22e0 1682 chip->msi = q->value;
80c43ed7
TI		 1683 return;
1684 }
1685
1686 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e 1687 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
4e76a883 1688 dev_info(chip->card->dev, "Disabling MSI\n");
80c43ed7 1689 chip->msi = 0;
4d8e22e0
TI		 1690 }
1691}
1692
a1585d76 1693/* check the snoop mode availability */
e23e7a14 1694static void azx_check_snoop_available(struct azx *chip)
a1585d76 1695{
7c732015 1696 int snoop = hda_snoop;
a1585d76 1697
7c732015
TI		 1698 if (snoop >= 0) {
1699 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1700 snoop ? "snoop" : "non-snoop");
1701 chip->snoop = snoop;
78c9be61 1702 chip->uc_buffer = !snoop;
7c732015
TI		 1703 return;
1704 }
1705
1706 snoop = true;
37e661ee
TI		 1707 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1708 chip->driver_type == AZX_DRIVER_VIA) {
a1585d76
TI		 1709 /* force to non-snoop mode for a new VIA controller
1710 * when BIOS is set
1711 */
7c732015
TI		 1712 u8 val;
1713 pci_read_config_byte(chip->pci, 0x42, &val);
af52f998
DW		 1714 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1715 chip->pci->revision == 0x20))
7c732015 1716 snoop = false;
a1585d76
TI		 1717 }
1718
37e661ee
TI		 1719 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1720 snoop = false;
1721
7c732015 1722 chip->snoop = snoop;
78c9be61 1723 if (!snoop) {
7c732015 1724 dev_info(chip->card->dev, "Force to non-snoop mode\n");
78c9be61
TI		 1725 /* C-Media requires non-cached pages only for CORB/RIRB */
1726 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1727 chip->uc_buffer = true;
1728 }
a1585d76 1729}
669ba27a 1730
99a2008d
WX		 1731static void azx_probe_work(struct work_struct *work)
1732{
9a34af4a
TI		 1733 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1734 azx_probe_continue(&hda->chip);
99a2008d 1735}
99a2008d 1736
4f0189be
TI		 1737static int default_bdl_pos_adj(struct azx *chip)
1738{
2cf721db
TI		 1739 /* some exceptions: Atoms seem problematic with value 1 */
1740 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1741 switch (chip->pci->device) {
1742 case 0x0f04: /* Baytrail */
1743 case 0x2284: /* Braswell */
1744 return 32;
1745 }
1746 }
1747
4f0189be
TI		 1748 switch (chip->driver_type) {
1749 case AZX_DRIVER_ICH:
1750 case AZX_DRIVER_PCH:
1751 return 1;
1752 default:
1753 return 32;
1754 }
1755}
1756
1da177e4
LT		 1757/*
1758 * constructor
1759 */
a43ff5ba
TI		 1760static const struct hda_controller_ops pci_hda_ops;
1761
e23e7a14
BP		 1762static int azx_create(struct snd_card *card, struct pci_dev *pci,
1763 int dev, unsigned int driver_caps,
1764 struct azx **rchip)
1da177e4 1765{
41f394a8 1766 static const struct snd_device_ops ops = {
a41d1224 1767 .dev_disconnect = azx_dev_disconnect,
1da177e4
LT		 1768 .dev_free = azx_dev_free,
1769 };
a07187c9 1770 struct hda_intel *hda;
a82d51ed
TI		 1771 struct azx *chip;
1772 int err;
1da177e4
LT		 1773
1774 *rchip = NULL;
bcd72003 1775
927fc866
PM		 1776 err = pci_enable_device(pci);
1777 if (err < 0)
1da177e4
LT		 1778 return err;
1779
2393e755 1780 hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL);
a07187c9 1781 if (!hda) {
1da177e4
LT		 1782 pci_disable_device(pci);
1783 return -ENOMEM;
1784 }
1785
a07187c9 1786 chip = &hda->chip;
62932df8 1787 mutex_init(&chip->open_mutex);
1da177e4
LT		 1788 chip->card = card;
1789 chip->pci = pci;
a43ff5ba 1790 chip->ops = &pci_hda_ops;
9477c58e
TI		 1791 chip->driver_caps = driver_caps;
1792 chip->driver_type = driver_caps & 0xff;
4d8e22e0 1793 check_msi(chip);
555e219f 1794 chip->dev_index = dev;
3a182c84
TI		 1795 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1796 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
01b65bfb 1797 INIT_LIST_HEAD(&chip->pcm_list);
9a34af4a
TI		 1798 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1799 INIT_LIST_HEAD(&hda->list);
a82d51ed 1800 init_vga_switcheroo(chip);
9a34af4a 1801 init_completion(&hda->probe_wait);
1da177e4 1802
b6050ef6 1803 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
a6f2fd55 1804
5aba4f8e 1805 check_probe_mask(chip, dev);
3372a153 1806
41438f13
TI		 1807 if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1808 chip->fallback_to_single_cmd = 1;
1809 else /* explicitly set to single_cmd or not */
1810 chip->single_cmd = single_cmd;
1811
a1585d76 1812 azx_check_snoop_available(chip);
c74db86b 1813
4f0189be
TI		 1814 if (bdl_pos_adj[dev] < 0)
1815 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1816 else
1817 chip->bdl_pos_adj = bdl_pos_adj[dev];
5c0d7bc1 1818
19abfefd 1819 err = azx_bus_init(chip, model[dev]);
a41d1224 1820 if (err < 0) {
a41d1224
TI		 1821 pci_disable_device(pci);
1822 return err;
1823 }
1824
619a1f19
TI		 1825 /* use the non-cached pages in non-snoop mode */
1826 if (!azx_snoop(chip))
1827 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_UC;
1828
7d9a1808
TI		 1829 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1830 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
5f2cb361 1831 chip->bus.core.needs_damn_long_delay = 1;
7d9a1808
TI		 1832 }
1833
a82d51ed
TI		 1834 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1835 if (err < 0) {
4e76a883 1836 dev_err(card->dev, "Error creating device [card]!\n");
a82d51ed
TI		 1837 azx_free(chip);
1838 return err;
1839 }
1840
99a2008d 1841 /* continue probing in work context as may trigger request module */
9a34af4a 1842 INIT_WORK(&hda->probe_work, azx_probe_work);
99a2008d 1843
a82d51ed 1844 *rchip = chip;
99a2008d 1845
a82d51ed
TI		 1846 return 0;
1847}
1848
48c8b0eb 1849static int azx_first_init(struct azx *chip)
a82d51ed
TI		 1850{
1851 int dev = chip->dev_index;
1852 struct pci_dev *pci = chip->pci;
1853 struct snd_card *card = chip->card;
a41d1224 1854 struct hdac_bus *bus = azx_bus(chip);
67908994 1855 int err;
a82d51ed 1856 unsigned short gcap;
413cbf46 1857 unsigned int dma_bits = 64;
a82d51ed 1858
07e4ca50
TI		 1859#if BITS_PER_LONG != 64
1860 /* Fix up base address on ULI M5461 */
1861 if (chip->driver_type == AZX_DRIVER_ULI) {
1862 u16 tmp3;
1863 pci_read_config_word(pci, 0x40, &tmp3);
1864 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1865 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1866 }
1867#endif
1868
927fc866 1869 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 1870 if (err < 0)
1da177e4 1871 return err;
a82d51ed 1872 chip->region_requested = 1;
1da177e4 1873
a41d1224
TI		 1874 bus->addr = pci_resource_start(pci, 0);
1875 bus->remap_addr = pci_ioremap_bar(pci, 0);
1876 if (bus->remap_addr == NULL) {
4e76a883 1877 dev_err(card->dev, "ioremap error\n");
a82d51ed 1878 return -ENXIO;
1da177e4
LT		 1879 }
1880
a4b4793f 1881 if (chip->driver_type == AZX_DRIVER_SKL)
50279d9b
GS		 1882 snd_hdac_bus_parse_capabilities(bus);
1883
1884 /*
1885 * Some Intel CPUs has always running timer (ART) feature and
1886 * controller may have Global time sync reporting capability, so
1887 * check both of these before declaring synchronized time reporting
1888 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1889 */
1890 chip->gts_present = false;
1891
1892#ifdef CONFIG_X86
1893 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1894 chip->gts_present = true;
1895#endif
1896
db79afa1
BH		 1897 if (chip->msi) {
1898 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1899 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1900 pci->no_64bit_msi = true;
1901 }
68e7fffc
TI		 1902 if (pci_enable_msi(pci) < 0)
1903 chip->msi = 0;
db79afa1 1904 }
7376d013 1905
1da177e4 1906 pci_set_master(pci);
1da177e4 1907
bcd72003 1908 gcap = azx_readw(chip, GCAP);
4e76a883 1909 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
bcd72003 1910
413cbf46
TI		 1911 /* AMD devices support 40 or 48bit DMA, take the safe one */
1912 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1913 dma_bits = 40;
1914
dc4c2e6b 1915 /* disable SB600 64bit support for safety */
9477c58e 1916 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b 1917 struct pci_dev *p_smbus;
413cbf46 1918 dma_bits = 40;
dc4c2e6b
AB		 1919 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1920 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1921 NULL);
1922 if (p_smbus) {
1923 if (p_smbus->revision < 0x30)
fb1d8ac2 1924 gcap &= ~AZX_GCAP_64OK;
dc4c2e6b
AB		 1925 pci_dev_put(p_smbus);
1926 }
1927 }
09240cf4 1928
3ab7511e
AB		 1929 /* NVidia hardware normally only supports up to 40 bits of DMA */
1930 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1931 dma_bits = 40;
1932
9477c58e
TI		 1933 /* disable 64bit DMA address on some devices */
1934 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
4e76a883 1935 dev_dbg(card->dev, "Disabling 64bit DMA\n");
fb1d8ac2 1936 gcap &= ~AZX_GCAP_64OK;
9477c58e 1937 }
396087ea 1938
2ae66c26 1939 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 1940 if (align_buffer_size >= 0)
1941 chip->align_buffer_size = !!align_buffer_size;
1942 else {
103884a3 1943 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
7bfe059e 1944 chip->align_buffer_size = 0;
7bfe059e
TI		 1945 else
1946 chip->align_buffer_size = 1;
1947 }
2ae66c26 1948
cf7aaca8 1949 /* allow 64bit DMA address if supported by H/W */
413cbf46
TI		 1950 if (!(gcap & AZX_GCAP_64OK))
1951 dma_bits = 32;
412b979c
QL		 1952 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1953 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
413cbf46 1954 } else {
412b979c
QL		 1955 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1956 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
09240cf4 1957 }
cf7aaca8 1958
8b6ed8e7
TI		 1959 /* read number of streams from GCAP register instead of using
1960 * hardcoded value
1961 */
1962 chip->capture_streams = (gcap >> 8) & 0x0f;
1963 chip->playback_streams = (gcap >> 12) & 0x0f;
1964 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 1965 /* gcap didn't give any info, switching to old method */
1966
1967 switch (chip->driver_type) {
1968 case AZX_DRIVER_ULI:
1969 chip->playback_streams = ULI_NUM_PLAYBACK;
1970 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 1971 break;
1972 case AZX_DRIVER_ATIHDMI:
1815b34a 1973 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 1974 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1975 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 1976 break;
c4da29ca 1977 case AZX_DRIVER_GENERIC:
bcd72003
TD		 1978 default:
1979 chip->playback_streams = ICH6_NUM_PLAYBACK;
1980 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 1981 break;
1982 }
07e4ca50 1983 }
8b6ed8e7
TI		 1984 chip->capture_index_offset = 0;
1985 chip->playback_index_offset = chip->capture_streams;
07e4ca50 1986 chip->num_streams = chip->playback_streams + chip->capture_streams;
07e4ca50 1987
df56c3db
JK		 1988 /* sanity check for the SDxCTL.STRM field overflow */
1989 if (chip->num_streams > 15 &&
1990 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1991 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1992 "forcing separate stream tags", chip->num_streams);
1993 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1994 }
1995
a41d1224
TI		 1996 /* initialize streams */
1997 err = azx_init_streams(chip);
81740861 1998 if (err < 0)
a82d51ed 1999 return err;
1da177e4 2000
a41d1224
TI		 2001 err = azx_alloc_stream_pages(chip);
2002 if (err < 0)
2003 return err;
1da177e4
LT		 2004
2005 /* initialize chip */
cb53c626 2006 azx_init_pci(chip);
e4d9e513 2007
e454ff8e 2008 snd_hdac_i915_set_bclk(bus);
e4d9e513 2009
0a673521 2010 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 2011
2012 /* codec detection */
a41d1224 2013 if (!azx_bus(chip)->codec_mask) {
4e76a883 2014 dev_err(card->dev, "no codecs found!\n");
9479e75f 2015 /* keep running the rest for the runtime PM */
1da177e4
LT		 2016 }
2017
f495222e
TI		 2018 if (azx_acquire_irq(chip, 0) < 0)
2019 return -EBUSY;
2020
07e4ca50 2021 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 2022 strlcpy(card->shortname, driver_short_names[chip->driver_type],
2023 sizeof(card->shortname));
2024 snprintf(card->longname, sizeof(card->longname),
2025 "%s at 0x%lx irq %i",
a41d1224 2026 card->shortname, bus->addr, bus->irq);
07e4ca50 2027
1da177e4 2028 return 0;
1da177e4
LT		 2029}
2030
97c6a3d1 2031#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 2032/* callback from request_firmware_nowait() */
2033static void azx_firmware_cb(const struct firmware *fw, void *context)
2034{
2035 struct snd_card *card = context;
2036 struct azx *chip = card->private_data;
5cb543db 2037
25faa4bd
TI		 2038 if (fw)
2039 chip->fw = fw;
2040 else
2041 dev_err(card->dev, "Cannot load firmware, continue without patching\n");
5cb543db
TI		 2042 if (!chip->disabled) {
2043 /* continue probing */
25faa4bd 2044 azx_probe_continue(chip);
5cb543db 2045 }
5cb543db 2046}
97c6a3d1 2047#endif
5cb543db 2048
f46ea609
DR		 2049static int disable_msi_reset_irq(struct azx *chip)
2050{
a41d1224 2051 struct hdac_bus *bus = azx_bus(chip);
f46ea609
DR		 2052 int err;
2053
a41d1224
TI		 2054 free_irq(bus->irq, chip);
2055 bus->irq = -1;
f36da940 2056 chip->card->sync_irq = -1;
f46ea609
DR		 2057 pci_disable_msi(chip->pci);
2058 chip->msi = 0;
2059 err = azx_acquire_irq(chip, 1);
2060 if (err < 0)
2061 return err;
2062
2063 return 0;
2064}
2065
8769b278
DR		 2066static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2067 struct vm_area_struct *area)
2068{
2069#ifdef CONFIG_X86
2070 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2071 struct azx *chip = apcm->chip;
78c9be61 2072 if (chip->uc_buffer)
8769b278
DR		 2073 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2074#endif
2075}
2076
3c6fd1f0
TI		 2077/* Blacklist for skipping the whole probe:
2078 * some HD-audio PCI entries are exposed without any codecs, and such devices
2079 * should be ignored from the beginning.
2080 */
977dfef4
TI		 2081static const struct pci_device_id driver_blacklist[] = {
2082 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */
2083 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */
2084 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */
3c6fd1f0
TI		 2085 {}
2086};
2087
a43ff5ba
TI		 2088static const struct hda_controller_ops pci_hda_ops = {
2089 .disable_msi_reset_irq = disable_msi_reset_irq,
8769b278 2090 .pcm_mmap_prepare = pcm_mmap_prepare,
7ca954a8 2091 .position_check = azx_position_check,
40830813
DR		 2092};
2093
e23e7a14
BP		 2094static int azx_probe(struct pci_dev *pci,
2095 const struct pci_device_id *pci_id)
1da177e4 2096{
5aba4f8e 2097 static int dev;
a98f90fd 2098 struct snd_card *card;
9a34af4a 2099 struct hda_intel *hda;
a98f90fd 2100 struct azx *chip;
aad730d0 2101 bool schedule_probe;
927fc866 2102 int err;
1da177e4 2103
977dfef4 2104 if (pci_match_id(driver_blacklist, pci)) {
3c6fd1f0
TI		 2105 dev_info(&pci->dev, "Skipping the blacklisted device\n");
2106 return -ENODEV;
2107 }
2108
5aba4f8e
TI		 2109 if (dev >= SNDRV_CARDS)
2110 return -ENODEV;
2111 if (!enable[dev]) {
2112 dev++;
2113 return -ENOENT;
2114 }
2115
82d9d54a
JK		 2116 /*
2117 * stop probe if another Intel's DSP driver should be activated
2118 */
7fba6aea 2119 if (dmic_detect) {
82d9d54a
JK		 2120 err = snd_intel_dsp_driver_probe(pci);
2121 if (err != SND_INTEL_DSP_DRIVER_ANY &&
2122 err != SND_INTEL_DSP_DRIVER_LEGACY)
2123 return -ENODEV;
7fba6aea
TI		 2124 } else {
2125 dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n");
82d9d54a
JK		 2126 }
2127
60c5772b
TI		 2128 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2129 0, &card);
e58de7ba 2130 if (err < 0) {
4e76a883 2131 dev_err(&pci->dev, "Error creating card!\n");
e58de7ba 2132 return err;
1da177e4
LT		 2133 }
2134
a43ff5ba 2135 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 2136 if (err < 0)
2137 goto out_free;
421a1252 2138 card->private_data = chip;
9a34af4a 2139 hda = container_of(chip, struct hda_intel, chip);
f4c482a4
TI		 2140
2141 pci_set_drvdata(pci, card);
2142
2143 err = register_vga_switcheroo(chip);
2144 if (err < 0) {
2b760d88 2145 dev_err(card->dev, "Error registering vga_switcheroo client\n");
f4c482a4
TI		 2146 goto out_free;
2147 }
2148
2149 if (check_hdmi_disabled(pci)) {
4e76a883
TI		 2150 dev_info(card->dev, "VGA controller is disabled\n");
2151 dev_info(card->dev, "Delaying initialization\n");
f4c482a4
TI		 2152 chip->disabled = true;
2153 }
2154
aad730d0 2155 schedule_probe = !chip->disabled;
1da177e4 2156
4918cdab
TI		 2157#ifdef CONFIG_SND_HDA_PATCH_LOADER
2158 if (patch[dev] && *patch[dev]) {
4e76a883
TI		 2159 dev_info(card->dev, "Applying patch firmware '%s'\n",
2160 patch[dev]);
5cb543db
TI		 2161 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2162 &pci->dev, GFP_KERNEL, card,
2163 azx_firmware_cb);
4918cdab
TI		 2164 if (err < 0)
2165 goto out_free;
aad730d0 2166 schedule_probe = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 2167 }
2168#endif /* CONFIG_SND_HDA_PATCH_LOADER */
2169
aad730d0 2170#ifndef CONFIG_SND_HDA_I915
6ee8eeb4
TI		 2171 if (CONTROLLER_IN_GPU(pci))
2172 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
99a2008d 2173#endif
99a2008d 2174
aad730d0 2175 if (schedule_probe)
9a34af4a 2176 schedule_work(&hda->probe_work);
a82d51ed 2177
a82d51ed 2178 dev++;
88d071fc 2179 if (chip->disabled)
9a34af4a 2180 complete_all(&hda->probe_wait);
a82d51ed
TI		 2181 return 0;
2182
2183out_free:
2184 snd_card_free(card);
2185 return err;
2186}
2187
1ba8f9d3
HG		 2188#ifdef CONFIG_PM
2189/* On some boards setting power_save to a non 0 value leads to clicking /
2190 * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2191 * figure out how to avoid these sounds, but that is not always feasible.
2192 * So we keep a list of devices where we disable powersaving as its known
2193 * to causes problems on these devices.
2194 */
a5dc05e4 2195static const struct snd_pci_quirk power_save_blacklist[] = {
1ba8f9d3 2196 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
8e82a728 2197 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
1ba8f9d3 2198 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
39070a98
HG		 2199 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2200 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
45e5fbc2
HG		 2201 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2202 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
1ba8f9d3 2203 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
b529ef24
HG		 2204 /* https://bugzilla.redhat.com/show_bug.cgi?id=1581607 */
2205 SND_PCI_QUIRK(0x1558, 0x3501, "Clevo W35xSS_370SS", 0),
38d9c12c 2206 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
d8feb608
HG		 2207 SND_PCI_QUIRK(0x1558, 0x6504, "Clevo W65_67SB", 0),
2208 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
5cb6b5fc
HG		 2209 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2210 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
38d9c12c
HG		 2211 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2212 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
5cb6b5fc
HG		 2213 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2214 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
f91f1806
HG		 2215 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2216 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
cae30527
HW		 2217 /* https://bugs.launchpad.net/bugs/1821663 */
2218 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
dd6dd536
HG		 2219 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2220 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
1ba8f9d3
HG		 2221 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2222 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
721f1e6c
JK		 2223 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2224 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2225 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2226 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
cae30527
HW		 2227 /* https://bugs.launchpad.net/bugs/1821663 */
2228 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
1ba8f9d3
HG		 2229 {}
2230};
2231#endif /* CONFIG_PM */
2232
37a3a98e
TI		 2233static void set_default_power_save(struct azx *chip)
2234{
2235 int val = power_save;
2236
2237#ifdef CONFIG_PM
2238 if (pm_blacklist) {
2239 const struct snd_pci_quirk *q;
2240
2241 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist);
2242 if (q && val) {
2243 dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n",
2244 q->subvendor, q->subdevice);
2245 val = 0;
2246 }
2247 }
2248#endif /* CONFIG_PM */
2249 snd_hda_set_power_save(&chip->bus, val * 1000);
2250}
2251
e62a42ae 2252/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
bf82326f 2253static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
e62a42ae
DR		 2254 [AZX_DRIVER_NVIDIA] = 8,
2255 [AZX_DRIVER_TERA] = 1,
2256};
2257
48c8b0eb 2258static int azx_probe_continue(struct azx *chip)
a82d51ed 2259{
9a34af4a 2260 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
98d8fc6c 2261 struct hdac_bus *bus = azx_bus(chip);
c67e2228 2262 struct pci_dev *pci = chip->pci;
a82d51ed
TI		 2263 int dev = chip->dev_index;
2264 int err;
2265
305a0ade 2266 to_hda_bus(bus)->bus_probing = 1;
a41d1224 2267 hda->probe_continued = 1;
795614dd 2268
fcc88d91 2269 /* bind with i915 if needed */
dba9b7b6 2270 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
98d8fc6c 2271 err = snd_hdac_i915_init(bus);
535115b5
TI		 2272 if (err < 0) {
2273 /* if the controller is bound only with HDMI/DP
2274 * (for HSW and BDW), we need to abort the probe;
2275 * for other chips, still continue probing as other
2276 * codecs can be on the same link.
2277 */
bed2e98e
TI		 2278 if (CONTROLLER_IN_GPU(pci)) {
2279 dev_err(chip->card->dev,
2280 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
535115b5 2281 goto out_free;
fcc88d91
TI		 2282 } else {
2283 /* don't bother any longer */
e454ff8e 2284 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
fcc88d91 2285 }
535115b5 2286 }
e454ff8e
TI		 2287
2288 /* HSW/BDW controllers need this power */
2289 if (CONTROLLER_IN_GPU(pci))
2290 hda->need_i915_power = 1;
fcc88d91
TI		 2291 }
2292
2293 /* Request display power well for the HDA controller or codec. For
2294 * Haswell/Broadwell, both the display HDA controller and codec need
2295 * this power. For other platforms, like Baytrail/Braswell, only the
2296 * display codec needs the power and it can be released after probe.
2297 */
4f799e73 2298 display_power(chip, true);
99a2008d 2299
5c90680e
TI		 2300 err = azx_first_init(chip);
2301 if (err < 0)
2302 goto out_free;
2303
2dca0bba
JK		 2304#ifdef CONFIG_SND_HDA_INPUT_BEEP
2305 chip->beep_mode = beep_mode[dev];
2306#endif
2307
1da177e4 2308 /* create codec instances */
9479e75f
TI		 2309 if (bus->codec_mask) {
2310 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2311 if (err < 0)
2312 goto out_free;
2313 }
96d2bd6e 2314
4ea6fbc8 2315#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab 2316 if (chip->fw) {
a41d1224 2317 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
4918cdab 2318 chip->fw->data);
4ea6fbc8
TI		 2319 if (err < 0)
2320 goto out_free;
e39ae856 2321#ifndef CONFIG_PM
4918cdab
TI		 2322 release_firmware(chip->fw); /* no longer needed */
2323 chip->fw = NULL;
e39ae856 2324#endif
4ea6fbc8
TI		 2325 }
2326#endif
9479e75f 2327 if (bus->codec_mask && !(probe_only[dev] & 1)) {
a1e21c90
TI		 2328 err = azx_codec_configure(chip);
2329 if (err < 0)
2330 goto out_free;
2331 }
1da177e4 2332
a82d51ed 2333 err = snd_card_register(chip->card);
41dda0fd
WF		 2334 if (err < 0)
2335 goto out_free;
1da177e4 2336
37a3a98e
TI		 2337 setup_vga_switcheroo_runtime_pm(chip);
2338
cb53c626 2339 chip->running = 1;
65fcd41d 2340 azx_add_card_list(chip);
07f4f97d 2341
37a3a98e 2342 set_default_power_save(chip);
07f4f97d 2343
3ba21113
RS		 2344 if (azx_has_pm_runtime(chip)) {
2345 pm_runtime_use_autosuspend(&pci->dev);
9a641848 2346 pm_runtime_allow(&pci->dev);
30ff5957 2347 pm_runtime_put_autosuspend(&pci->dev);
3ba21113 2348 }
1da177e4 2349
41dda0fd 2350out_free:
2393e755
TI		 2351 if (err < 0) {
2352 azx_free(chip);
2353 return err;
2354 }
2355
2356 if (!hda->need_i915_power)
029d92c2 2357 display_power(chip, false);
9a34af4a 2358 complete_all(&hda->probe_wait);
305a0ade 2359 to_hda_bus(bus)->bus_probing = 0;
2393e755 2360 return 0;
1da177e4
LT		 2361}
2362
e23e7a14 2363static void azx_remove(struct pci_dev *pci)
1da177e4 2364{
9121947d 2365 struct snd_card *card = pci_get_drvdata(pci);
991f86d7
TI		 2366 struct azx *chip;
2367 struct hda_intel *hda;
2368
2369 if (card) {
0b8c8219 2370 /* cancel the pending probing work */
991f86d7
TI		 2371 chip = card->private_data;
2372 hda = container_of(chip, struct hda_intel, chip);
ab949d51
TI		 2373 /* FIXME: below is an ugly workaround.
2374 * Both device_release_driver() and driver_probe_device()
2375 * take *both* the device's and its parent's lock before
2376 * calling the remove() and probe() callbacks. The codec
2377 * probe takes the locks of both the codec itself and its
2378 * parent, i.e. the PCI controller dev. Meanwhile, when
2379 * the PCI controller is unbound, it takes its lock, too
2380 * ==> ouch, a deadlock!
2381 * As a workaround, we unlock temporarily here the controller
2382 * device during cancel_work_sync() call.
2383 */
2384 device_unlock(&pci->dev);
0b8c8219 2385 cancel_work_sync(&hda->probe_work);
ab949d51 2386 device_lock(&pci->dev);
b8dfc462 2387
9121947d 2388 snd_card_free(card);
991f86d7 2389 }
1da177e4
LT		 2390}
2391
b2a0bafa
TI		 2392static void azx_shutdown(struct pci_dev *pci)
2393{
2394 struct snd_card *card = pci_get_drvdata(pci);
2395 struct azx *chip;
2396
2397 if (!card)
2398 return;
2399 chip = card->private_data;
2400 if (chip && chip->running)
2401 azx_stop_chip(chip);
2402}
2403
1da177e4 2404/* PCI IDs */
6f51f6cf 2405static const struct pci_device_id azx_ids[] = {
d2f2fcd2 2406 /* CPT */
9477c58e 2407 { PCI_DEVICE(0x8086, 0x1c20),
d7dab4db 2408 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
cea310e8 2409 /* PBG */
9477c58e 2410 { PCI_DEVICE(0x8086, 0x1d20),
d7dab4db 2411 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
d2edeb7c 2412 /* Panther Point */
9477c58e 2413 { PCI_DEVICE(0x8086, 0x1e20),
de5d0ad5 2414 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
8bc039a1
SH		 2415 /* Lynx Point */
2416 { PCI_DEVICE(0x8086, 0x8c20),
2ea3c6a2 2417 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
77f07800
TI		 2418 /* 9 Series */
2419 { PCI_DEVICE(0x8086, 0x8ca0),
2420 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
884b088f
JR		 2421 /* Wellsburg */
2422 { PCI_DEVICE(0x8086, 0x8d20),
2423 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2424 { PCI_DEVICE(0x8086, 0x8d21),
2425 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
5cf92c8b
AY		 2426 /* Lewisburg */
2427 { PCI_DEVICE(0x8086, 0xa1f0),
e7480b34 2428 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
5cf92c8b 2429 { PCI_DEVICE(0x8086, 0xa270),
e7480b34 2430 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
144dad99
JR		 2431 /* Lynx Point-LP */
2432 { PCI_DEVICE(0x8086, 0x9c20),
2ea3c6a2 2433 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 2434 /* Lynx Point-LP */
2435 { PCI_DEVICE(0x8086, 0x9c21),
2ea3c6a2 2436 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4eeca499
JR		 2437 /* Wildcat Point-LP */
2438 { PCI_DEVICE(0x8086, 0x9ca0),
2439 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
c8b00fd2
JR		 2440 /* Sunrise Point */
2441 { PCI_DEVICE(0x8086, 0xa170),
a4b4793f 2442 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
b4565913
DR		 2443 /* Sunrise Point-LP */
2444 { PCI_DEVICE(0x8086, 0x9d70),
3e9ad24b 2445 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
35639a0e
VK		 2446 /* Kabylake */
2447 { PCI_DEVICE(0x8086, 0xa171),
a4b4793f 2448 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
35639a0e
VK		 2449 /* Kabylake-LP */
2450 { PCI_DEVICE(0x8086, 0x9d71),
3e9ad24b 2451 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
6858107e
VK		 2452 /* Kabylake-H */
2453 { PCI_DEVICE(0x8086, 0xa2f0),
a4b4793f 2454 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
e79b0006
MD		 2455 /* Coffelake */
2456 { PCI_DEVICE(0x8086, 0xa348),
3e9ad24b 2457 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2357f6f0
GS		 2458 /* Cannonlake */
2459 { PCI_DEVICE(0x8086, 0x9dc8),
3e9ad24b 2460 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
d4c2ccdb
PLB		 2461 /* CometLake-LP */
2462 { PCI_DEVICE(0x8086, 0x02C8),
2463 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2464 /* CometLake-H */
2465 { PCI_DEVICE(0x8086, 0x06C8),
2466 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
b73a5854
CC		 2467 /* CometLake-S */
2468 { PCI_DEVICE(0x8086, 0xa3f0),
2469 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
491f8331
GS		 2470 /* Icelake */
2471 { PCI_DEVICE(0x8086, 0x34c8),
3e9ad24b 2472 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
4750c212
PX		 2473 /* Jasperlake */
2474 { PCI_DEVICE(0x8086, 0x38c8),
2475 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
78be2228
YZ		 2476 { PCI_DEVICE(0x8086, 0x4dc8),
2477 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
4750c212
PX		 2478 /* Tigerlake */
2479 { PCI_DEVICE(0x8086, 0xa0c8),
2480 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
f94287b6
LPS		 2481 /* Elkhart Lake */
2482 { PCI_DEVICE(0x8086, 0x4b55),
2483 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
c87693da
LH		 2484 /* Broxton-P(Apollolake) */
2485 { PCI_DEVICE(0x8086, 0x5a98),
3e9ad24b 2486 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
9859a971
LH		 2487 /* Broxton-T */
2488 { PCI_DEVICE(0x8086, 0x1a98),
a4b4793f 2489 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
44b46d73
VK		 2490 /* Gemini-Lake */
2491 { PCI_DEVICE(0x8086, 0x3198),
3e9ad24b 2492 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
e926f2c8 2493 /* Haswell */
4a7c516b 2494 { PCI_DEVICE(0x8086, 0x0a0c),
fab1285a 2495 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
e926f2c8 2496 { PCI_DEVICE(0x8086, 0x0c0c),
fab1285a 2497 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
d279fae8 2498 { PCI_DEVICE(0x8086, 0x0d0c),
fab1285a 2499 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
862d7618
ML		 2500 /* Broadwell */
2501 { PCI_DEVICE(0x8086, 0x160c),
54a0405d 2502 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
99df18b3
PLB		 2503 /* 5 Series/3400 */
2504 { PCI_DEVICE(0x8086, 0x3b56),
2c1350fd 2505 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
f748abcc 2506 /* Poulsbo */
9477c58e 2507 { PCI_DEVICE(0x8086, 0x811b),
6603249d 2508 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
f748abcc 2509 /* Oaktrail */
09904b95 2510 { PCI_DEVICE(0x8086, 0x080a),
6603249d 2511 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
e44007e0
CCE		 2512 /* BayTrail */
2513 { PCI_DEVICE(0x8086, 0x0f04),
40cc2392 2514 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
f31b2ffc
LY		 2515 /* Braswell */
2516 { PCI_DEVICE(0x8086, 0x2284),
2d846c74 2517 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
b42b4afb 2518 /* ICH6 */
8b0bd226 2519 { PCI_DEVICE(0x8086, 0x2668),
b42b4afb
TI		 2520 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2521 /* ICH7 */
8b0bd226 2522 { PCI_DEVICE(0x8086, 0x27d8),
b42b4afb
TI		 2523 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2524 /* ESB2 */
8b0bd226 2525 { PCI_DEVICE(0x8086, 0x269a),
b42b4afb
TI		 2526 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2527 /* ICH8 */
8b0bd226 2528 { PCI_DEVICE(0x8086, 0x284b),
b42b4afb
TI		 2529 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2530 /* ICH9 */
8b0bd226 2531 { PCI_DEVICE(0x8086, 0x293e),
b42b4afb
TI		 2532 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2533 /* ICH9 */
8b0bd226 2534 { PCI_DEVICE(0x8086, 0x293f),
b42b4afb
TI		 2535 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2536 /* ICH10 */
8b0bd226 2537 { PCI_DEVICE(0x8086, 0x3a3e),
b42b4afb
TI		 2538 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2539 /* ICH10 */
8b0bd226 2540 { PCI_DEVICE(0x8086, 0x3a6e),
b42b4afb 2541 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
b6864535
TI		 2542 /* Generic Intel */
2543 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2544 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2545 .class_mask = 0xffffff,
103884a3 2546 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
9477c58e
TI		 2547 /* ATI SB 450/600/700/800/900 */
2548 { PCI_DEVICE(0x1002, 0x437b),
2549 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2550 { PCI_DEVICE(0x1002, 0x4383),
2551 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2552 /* AMD Hudson */
2553 { PCI_DEVICE(0x1022, 0x780d),
2554 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
c02f77d3
TI		 2555 /* AMD, X370 & co */
2556 { PCI_DEVICE(0x1022, 0x1457),
2557 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
de768ce4
TI		 2558 /* AMD, X570 & co */
2559 { PCI_DEVICE(0x1022, 0x1487),
2560 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
3deef52c
KHF		 2561 /* AMD Stoney */
2562 { PCI_DEVICE(0x1022, 0x157a),
2563 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2564 AZX_DCAPS_PM_RUNTIME },
9ceace3c
VM		 2565 /* AMD Raven */
2566 { PCI_DEVICE(0x1022, 0x15e3),
d2c63b7d 2567 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
87218e9c 2568 /* ATI HDMI */
fd48331f
MSB		 2569 { PCI_DEVICE(0x1002, 0x0002),
2570 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
650474fb
AD		 2571 { PCI_DEVICE(0x1002, 0x1308),
2572 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2573 { PCI_DEVICE(0x1002, 0x157a),
2574 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
d716fb03
AB		 2575 { PCI_DEVICE(0x1002, 0x15b3),
2576 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
9477c58e
TI		 2577 { PCI_DEVICE(0x1002, 0x793b),
2578 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2579 { PCI_DEVICE(0x1002, 0x7919),
2580 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2581 { PCI_DEVICE(0x1002, 0x960f),
2582 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2583 { PCI_DEVICE(0x1002, 0x970f),
2584 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
650474fb
AD		 2585 { PCI_DEVICE(0x1002, 0x9840),
2586 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
9477c58e
TI		 2587 { PCI_DEVICE(0x1002, 0xaa00),
2588 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2589 { PCI_DEVICE(0x1002, 0xaa08),
2590 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2591 { PCI_DEVICE(0x1002, 0xaa10),
2592 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2593 { PCI_DEVICE(0x1002, 0xaa18),
2594 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2595 { PCI_DEVICE(0x1002, 0xaa20),
2596 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2597 { PCI_DEVICE(0x1002, 0xaa28),
2598 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2599 { PCI_DEVICE(0x1002, 0xaa30),
2600 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2601 { PCI_DEVICE(0x1002, 0xaa38),
2602 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2603 { PCI_DEVICE(0x1002, 0xaa40),
2604 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2605 { PCI_DEVICE(0x1002, 0xaa48),
2606 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
bbaa0d66
CL		 2607 { PCI_DEVICE(0x1002, 0xaa50),
2608 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2609 { PCI_DEVICE(0x1002, 0xaa58),
2610 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2611 { PCI_DEVICE(0x1002, 0xaa60),
2612 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2613 { PCI_DEVICE(0x1002, 0xaa68),
2614 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2615 { PCI_DEVICE(0x1002, 0xaa80),
2616 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2617 { PCI_DEVICE(0x1002, 0xaa88),
2618 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2619 { PCI_DEVICE(0x1002, 0xaa90),
2620 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2621 { PCI_DEVICE(0x1002, 0xaa98),
2622 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a 2623 { PCI_DEVICE(0x1002, 0x9902),
37e661ee 2624 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2625 { PCI_DEVICE(0x1002, 0xaaa0),
37e661ee 2626 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2627 { PCI_DEVICE(0x1002, 0xaaa8),
37e661ee 2628 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2629 { PCI_DEVICE(0x1002, 0xaab0),
37e661ee 2630 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2631 { PCI_DEVICE(0x1002, 0xaac0),
2632 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
0fa372b6
TI		 2633 { PCI_DEVICE(0x1002, 0xaac8),
2634 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d 2635 { PCI_DEVICE(0x1002, 0xaad8),
73b1422b
AD		 2636 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2637 AZX_DCAPS_PM_RUNTIME },
8eb22214 2638 { PCI_DEVICE(0x1002, 0xaae0),
73b1422b
AD		 2639 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2640 AZX_DCAPS_PM_RUNTIME },
2641 { PCI_DEVICE(0x1002, 0xaae8),
2642 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2643 AZX_DCAPS_PM_RUNTIME },
8eb22214 2644 { PCI_DEVICE(0x1002, 0xaaf0),
73b1422b
AD		 2645 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2646 AZX_DCAPS_PM_RUNTIME },
8d68a872 2647 { PCI_DEVICE(0x1002, 0xaaf8),
73b1422b
AD		 2648 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2649 AZX_DCAPS_PM_RUNTIME },
8d68a872 2650 { PCI_DEVICE(0x1002, 0xab00),
73b1422b
AD		 2651 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2652 AZX_DCAPS_PM_RUNTIME },
8d68a872 2653 { PCI_DEVICE(0x1002, 0xab08),
73b1422b
AD		 2654 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2655 AZX_DCAPS_PM_RUNTIME },
8d68a872 2656 { PCI_DEVICE(0x1002, 0xab10),
73b1422b
AD		 2657 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2658 AZX_DCAPS_PM_RUNTIME },
8d68a872 2659 { PCI_DEVICE(0x1002, 0xab18),
73b1422b
AD		 2660 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2661 AZX_DCAPS_PM_RUNTIME },
8d68a872 2662 { PCI_DEVICE(0x1002, 0xab20),
73b1422b
AD		 2663 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2664 AZX_DCAPS_PM_RUNTIME },
8d68a872 2665 { PCI_DEVICE(0x1002, 0xab38),
73b1422b
AD		 2666 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2667 AZX_DCAPS_PM_RUNTIME },
87218e9c 2668 /* VIA VT8251/VT8237A */
26f05717 2669 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
754fdff8
AL		 2670 /* VIA GFX VT7122/VX900 */
2671 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2672 /* VIA GFX VT6122/VX11 */
2673 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 2674 /* SIS966 */
2675 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2676 /* ULI M5461 */
2677 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2678 /* NVIDIA MCP */
0c2fd1bf
TI		 2679 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2680 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2681 .class_mask = 0xffffff,
9477c58e 2682 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 2683 /* Teradici */
9477c58e
TI		 2684 { PCI_DEVICE(0x6549, 0x1200),
2685 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 2686 { PCI_DEVICE(0x6549, 0x2200),
2687 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 2688 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 2689 /* CTHDA chips */
2690 { PCI_DEVICE(0x1102, 0x0010),
2691 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2692 { PCI_DEVICE(0x1102, 0x0012),
2693 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
8eeaa2f9 2694#if !IS_ENABLED(CONFIG_SND_CTXFI)
313f6e2d
TI		 2695 /* the following entry conflicts with snd-ctxfi driver,
2696 * as ctxfi driver mutates from HD-audio to native mode with
2697 * a special command sequence.
2698 */
4e01f54b
TI		 2699 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2700 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2701 .class_mask = 0xffffff,
9477c58e 2702 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
ef85f299 2703 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 2704#else
2705 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 2706 { PCI_DEVICE(0x1102, 0x0009),
2707 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
ef85f299 2708 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 2709#endif
c563f473
TI		 2710 /* CM8888 */
2711 { PCI_DEVICE(0x13f6, 0x5011),
2712 .driver_data = AZX_DRIVER_CMEDIA |
37e661ee 2713 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
e35d4b11
OS		 2714 /* Vortex86MX */
2715 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 2716 /* VMware HDAudio */
2717 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 2718 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 2719 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2720 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2721 .class_mask = 0xffffff,
9477c58e 2722 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 2723 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2724 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2725 .class_mask = 0xffffff,
9477c58e 2726 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
b6fcab14
TW		 2727 /* Zhaoxin */
2728 { PCI_DEVICE(0x1d17, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN },
1da177e4
LT		 2729 { 0, }
2730};
2731MODULE_DEVICE_TABLE(pci, azx_ids);
2732
2733/* pci_driver definition */
e9f66d9b 2734static struct pci_driver azx_driver = {
3733e424 2735 .name = KBUILD_MODNAME,
1da177e4
LT		 2736 .id_table = azx_ids,
2737 .probe = azx_probe,
e23e7a14 2738 .remove = azx_remove,
b2a0bafa 2739 .shutdown = azx_shutdown,
68cb2b55
TI		 2740 .driver = {
2741 .pm = AZX_PM_OPS,
2742 },
1da177e4
LT		 2743};
2744
e9f66d9b 2745module_pci_driver(azx_driver);
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