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Merge branch 'topic/alc28x' into for-next
[people/ms/linux.git] / sound / pci / hda / patch_hdmi.c
CommitLineData
079d88cc
WF		 1/*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
84eb01be
TI		 6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
5a613584 9 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
079d88cc
WF		 10 *
11 * Authors:
12 * Wu Fengguang <wfg@linux.intel.com>
13 *
14 * Maintained by:
15 * Wu Fengguang <wfg@linux.intel.com>
16 *
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the Free
19 * Software Foundation; either version 2 of the License, or (at your option)
20 * any later version.
21 *
22 * This program is distributed in the hope that it will be useful, but
23 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
24 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 * for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software Foundation,
29 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
84eb01be
TI		 32#include <linux/init.h>
33#include <linux/delay.h>
34#include <linux/slab.h>
65a77217 35#include <linux/module.h>
84eb01be 36#include <sound/core.h>
07acecc1 37#include <sound/jack.h>
433968da 38#include <sound/asoundef.h>
d45e6889 39#include <sound/tlv.h>
84eb01be
TI		 40#include "hda_codec.h"
41#include "hda_local.h"
1835a0f9 42#include "hda_jack.h"
84eb01be 43
0ebaa24c
TI		 44static bool static_hdmi_pcm;
45module_param(static_hdmi_pcm, bool, 0644);
46MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
47
fb87fa3a 48#define is_haswell(codec) ((codec)->vendor_id == 0x80862807)
75dcbe4d
ML		 49#define is_broadwell(codec) ((codec)->vendor_id == 0x80862808)
50#define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec))
51
02383854 52#define is_valleyview(codec) ((codec)->vendor_id == 0x80862882)
fb87fa3a 53
384a48d7
SW		 54struct hdmi_spec_per_cvt {
55 hda_nid_t cvt_nid;
56 int assigned;
57 unsigned int channels_min;
58 unsigned int channels_max;
59 u32 rates;
60 u64 formats;
61 unsigned int maxbps;
62};
079d88cc 63
4eea3091
TI		 64/* max. connections to a widget */
65#define HDA_MAX_CONNECTIONS 32
66
384a48d7
SW		 67struct hdmi_spec_per_pin {
68 hda_nid_t pin_nid;
69 int num_mux_nids;
70 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
1df5a06a 71 hda_nid_t cvt_nid;
744626da
WF		 72
73 struct hda_codec *codec;
384a48d7 74 struct hdmi_eld sink_eld;
a4e9a38b 75 struct mutex lock;
744626da 76 struct delayed_work work;
92c69e79 77 struct snd_kcontrol *eld_ctl;
c6e8453e 78 int repoll_count;
b054087d
TI		 79 bool setup; /* the stream has been set up by prepare callback */
80 int channels; /* current number of channels */
1a6003b5 81 bool non_pcm;
d45e6889
TI		 82 bool chmap_set; /* channel-map override by ALSA API? */
83 unsigned char chmap[8]; /* ALSA API channel-map */
bce0d2a8 84 char pcm_name[8]; /* filled in build_pcm callbacks */
a4e9a38b
TI		 85#ifdef CONFIG_PROC_FS
86 struct snd_info_entry *proc_entry;
87#endif
384a48d7 88};
079d88cc 89
307229d2
AH		 90struct cea_channel_speaker_allocation;
91
92/* operations used by generic code that can be overridden by patches */
93struct hdmi_ops {
94 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
95 unsigned char *buf, int *eld_size);
96
97 /* get and set channel assigned to each HDMI ASP (audio sample packet) slot */
98 int (*pin_get_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
99 int asp_slot);
100 int (*pin_set_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
101 int asp_slot, int channel);
102
103 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
104 int ca, int active_channels, int conn_type);
105
106 /* enable/disable HBR (HD passthrough) */
107 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
108
109 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
110 hda_nid_t pin_nid, u32 stream_tag, int format);
111
112 /* Helpers for producing the channel map TLVs. These can be overridden
113 * for devices that have non-standard mapping requirements. */
114 int (*chmap_cea_alloc_validate_get_type)(struct cea_channel_speaker_allocation *cap,
115 int channels);
116 void (*cea_alloc_to_tlv_chmap)(struct cea_channel_speaker_allocation *cap,
117 unsigned int *chmap, int channels);
118
119 /* check that the user-given chmap is supported */
120 int (*chmap_validate)(int ca, int channels, unsigned char *chmap);
121};
122
384a48d7
SW		 123struct hdmi_spec {
124 int num_cvts;
bce0d2a8
TI		 125 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
126 hda_nid_t cvt_nids[4]; /* only for haswell fix */
079d88cc 127
384a48d7 128 int num_pins;
bce0d2a8
TI		 129 struct snd_array pins; /* struct hdmi_spec_per_pin */
130 struct snd_array pcm_rec; /* struct hda_pcm */
d45e6889 131 unsigned int channels_max; /* max over all cvts */
079d88cc 132
4bd038f9 133 struct hdmi_eld temp_eld;
307229d2 134 struct hdmi_ops ops;
75fae117
SW		 135
136 bool dyn_pin_out;
137
079d88cc 138 /*
5a613584 139 * Non-generic VIA/NVIDIA specific
079d88cc
WF		 140 */
141 struct hda_multi_out multiout;
d0b1252d 142 struct hda_pcm_stream pcm_playback;
079d88cc
WF		 143};
144
145
146struct hdmi_audio_infoframe {
147 u8 type; /* 0x84 */
148 u8 ver; /* 0x01 */
149 u8 len; /* 0x0a */
150
53d7d69d
WF		 151 u8 checksum;
152
079d88cc
WF		 153 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
154 u8 SS01_SF24;
155 u8 CXT04;
156 u8 CA;
157 u8 LFEPBL01_LSV36_DM_INH7;
53d7d69d
WF		 158};
159
160struct dp_audio_infoframe {
161 u8 type; /* 0x84 */
162 u8 len; /* 0x1b */
163 u8 ver; /* 0x11 << 2 */
164
165 u8 CC02_CT47; /* match with HDMI infoframe from this on */
166 u8 SS01_SF24;
167 u8 CXT04;
168 u8 CA;
169 u8 LFEPBL01_LSV36_DM_INH7;
079d88cc
WF		 170};
171
2b203dbb
TI		 172union audio_infoframe {
173 struct hdmi_audio_infoframe hdmi;
174 struct dp_audio_infoframe dp;
175 u8 bytes[0];
176};
177
079d88cc
WF		 178/*
179 * CEA speaker placement:
180 *
181 * FLH FCH FRH
182 * FLW FL FLC FC FRC FR FRW
183 *
184 * LFE
185 * TC
186 *
187 * RL RLC RC RRC RR
188 *
189 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
190 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
191 */
192enum cea_speaker_placement {
193 FL = (1 << 0), /* Front Left */
194 FC = (1 << 1), /* Front Center */
195 FR = (1 << 2), /* Front Right */
196 FLC = (1 << 3), /* Front Left Center */
197 FRC = (1 << 4), /* Front Right Center */
198 RL = (1 << 5), /* Rear Left */
199 RC = (1 << 6), /* Rear Center */
200 RR = (1 << 7), /* Rear Right */
201 RLC = (1 << 8), /* Rear Left Center */
202 RRC = (1 << 9), /* Rear Right Center */
203 LFE = (1 << 10), /* Low Frequency Effect */
204 FLW = (1 << 11), /* Front Left Wide */
205 FRW = (1 << 12), /* Front Right Wide */
206 FLH = (1 << 13), /* Front Left High */
207 FCH = (1 << 14), /* Front Center High */
208 FRH = (1 << 15), /* Front Right High */
209 TC = (1 << 16), /* Top Center */
210};
211
212/*
213 * ELD SA bits in the CEA Speaker Allocation data block
214 */
215static int eld_speaker_allocation_bits[] = {
216 [0] = FL | FR,
217 [1] = LFE,
218 [2] = FC,
219 [3] = RL | RR,
220 [4] = RC,
221 [5] = FLC | FRC,
222 [6] = RLC | RRC,
223 /* the following are not defined in ELD yet */
224 [7] = FLW | FRW,
225 [8] = FLH | FRH,
226 [9] = TC,
227 [10] = FCH,
228};
229
230struct cea_channel_speaker_allocation {
231 int ca_index;
232 int speakers[8];
233
234 /* derived values, just for convenience */
235 int channels;
236 int spk_mask;
237};
238
239/*
240 * ALSA sequence is:
241 *
242 * surround40 surround41 surround50 surround51 surround71
243 * ch0 front left = = = =
244 * ch1 front right = = = =
245 * ch2 rear left = = = =
246 * ch3 rear right = = = =
247 * ch4 LFE center center center
248 * ch5 LFE LFE
249 * ch6 side left
250 * ch7 side right
251 *
252 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
253 */
254static int hdmi_channel_mapping[0x32][8] = {
255 /* stereo */
256 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
257 /* 2.1 */
258 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
259 /* Dolby Surround */
260 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
261 /* surround40 */
262 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
263 /* 4ch */
264 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
265 /* surround41 */
9396d317 266 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
079d88cc
WF		 267 /* surround50 */
268 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
269 /* surround51 */
270 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
271 /* 7.1 */
272 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
273};
274
275/*
276 * This is an ordered list!
277 *
278 * The preceding ones have better chances to be selected by
53d7d69d 279 * hdmi_channel_allocation().
079d88cc
WF		 280 */
281static struct cea_channel_speaker_allocation channel_allocations[] = {
282/* channel: 7 6 5 4 3 2 1 0 */
283{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
284 /* 2.1 */
285{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
286 /* Dolby Surround */
287{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
288 /* surround40 */
289{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
290 /* surround41 */
291{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
292 /* surround50 */
293{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
294 /* surround51 */
295{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
296 /* 6.1 */
297{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
298 /* surround71 */
299{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
300
301{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
302{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
303{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
304{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
305{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
306{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
307{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
308{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
309{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
310{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
311{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
312{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
313{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
314{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
315{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
316{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
317{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
318{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
319{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
320{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
321{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
322{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
323{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
324{ .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
325{ .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
326{ .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
327{ .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
328{ .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
329{ .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
330{ .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
331{ .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
332{ .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
333{ .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
334{ .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
335{ .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
336{ .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
337{ .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
338{ .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
339{ .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
340{ .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
341{ .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
342};
343
344
345/*
346 * HDMI routines
347 */
348
bce0d2a8
TI		 349#define get_pin(spec, idx) \
350 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
351#define get_cvt(spec, idx) \
352 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
353#define get_pcm_rec(spec, idx) \
354 ((struct hda_pcm *)snd_array_elem(&spec->pcm_rec, idx))
355
4e76a883 356static int pin_nid_to_pin_index(struct hda_codec *codec, hda_nid_t pin_nid)
079d88cc 357{
4e76a883 358 struct hdmi_spec *spec = codec->spec;
384a48d7 359 int pin_idx;
079d88cc 360
384a48d7 361 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
bce0d2a8 362 if (get_pin(spec, pin_idx)->pin_nid == pin_nid)
384a48d7 363 return pin_idx;
079d88cc 364
4e76a883 365 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
384a48d7
SW		 366 return -EINVAL;
367}
368
4e76a883 369static int hinfo_to_pin_index(struct hda_codec *codec,
384a48d7
SW		 370 struct hda_pcm_stream *hinfo)
371{
4e76a883 372 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 373 int pin_idx;
374
375 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
bce0d2a8 376 if (get_pcm_rec(spec, pin_idx)->stream == hinfo)
384a48d7
SW		 377 return pin_idx;
378
4e76a883 379 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
384a48d7
SW		 380 return -EINVAL;
381}
382
4e76a883 383static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
384a48d7 384{
4e76a883 385 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 386 int cvt_idx;
387
388 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
bce0d2a8 389 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
384a48d7
SW		 390 return cvt_idx;
391
4e76a883 392 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
079d88cc
WF		 393 return -EINVAL;
394}
395
14bc52b8
PLB		 396static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
397 struct snd_ctl_elem_info *uinfo)
398{
399 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9 400 struct hdmi_spec *spec = codec->spec;
a4e9a38b 401 struct hdmi_spec_per_pin *per_pin;
68e03de9 402 struct hdmi_eld *eld;
14bc52b8
PLB		 403 int pin_idx;
404
14bc52b8
PLB		 405 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
406
407 pin_idx = kcontrol->private_value;
a4e9a38b
TI		 408 per_pin = get_pin(spec, pin_idx);
409 eld = &per_pin->sink_eld;
68e03de9 410
a4e9a38b 411 mutex_lock(&per_pin->lock);
68e03de9 412 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
a4e9a38b 413 mutex_unlock(&per_pin->lock);
14bc52b8
PLB		 414
415 return 0;
416}
417
418static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
419 struct snd_ctl_elem_value *ucontrol)
420{
421 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9 422 struct hdmi_spec *spec = codec->spec;
a4e9a38b 423 struct hdmi_spec_per_pin *per_pin;
68e03de9 424 struct hdmi_eld *eld;
14bc52b8
PLB		 425 int pin_idx;
426
14bc52b8 427 pin_idx = kcontrol->private_value;
a4e9a38b
TI		 428 per_pin = get_pin(spec, pin_idx);
429 eld = &per_pin->sink_eld;
68e03de9 430
a4e9a38b 431 mutex_lock(&per_pin->lock);
68e03de9 432 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data)) {
a4e9a38b 433 mutex_unlock(&per_pin->lock);
68e03de9
DH		 434 snd_BUG();
435 return -EINVAL;
436 }
437
438 memset(ucontrol->value.bytes.data, 0,
439 ARRAY_SIZE(ucontrol->value.bytes.data));
440 if (eld->eld_valid)
441 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
442 eld->eld_size);
a4e9a38b 443 mutex_unlock(&per_pin->lock);
14bc52b8
PLB		 444
445 return 0;
446}
447
448static struct snd_kcontrol_new eld_bytes_ctl = {
449 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
450 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
451 .name = "ELD",
452 .info = hdmi_eld_ctl_info,
453 .get = hdmi_eld_ctl_get,
454};
455
456static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
457 int device)
458{
459 struct snd_kcontrol *kctl;
460 struct hdmi_spec *spec = codec->spec;
461 int err;
462
463 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
464 if (!kctl)
465 return -ENOMEM;
466 kctl->private_value = pin_idx;
467 kctl->id.device = device;
468
bce0d2a8 469 err = snd_hda_ctl_add(codec, get_pin(spec, pin_idx)->pin_nid, kctl);
14bc52b8
PLB		 470 if (err < 0)
471 return err;
472
bce0d2a8 473 get_pin(spec, pin_idx)->eld_ctl = kctl;
14bc52b8
PLB		 474 return 0;
475}
476
079d88cc
WF		 477#ifdef BE_PARANOID
478static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
479 int *packet_index, int *byte_index)
480{
481 int val;
482
483 val = snd_hda_codec_read(codec, pin_nid, 0,
484 AC_VERB_GET_HDMI_DIP_INDEX, 0);
485
486 *packet_index = val >> 5;
487 *byte_index = val & 0x1f;
488}
489#endif
490
491static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
492 int packet_index, int byte_index)
493{
494 int val;
495
496 val = (packet_index << 5) | (byte_index & 0x1f);
497
498 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
499}
500
501static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
502 unsigned char val)
503{
504 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
505}
506
384a48d7 507static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
079d88cc 508{
75fae117
SW		 509 struct hdmi_spec *spec = codec->spec;
510 int pin_out;
511
079d88cc
WF		 512 /* Unmute */
513 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
514 snd_hda_codec_write(codec, pin_nid, 0,
515 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
75fae117
SW		 516
517 if (spec->dyn_pin_out)
518 /* Disable pin out until stream is active */
519 pin_out = 0;
520 else
521 /* Enable pin out: some machines with GM965 gets broken output
522 * when the pin is disabled or changed while using with HDMI
523 */
524 pin_out = PIN_OUT;
525
079d88cc 526 snd_hda_codec_write(codec, pin_nid, 0,
75fae117 527 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
079d88cc
WF		 528}
529
384a48d7 530static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc 531{
384a48d7 532 return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
079d88cc
WF		 533 AC_VERB_GET_CVT_CHAN_COUNT, 0);
534}
535
536static void hdmi_set_channel_count(struct hda_codec *codec,
384a48d7 537 hda_nid_t cvt_nid, int chs)
079d88cc 538{
384a48d7
SW		 539 if (chs != hdmi_get_channel_count(codec, cvt_nid))
540 snd_hda_codec_write(codec, cvt_nid, 0,
079d88cc
WF		 541 AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
542}
543
a4e9a38b
TI		 544/*
545 * ELD proc files
546 */
547
548#ifdef CONFIG_PROC_FS
549static void print_eld_info(struct snd_info_entry *entry,
550 struct snd_info_buffer *buffer)
551{
552 struct hdmi_spec_per_pin *per_pin = entry->private_data;
553
554 mutex_lock(&per_pin->lock);
555 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
556 mutex_unlock(&per_pin->lock);
557}
558
559static void write_eld_info(struct snd_info_entry *entry,
560 struct snd_info_buffer *buffer)
561{
562 struct hdmi_spec_per_pin *per_pin = entry->private_data;
563
564 mutex_lock(&per_pin->lock);
565 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
566 mutex_unlock(&per_pin->lock);
567}
568
569static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
570{
571 char name[32];
572 struct hda_codec *codec = per_pin->codec;
573 struct snd_info_entry *entry;
574 int err;
575
576 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
577 err = snd_card_proc_new(codec->bus->card, name, &entry);
578 if (err < 0)
579 return err;
580
581 snd_info_set_text_ops(entry, per_pin, print_eld_info);
582 entry->c.text.write = write_eld_info;
583 entry->mode |= S_IWUSR;
584 per_pin->proc_entry = entry;
585
586 return 0;
587}
588
589static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
590{
591 if (!per_pin->codec->bus->shutdown && per_pin->proc_entry) {
592 snd_device_free(per_pin->codec->bus->card, per_pin->proc_entry);
593 per_pin->proc_entry = NULL;
594 }
595}
596#else
b55447a7
TI		 597static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
598 int index)
a4e9a38b
TI		 599{
600 return 0;
601}
b55447a7 602static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
a4e9a38b
TI		 603{
604}
605#endif
079d88cc
WF		 606
607/*
608 * Channel mapping routines
609 */
610
611/*
612 * Compute derived values in channel_allocations[].
613 */
614static void init_channel_allocations(void)
615{
616 int i, j;
617 struct cea_channel_speaker_allocation *p;
618
619 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
620 p = channel_allocations + i;
621 p->channels = 0;
622 p->spk_mask = 0;
623 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
624 if (p->speakers[j]) {
625 p->channels++;
626 p->spk_mask |= p->speakers[j];
627 }
628 }
629}
630
72357c78
WX		 631static int get_channel_allocation_order(int ca)
632{
633 int i;
634
635 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
636 if (channel_allocations[i].ca_index == ca)
637 break;
638 }
639 return i;
640}
641
079d88cc
WF		 642/*
643 * The transformation takes two steps:
644 *
645 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
646 * spk_mask => (channel_allocations[]) => ai->CA
647 *
648 * TODO: it could select the wrong CA from multiple candidates.
649*/
384a48d7 650static int hdmi_channel_allocation(struct hdmi_eld *eld, int channels)
079d88cc 651{
079d88cc 652 int i;
53d7d69d 653 int ca = 0;
079d88cc 654 int spk_mask = 0;
079d88cc
WF		 655 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
656
657 /*
658 * CA defaults to 0 for basic stereo audio
659 */
660 if (channels <= 2)
661 return 0;
662
079d88cc
WF		 663 /*
664 * expand ELD's speaker allocation mask
665 *
666 * ELD tells the speaker mask in a compact(paired) form,
667 * expand ELD's notions to match the ones used by Audio InfoFrame.
668 */
669 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
1613d6b4 670 if (eld->info.spk_alloc & (1 << i))
079d88cc
WF		 671 spk_mask |= eld_speaker_allocation_bits[i];
672 }
673
674 /* search for the first working match in the CA table */
675 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
676 if (channels == channel_allocations[i].channels &&
677 (spk_mask & channel_allocations[i].spk_mask) ==
678 channel_allocations[i].spk_mask) {
53d7d69d 679 ca = channel_allocations[i].ca_index;
079d88cc
WF		 680 break;
681 }
682 }
683
18e39186
AH		 684 if (!ca) {
685 /* if there was no match, select the regular ALSA channel
686 * allocation with the matching number of channels */
687 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
688 if (channels == channel_allocations[i].channels) {
689 ca = channel_allocations[i].ca_index;
690 break;
691 }
692 }
693 }
694
1613d6b4 695 snd_print_channel_allocation(eld->info.spk_alloc, buf, sizeof(buf));
2abbf439 696 snd_printdd("HDMI: select CA 0x%x for %d-channel allocation: %s\n",
53d7d69d 697 ca, channels, buf);
079d88cc 698
53d7d69d 699 return ca;
079d88cc
WF		 700}
701
702static void hdmi_debug_channel_mapping(struct hda_codec *codec,
703 hda_nid_t pin_nid)
704{
705#ifdef CONFIG_SND_DEBUG_VERBOSE
307229d2 706 struct hdmi_spec *spec = codec->spec;
079d88cc 707 int i;
307229d2 708 int channel;
079d88cc
WF		 709
710 for (i = 0; i < 8; i++) {
307229d2 711 channel = spec->ops.pin_get_slot_channel(codec, pin_nid, i);
4e76a883 712 codec_dbg(codec, "HDMI: ASP channel %d => slot %d\n",
307229d2 713 channel, i);
079d88cc
WF		 714 }
715#endif
716}
717
d45e6889 718static void hdmi_std_setup_channel_mapping(struct hda_codec *codec,
079d88cc 719 hda_nid_t pin_nid,
433968da 720 bool non_pcm,
53d7d69d 721 int ca)
079d88cc 722{
307229d2 723 struct hdmi_spec *spec = codec->spec;
90f28002 724 struct cea_channel_speaker_allocation *ch_alloc;
079d88cc 725 int i;
079d88cc 726 int err;
72357c78 727 int order;
433968da 728 int non_pcm_mapping[8];
079d88cc 729
72357c78 730 order = get_channel_allocation_order(ca);
90f28002 731 ch_alloc = &channel_allocations[order];
433968da 732
079d88cc 733 if (hdmi_channel_mapping[ca][1] == 0) {
90f28002
AH		 734 int hdmi_slot = 0;
735 /* fill actual channel mappings in ALSA channel (i) order */
736 for (i = 0; i < ch_alloc->channels; i++) {
737 while (!ch_alloc->speakers[7 - hdmi_slot] && !WARN_ON(hdmi_slot >= 8))
738 hdmi_slot++; /* skip zero slots */
739
740 hdmi_channel_mapping[ca][i] = (i << 4) | hdmi_slot++;
741 }
742 /* fill the rest of the slots with ALSA channel 0xf */
743 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++)
744 if (!ch_alloc->speakers[7 - hdmi_slot])
745 hdmi_channel_mapping[ca][i++] = (0xf << 4) | hdmi_slot;
079d88cc
WF		 746 }
747
433968da 748 if (non_pcm) {
90f28002 749 for (i = 0; i < ch_alloc->channels; i++)
11f7c52d 750 non_pcm_mapping[i] = (i << 4) | i;
433968da 751 for (; i < 8; i++)
11f7c52d 752 non_pcm_mapping[i] = (0xf << 4) | i;
433968da
WX		 753 }
754
079d88cc 755 for (i = 0; i < 8; i++) {
307229d2
AH		 756 int slotsetup = non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i];
757 int hdmi_slot = slotsetup & 0x0f;
758 int channel = (slotsetup & 0xf0) >> 4;
759 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot, channel);
079d88cc 760 if (err) {
4e76a883 761 codec_dbg(codec, "HDMI: channel mapping failed\n");
079d88cc
WF		 762 break;
763 }
764 }
079d88cc
WF		 765}
766
d45e6889
TI		 767struct channel_map_table {
768 unsigned char map; /* ALSA API channel map position */
d45e6889
TI		 769 int spk_mask; /* speaker position bit mask */
770};
771
772static struct channel_map_table map_tables[] = {
a5b7d510
AH		 773 { SNDRV_CHMAP_FL, FL },
774 { SNDRV_CHMAP_FR, FR },
775 { SNDRV_CHMAP_RL, RL },
776 { SNDRV_CHMAP_RR, RR },
777 { SNDRV_CHMAP_LFE, LFE },
778 { SNDRV_CHMAP_FC, FC },
779 { SNDRV_CHMAP_RLC, RLC },
780 { SNDRV_CHMAP_RRC, RRC },
781 { SNDRV_CHMAP_RC, RC },
782 { SNDRV_CHMAP_FLC, FLC },
783 { SNDRV_CHMAP_FRC, FRC },
94908a39
AH		 784 { SNDRV_CHMAP_TFL, FLH },
785 { SNDRV_CHMAP_TFR, FRH },
a5b7d510
AH		 786 { SNDRV_CHMAP_FLW, FLW },
787 { SNDRV_CHMAP_FRW, FRW },
788 { SNDRV_CHMAP_TC, TC },
94908a39 789 { SNDRV_CHMAP_TFC, FCH },
d45e6889
TI		 790 {} /* terminator */
791};
792
793/* from ALSA API channel position to speaker bit mask */
794static int to_spk_mask(unsigned char c)
795{
796 struct channel_map_table *t = map_tables;
797 for (; t->map; t++) {
798 if (t->map == c)
799 return t->spk_mask;
800 }
801 return 0;
802}
803
804/* from ALSA API channel position to CEA slot */
a5b7d510 805static int to_cea_slot(int ordered_ca, unsigned char pos)
d45e6889 806{
a5b7d510
AH		 807 int mask = to_spk_mask(pos);
808 int i;
d45e6889 809
a5b7d510
AH		 810 if (mask) {
811 for (i = 0; i < 8; i++) {
812 if (channel_allocations[ordered_ca].speakers[7 - i] == mask)
813 return i;
814 }
d45e6889 815 }
a5b7d510
AH		 816
817 return -1;
d45e6889
TI		 818}
819
820/* from speaker bit mask to ALSA API channel position */
821static int spk_to_chmap(int spk)
822{
823 struct channel_map_table *t = map_tables;
824 for (; t->map; t++) {
825 if (t->spk_mask == spk)
826 return t->map;
827 }
828 return 0;
829}
830
a5b7d510
AH		 831/* from CEA slot to ALSA API channel position */
832static int from_cea_slot(int ordered_ca, unsigned char slot)
833{
834 int mask = channel_allocations[ordered_ca].speakers[7 - slot];
835
836 return spk_to_chmap(mask);
837}
838
d45e6889
TI		 839/* get the CA index corresponding to the given ALSA API channel map */
840static int hdmi_manual_channel_allocation(int chs, unsigned char *map)
841{
842 int i, spks = 0, spk_mask = 0;
843
844 for (i = 0; i < chs; i++) {
845 int mask = to_spk_mask(map[i]);
846 if (mask) {
847 spk_mask |= mask;
848 spks++;
849 }
850 }
851
852 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
853 if ((chs == channel_allocations[i].channels ||
854 spks == channel_allocations[i].channels) &&
855 (spk_mask & channel_allocations[i].spk_mask) ==
856 channel_allocations[i].spk_mask)
857 return channel_allocations[i].ca_index;
858 }
859 return -1;
860}
861
862/* set up the channel slots for the given ALSA API channel map */
863static int hdmi_manual_setup_channel_mapping(struct hda_codec *codec,
864 hda_nid_t pin_nid,
a5b7d510
AH		 865 int chs, unsigned char *map,
866 int ca)
d45e6889 867{
307229d2 868 struct hdmi_spec *spec = codec->spec;
a5b7d510 869 int ordered_ca = get_channel_allocation_order(ca);
11f7c52d
AH		 870 int alsa_pos, hdmi_slot;
871 int assignments[8] = {[0 ... 7] = 0xf};
872
873 for (alsa_pos = 0; alsa_pos < chs; alsa_pos++) {
874
a5b7d510 875 hdmi_slot = to_cea_slot(ordered_ca, map[alsa_pos]);
11f7c52d
AH		 876
877 if (hdmi_slot < 0)
878 continue; /* unassigned channel */
879
880 assignments[hdmi_slot] = alsa_pos;
881 }
882
883 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++) {
307229d2 884 int err;
11f7c52d 885
307229d2
AH		 886 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot,
887 assignments[hdmi_slot]);
d45e6889
TI		 888 if (err)
889 return -EINVAL;
890 }
891 return 0;
892}
893
894/* store ALSA API channel map from the current default map */
895static void hdmi_setup_fake_chmap(unsigned char *map, int ca)
896{
897 int i;
56cac413 898 int ordered_ca = get_channel_allocation_order(ca);
d45e6889 899 for (i = 0; i < 8; i++) {
56cac413 900 if (i < channel_allocations[ordered_ca].channels)
a5b7d510 901 map[i] = from_cea_slot(ordered_ca, hdmi_channel_mapping[ca][i] & 0x0f);
d45e6889
TI		 902 else
903 map[i] = 0;
904 }
905}
906
907static void hdmi_setup_channel_mapping(struct hda_codec *codec,
908 hda_nid_t pin_nid, bool non_pcm, int ca,
20608731
AH		 909 int channels, unsigned char *map,
910 bool chmap_set)
d45e6889 911{
20608731 912 if (!non_pcm && chmap_set) {
d45e6889 913 hdmi_manual_setup_channel_mapping(codec, pin_nid,
a5b7d510 914 channels, map, ca);
d45e6889
TI		 915 } else {
916 hdmi_std_setup_channel_mapping(codec, pin_nid, non_pcm, ca);
917 hdmi_setup_fake_chmap(map, ca);
918 }
980b2495
AH		 919
920 hdmi_debug_channel_mapping(codec, pin_nid);
d45e6889 921}
079d88cc 922
307229d2
AH		 923static int hdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
924 int asp_slot, int channel)
925{
926 return snd_hda_codec_write(codec, pin_nid, 0,
927 AC_VERB_SET_HDMI_CHAN_SLOT,
928 (channel << 4) | asp_slot);
929}
930
931static int hdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
932 int asp_slot)
933{
934 return (snd_hda_codec_read(codec, pin_nid, 0,
935 AC_VERB_GET_HDMI_CHAN_SLOT,
936 asp_slot) & 0xf0) >> 4;
937}
938
079d88cc
WF		 939/*
940 * Audio InfoFrame routines
941 */
942
943/*
944 * Enable Audio InfoFrame Transmission
945 */
946static void hdmi_start_infoframe_trans(struct hda_codec *codec,
947 hda_nid_t pin_nid)
948{
949 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
950 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
951 AC_DIPXMIT_BEST);
952}
953
954/*
955 * Disable Audio InfoFrame Transmission
956 */
957static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
958 hda_nid_t pin_nid)
959{
960 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
961 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
962 AC_DIPXMIT_DISABLE);
963}
964
965static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
966{
967#ifdef CONFIG_SND_DEBUG_VERBOSE
968 int i;
969 int size;
970
971 size = snd_hdmi_get_eld_size(codec, pin_nid);
4e76a883 972 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
079d88cc
WF		 973
974 for (i = 0; i < 8; i++) {
975 size = snd_hda_codec_read(codec, pin_nid, 0,
976 AC_VERB_GET_HDMI_DIP_SIZE, i);
4e76a883 977 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
079d88cc
WF		 978 }
979#endif
980}
981
982static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
983{
984#ifdef BE_PARANOID
985 int i, j;
986 int size;
987 int pi, bi;
988 for (i = 0; i < 8; i++) {
989 size = snd_hda_codec_read(codec, pin_nid, 0,
990 AC_VERB_GET_HDMI_DIP_SIZE, i);
991 if (size == 0)
992 continue;
993
994 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
995 for (j = 1; j < 1000; j++) {
996 hdmi_write_dip_byte(codec, pin_nid, 0x0);
997 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
998 if (pi != i)
4e76a883 999 codec_dbg(codec, "dip index %d: %d != %d\n",
079d88cc
WF		 1000 bi, pi, i);
1001 if (bi == 0) /* byte index wrapped around */
1002 break;
1003 }
4e76a883 1004 codec_dbg(codec,
079d88cc
WF		 1005 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
1006 i, size, j);
1007 }
1008#endif
1009}
1010
53d7d69d 1011static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
079d88cc 1012{
53d7d69d 1013 u8 *bytes = (u8 *)hdmi_ai;
079d88cc
WF		 1014 u8 sum = 0;
1015 int i;
1016
53d7d69d 1017 hdmi_ai->checksum = 0;
079d88cc 1018
53d7d69d 1019 for (i = 0; i < sizeof(*hdmi_ai); i++)
079d88cc
WF		 1020 sum += bytes[i];
1021
53d7d69d 1022 hdmi_ai->checksum = -sum;
079d88cc
WF		 1023}
1024
1025static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
1026 hda_nid_t pin_nid,
53d7d69d 1027 u8 *dip, int size)
079d88cc 1028{
079d88cc
WF		 1029 int i;
1030
1031 hdmi_debug_dip_size(codec, pin_nid);
1032 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
1033
079d88cc 1034 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d
WF		 1035 for (i = 0; i < size; i++)
1036 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
079d88cc
WF		 1037}
1038
1039static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
53d7d69d 1040 u8 *dip, int size)
079d88cc 1041{
079d88cc
WF		 1042 u8 val;
1043 int i;
1044
1045 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
1046 != AC_DIPXMIT_BEST)
1047 return false;
1048
1049 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d 1050 for (i = 0; i < size; i++) {
079d88cc
WF		 1051 val = snd_hda_codec_read(codec, pin_nid, 0,
1052 AC_VERB_GET_HDMI_DIP_DATA, 0);
53d7d69d 1053 if (val != dip[i])
079d88cc
WF		 1054 return false;
1055 }
1056
1057 return true;
1058}
1059
307229d2
AH		 1060static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
1061 hda_nid_t pin_nid,
1062 int ca, int active_channels,
1063 int conn_type)
1064{
1065 union audio_infoframe ai;
1066
caaf5ef9 1067 memset(&ai, 0, sizeof(ai));
307229d2
AH		 1068 if (conn_type == 0) { /* HDMI */
1069 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
1070
1071 hdmi_ai->type = 0x84;
1072 hdmi_ai->ver = 0x01;
1073 hdmi_ai->len = 0x0a;
1074 hdmi_ai->CC02_CT47 = active_channels - 1;
1075 hdmi_ai->CA = ca;
1076 hdmi_checksum_audio_infoframe(hdmi_ai);
1077 } else if (conn_type == 1) { /* DisplayPort */
1078 struct dp_audio_infoframe *dp_ai = &ai.dp;
1079
1080 dp_ai->type = 0x84;
1081 dp_ai->len = 0x1b;
1082 dp_ai->ver = 0x11 << 2;
1083 dp_ai->CC02_CT47 = active_channels - 1;
1084 dp_ai->CA = ca;
1085 } else {
4e76a883 1086 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
307229d2
AH		 1087 pin_nid);
1088 return;
1089 }
1090
1091 /*
1092 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
1093 * sizeof(*dp_ai) to avoid partial match/update problems when
1094 * the user switches between HDMI/DP monitors.
1095 */
1096 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
1097 sizeof(ai))) {
4e76a883
TI		 1098 codec_dbg(codec,
1099 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
307229d2
AH		 1100 pin_nid,
1101 active_channels, ca);
1102 hdmi_stop_infoframe_trans(codec, pin_nid);
1103 hdmi_fill_audio_infoframe(codec, pin_nid,
1104 ai.bytes, sizeof(ai));
1105 hdmi_start_infoframe_trans(codec, pin_nid);
1106 }
1107}
1108
b054087d
TI		 1109static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
1110 struct hdmi_spec_per_pin *per_pin,
1111 bool non_pcm)
079d88cc 1112{
307229d2 1113 struct hdmi_spec *spec = codec->spec;
384a48d7 1114 hda_nid_t pin_nid = per_pin->pin_nid;
b054087d 1115 int channels = per_pin->channels;
1df5a06a 1116 int active_channels;
384a48d7 1117 struct hdmi_eld *eld;
1df5a06a 1118 int ca, ordered_ca;
079d88cc 1119
b054087d
TI		 1120 if (!channels)
1121 return;
1122
75dcbe4d 1123 if (is_haswell_plus(codec))
58f7d28d
ML		 1124 snd_hda_codec_write(codec, pin_nid, 0,
1125 AC_VERB_SET_AMP_GAIN_MUTE,
1126 AMP_OUT_UNMUTE);
1127
bce0d2a8 1128 eld = &per_pin->sink_eld;
384a48d7
SW		 1129 if (!eld->monitor_present)
1130 return;
079d88cc 1131
d45e6889
TI		 1132 if (!non_pcm && per_pin->chmap_set)
1133 ca = hdmi_manual_channel_allocation(channels, per_pin->chmap);
1134 else
1135 ca = hdmi_channel_allocation(eld, channels);
1136 if (ca < 0)
1137 ca = 0;
384a48d7 1138
1df5a06a
AH		 1139 ordered_ca = get_channel_allocation_order(ca);
1140 active_channels = channel_allocations[ordered_ca].channels;
1141
1142 hdmi_set_channel_count(codec, per_pin->cvt_nid, active_channels);
1143
39edac70
AH		 1144 /*
1145 * always configure channel mapping, it may have been changed by the
1146 * user in the meantime
1147 */
1148 hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
1149 channels, per_pin->chmap,
1150 per_pin->chmap_set);
1151
307229d2
AH		 1152 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
1153 eld->info.conn_type);
433968da 1154
1a6003b5 1155 per_pin->non_pcm = non_pcm;
079d88cc
WF		 1156}
1157
079d88cc
WF		 1158/*
1159 * Unsolicited events
1160 */
1161
efe47108 1162static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
38faddb1 1163
20ce9029 1164static void jack_callback(struct hda_codec *codec, struct hda_jack_tbl *jack)
079d88cc
WF		 1165{
1166 struct hdmi_spec *spec = codec->spec;
4e76a883 1167 int pin_idx = pin_nid_to_pin_index(codec, jack->nid);
20ce9029
DH		 1168 if (pin_idx < 0)
1169 return;
1170
1171 if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
1172 snd_hda_jack_report_sync(codec);
1173}
1174
1175static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
1176{
3a93897e 1177 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
3a93897e 1178 struct hda_jack_tbl *jack;
2e59e5ab 1179 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
3a93897e
TI		 1180
1181 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
1182 if (!jack)
1183 return;
3a93897e 1184 jack->jack_dirty = 1;
079d88cc 1185
4e76a883 1186 codec_dbg(codec,
2e59e5ab 1187 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
20ce9029 1188 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
fae3d88a 1189 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
079d88cc 1190
20ce9029 1191 jack_callback(codec, jack);
079d88cc
WF		 1192}
1193
1194static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
1195{
1196 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1197 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1198 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
1199 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
1200
4e76a883 1201 codec_info(codec,
e9ea8e8f 1202 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
384a48d7 1203 codec->addr,
079d88cc
WF		 1204 tag,
1205 subtag,
1206 cp_state,
1207 cp_ready);
1208
1209 /* TODO */
1210 if (cp_state)
1211 ;
1212 if (cp_ready)
1213 ;
1214}
1215
1216
1217static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
1218{
079d88cc
WF		 1219 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1220 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1221
3a93897e 1222 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
4e76a883 1223 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
079d88cc
WF		 1224 return;
1225 }
1226
1227 if (subtag == 0)
1228 hdmi_intrinsic_event(codec, res);
1229 else
1230 hdmi_non_intrinsic_event(codec, res);
1231}
1232
58f7d28d 1233static void haswell_verify_D0(struct hda_codec *codec,
53b434f0 1234 hda_nid_t cvt_nid, hda_nid_t nid)
83f26ad2 1235{
58f7d28d 1236 int pwr;
83f26ad2 1237
53b434f0
WX		 1238 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
1239 * thus pins could only choose converter 0 for use. Make sure the
1240 * converters are in correct power state */
fd678cac 1241 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
53b434f0
WX		 1242 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
1243
fd678cac 1244 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
83f26ad2
DH		 1245 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
1246 AC_PWRST_D0);
1247 msleep(40);
1248 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
1249 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
4e76a883 1250 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
83f26ad2 1251 }
83f26ad2
DH		 1252}
1253
079d88cc
WF		 1254/*
1255 * Callbacks
1256 */
1257
92f10b3f
TI		 1258/* HBR should be Non-PCM, 8 channels */
1259#define is_hbr_format(format) \
1260 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
1261
307229d2
AH		 1262static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
1263 bool hbr)
079d88cc 1264{
307229d2 1265 int pinctl, new_pinctl;
83f26ad2 1266
384a48d7
SW		 1267 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
1268 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
ea87d1c4
AH		 1269 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1270
13122e6e
AH		 1271 if (pinctl < 0)
1272 return hbr ? -EINVAL : 0;
1273
ea87d1c4 1274 new_pinctl = pinctl & ~AC_PINCTL_EPT;
307229d2 1275 if (hbr)
ea87d1c4
AH		 1276 new_pinctl |= AC_PINCTL_EPT_HBR;
1277 else
1278 new_pinctl |= AC_PINCTL_EPT_NATIVE;
1279
4e76a883
TI		 1280 codec_dbg(codec,
1281 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
384a48d7 1282 pin_nid,
ea87d1c4
AH		 1283 pinctl == new_pinctl ? "" : "new-",
1284 new_pinctl);
1285
1286 if (pinctl != new_pinctl)
384a48d7 1287 snd_hda_codec_write(codec, pin_nid, 0,
ea87d1c4
AH		 1288 AC_VERB_SET_PIN_WIDGET_CONTROL,
1289 new_pinctl);
307229d2
AH		 1290 } else if (hbr)
1291 return -EINVAL;
ea87d1c4 1292
307229d2
AH		 1293 return 0;
1294}
1295
1296static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
1297 hda_nid_t pin_nid, u32 stream_tag, int format)
1298{
1299 struct hdmi_spec *spec = codec->spec;
1300 int err;
1301
75dcbe4d 1302 if (is_haswell_plus(codec))
307229d2
AH		 1303 haswell_verify_D0(codec, cvt_nid, pin_nid);
1304
1305 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
1306
1307 if (err) {
4e76a883 1308 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
307229d2 1309 return err;
ea87d1c4 1310 }
079d88cc 1311
384a48d7 1312 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
ea87d1c4 1313 return 0;
079d88cc
WF		 1314}
1315
7ef166b8
WX		 1316static int hdmi_choose_cvt(struct hda_codec *codec,
1317 int pin_idx, int *cvt_id, int *mux_id)
bbbe3390
TI		 1318{
1319 struct hdmi_spec *spec = codec->spec;
384a48d7 1320 struct hdmi_spec_per_pin *per_pin;
384a48d7 1321 struct hdmi_spec_per_cvt *per_cvt = NULL;
7ef166b8 1322 int cvt_idx, mux_idx = 0;
bbbe3390 1323
bce0d2a8 1324 per_pin = get_pin(spec, pin_idx);
384a48d7
SW		 1325
1326 /* Dynamically assign converter to stream */
1327 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
bce0d2a8 1328 per_cvt = get_cvt(spec, cvt_idx);
bbbe3390 1329
384a48d7
SW		 1330 /* Must not already be assigned */
1331 if (per_cvt->assigned)
1332 continue;
1333 /* Must be in pin's mux's list of converters */
1334 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1335 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
1336 break;
1337 /* Not in mux list */
1338 if (mux_idx == per_pin->num_mux_nids)
1339 continue;
1340 break;
1341 }
7ef166b8 1342
384a48d7
SW		 1343 /* No free converters */
1344 if (cvt_idx == spec->num_cvts)
1345 return -ENODEV;
1346
7ef166b8
WX		 1347 if (cvt_id)
1348 *cvt_id = cvt_idx;
1349 if (mux_id)
1350 *mux_id = mux_idx;
1351
1352 return 0;
1353}
1354
300016b9
ML		 1355/* Intel HDMI workaround to fix audio routing issue:
1356 * For some Intel display codecs, pins share the same connection list.
1357 * So a conveter can be selected by multiple pins and playback on any of these
1358 * pins will generate sound on the external display, because audio flows from
1359 * the same converter to the display pipeline. Also muting one pin may make
1360 * other pins have no sound output.
1361 * So this function assures that an assigned converter for a pin is not selected
1362 * by any other pins.
1363 */
1364static void intel_not_share_assigned_cvt(struct hda_codec *codec,
f82d7d16 1365 hda_nid_t pin_nid, int mux_idx)
7ef166b8
WX		 1366{
1367 struct hdmi_spec *spec = codec->spec;
f82d7d16
ML		 1368 hda_nid_t nid, end_nid;
1369 int cvt_idx, curr;
1370 struct hdmi_spec_per_cvt *per_cvt;
7ef166b8 1371
f82d7d16
ML		 1372 /* configure all pins, including "no physical connection" ones */
1373 end_nid = codec->start_nid + codec->num_nodes;
1374 for (nid = codec->start_nid; nid < end_nid; nid++) {
1375 unsigned int wid_caps = get_wcaps(codec, nid);
1376 unsigned int wid_type = get_wcaps_type(wid_caps);
1377
1378 if (wid_type != AC_WID_PIN)
1379 continue;
7ef166b8 1380
f82d7d16 1381 if (nid == pin_nid)
7ef166b8
WX		 1382 continue;
1383
f82d7d16 1384 curr = snd_hda_codec_read(codec, nid, 0,
7ef166b8 1385 AC_VERB_GET_CONNECT_SEL, 0);
f82d7d16
ML		 1386 if (curr != mux_idx)
1387 continue;
7ef166b8 1388
f82d7d16
ML		 1389 /* choose an unassigned converter. The conveters in the
1390 * connection list are in the same order as in the codec.
1391 */
1392 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1393 per_cvt = get_cvt(spec, cvt_idx);
1394 if (!per_cvt->assigned) {
4e76a883
TI		 1395 codec_dbg(codec,
1396 "choose cvt %d for pin nid %d\n",
f82d7d16
ML		 1397 cvt_idx, nid);
1398 snd_hda_codec_write_cache(codec, nid, 0,
7ef166b8 1399 AC_VERB_SET_CONNECT_SEL,
f82d7d16
ML		 1400 cvt_idx);
1401 break;
1402 }
7ef166b8
WX		 1403 }
1404 }
1405}
1406
1407/*
1408 * HDA PCM callbacks
1409 */
1410static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1411 struct hda_codec *codec,
1412 struct snd_pcm_substream *substream)
1413{
1414 struct hdmi_spec *spec = codec->spec;
1415 struct snd_pcm_runtime *runtime = substream->runtime;
1416 int pin_idx, cvt_idx, mux_idx = 0;
1417 struct hdmi_spec_per_pin *per_pin;
1418 struct hdmi_eld *eld;
1419 struct hdmi_spec_per_cvt *per_cvt = NULL;
1420 int err;
1421
1422 /* Validate hinfo */
4e76a883 1423 pin_idx = hinfo_to_pin_index(codec, hinfo);
7ef166b8
WX		 1424 if (snd_BUG_ON(pin_idx < 0))
1425 return -EINVAL;
1426 per_pin = get_pin(spec, pin_idx);
1427 eld = &per_pin->sink_eld;
1428
1429 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, &mux_idx);
1430 if (err < 0)
1431 return err;
1432
1433 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1434 /* Claim converter */
1435 per_cvt->assigned = 1;
1df5a06a 1436 per_pin->cvt_nid = per_cvt->cvt_nid;
384a48d7
SW		 1437 hinfo->nid = per_cvt->cvt_nid;
1438
bddee96b 1439 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
384a48d7
SW		 1440 AC_VERB_SET_CONNECT_SEL,
1441 mux_idx);
7ef166b8
WX		 1442
1443 /* configure unused pins to choose other converters */
75dcbe4d 1444 if (is_haswell_plus(codec) || is_valleyview(codec))
300016b9 1445 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, mux_idx);
7ef166b8 1446
384a48d7 1447 snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
bbbe3390 1448
2def8172 1449 /* Initially set the converter's capabilities */
384a48d7
SW		 1450 hinfo->channels_min = per_cvt->channels_min;
1451 hinfo->channels_max = per_cvt->channels_max;
1452 hinfo->rates = per_cvt->rates;
1453 hinfo->formats = per_cvt->formats;
1454 hinfo->maxbps = per_cvt->maxbps;
2def8172 1455
384a48d7 1456 /* Restrict capabilities by ELD if this isn't disabled */
c3d52105 1457 if (!static_hdmi_pcm && eld->eld_valid) {
1613d6b4 1458 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
bbbe3390 1459 if (hinfo->channels_min > hinfo->channels_max ||
2ad779b7
TI		 1460 !hinfo->rates || !hinfo->formats) {
1461 per_cvt->assigned = 0;
1462 hinfo->nid = 0;
1463 snd_hda_spdif_ctls_unassign(codec, pin_idx);
bbbe3390 1464 return -ENODEV;
2ad779b7 1465 }
bbbe3390 1466 }
2def8172
SW		 1467
1468 /* Store the updated parameters */
639cef0e
TI		 1469 runtime->hw.channels_min = hinfo->channels_min;
1470 runtime->hw.channels_max = hinfo->channels_max;
1471 runtime->hw.formats = hinfo->formats;
1472 runtime->hw.rates = hinfo->rates;
4fe2ca14
TI		 1473
1474 snd_pcm_hw_constraint_step(substream->runtime, 0,
1475 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
bbbe3390
TI		 1476 return 0;
1477}
1478
079d88cc
WF		 1479/*
1480 * HDA/HDMI auto parsing
1481 */
384a48d7 1482static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
079d88cc
WF		 1483{
1484 struct hdmi_spec *spec = codec->spec;
bce0d2a8 1485 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
384a48d7 1486 hda_nid_t pin_nid = per_pin->pin_nid;
079d88cc
WF		 1487
1488 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
4e76a883
TI		 1489 codec_warn(codec,
1490 "HDMI: pin %d wcaps %#x does not support connection list\n",
079d88cc
WF		 1491 pin_nid, get_wcaps(codec, pin_nid));
1492 return -EINVAL;
1493 }
1494
384a48d7
SW		 1495 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1496 per_pin->mux_nids,
1497 HDA_MAX_CONNECTIONS);
079d88cc
WF		 1498
1499 return 0;
1500}
1501
efe47108 1502static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
079d88cc 1503{
464837a7 1504 struct hda_jack_tbl *jack;
744626da 1505 struct hda_codec *codec = per_pin->codec;
4bd038f9
DH		 1506 struct hdmi_spec *spec = codec->spec;
1507 struct hdmi_eld *eld = &spec->temp_eld;
1508 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
744626da 1509 hda_nid_t pin_nid = per_pin->pin_nid;
5d44f927
SW		 1510 /*
1511 * Always execute a GetPinSense verb here, even when called from
1512 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1513 * response's PD bit is not the real PD value, but indicates that
1514 * the real PD value changed. An older version of the HD-audio
1515 * specification worked this way. Hence, we just ignore the data in
1516 * the unsolicited response to avoid custom WARs.
1517 */
da4a7a39 1518 int present;
4bd038f9
DH		 1519 bool update_eld = false;
1520 bool eld_changed = false;
efe47108 1521 bool ret;
079d88cc 1522
da4a7a39
DH		 1523 snd_hda_power_up(codec);
1524 present = snd_hda_pin_sense(codec, pin_nid);
1525
a4e9a38b 1526 mutex_lock(&per_pin->lock);
4bd038f9
DH		 1527 pin_eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1528 if (pin_eld->monitor_present)
1529 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1530 else
1531 eld->eld_valid = false;
079d88cc 1532
4e76a883 1533 codec_dbg(codec,
384a48d7 1534 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
10250911 1535 codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid);
5d44f927 1536
4bd038f9 1537 if (eld->eld_valid) {
307229d2 1538 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1613d6b4 1539 &eld->eld_size) < 0)
4bd038f9 1540 eld->eld_valid = false;
1613d6b4
DH		 1541 else {
1542 memset(&eld->info, 0, sizeof(struct parsed_hdmi_eld));
1543 if (snd_hdmi_parse_eld(&eld->info, eld->eld_buffer,
1544 eld->eld_size) < 0)
4bd038f9 1545 eld->eld_valid = false;
1613d6b4
DH		 1546 }
1547
4bd038f9 1548 if (eld->eld_valid) {
1613d6b4 1549 snd_hdmi_show_eld(&eld->info);
4bd038f9 1550 update_eld = true;
1613d6b4 1551 }
c6e8453e 1552 else if (repoll) {
744626da
WF		 1553 queue_delayed_work(codec->bus->workq,
1554 &per_pin->work,
1555 msecs_to_jiffies(300));
cbbaa603 1556 goto unlock;
744626da
WF		 1557 }
1558 }
4bd038f9 1559
92c69e79 1560 if (pin_eld->eld_valid && !eld->eld_valid) {
4bd038f9 1561 update_eld = true;
92c69e79
DH		 1562 eld_changed = true;
1563 }
4bd038f9 1564 if (update_eld) {
b054087d 1565 bool old_eld_valid = pin_eld->eld_valid;
4bd038f9 1566 pin_eld->eld_valid = eld->eld_valid;
92c69e79
DH		 1567 eld_changed = pin_eld->eld_size != eld->eld_size ||
1568 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
4bd038f9
DH		 1569 eld->eld_size) != 0;
1570 if (eld_changed)
1571 memcpy(pin_eld->eld_buffer, eld->eld_buffer,
1572 eld->eld_size);
1573 pin_eld->eld_size = eld->eld_size;
1574 pin_eld->info = eld->info;
b054087d 1575
7342017f
AH		 1576 /*
1577 * Re-setup pin and infoframe. This is needed e.g. when
1578 * - sink is first plugged-in (infoframe is not set up if !monitor_present)
1579 * - transcoder can change during stream playback on Haswell
b054087d 1580 */
7342017f 1581 if (eld->eld_valid && !old_eld_valid && per_pin->setup)
b054087d
TI		 1582 hdmi_setup_audio_infoframe(codec, per_pin,
1583 per_pin->non_pcm);
4bd038f9 1584 }
92c69e79
DH		 1585
1586 if (eld_changed)
1587 snd_ctl_notify(codec->bus->card,
1588 SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO,
1589 &per_pin->eld_ctl->id);
cbbaa603 1590 unlock:
aff747eb 1591 ret = !repoll || !pin_eld->monitor_present || pin_eld->eld_valid;
464837a7
DH		 1592
1593 jack = snd_hda_jack_tbl_get(codec, pin_nid);
1594 if (jack)
1595 jack->block_report = !ret;
1596
a4e9a38b 1597 mutex_unlock(&per_pin->lock);
da4a7a39 1598 snd_hda_power_down(codec);
efe47108 1599 return ret;
079d88cc
WF		 1600}
1601
744626da
WF		 1602static void hdmi_repoll_eld(struct work_struct *work)
1603{
1604 struct hdmi_spec_per_pin *per_pin =
1605 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1606
c6e8453e
WF		 1607 if (per_pin->repoll_count++ > 6)
1608 per_pin->repoll_count = 0;
1609
efe47108
TI		 1610 if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1611 snd_hda_jack_report_sync(per_pin->codec);
744626da
WF		 1612}
1613
c88d4e84
TI		 1614static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1615 hda_nid_t nid);
1616
079d88cc
WF		 1617static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1618{
1619 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1620 unsigned int caps, config;
1621 int pin_idx;
1622 struct hdmi_spec_per_pin *per_pin;
07acecc1 1623 int err;
079d88cc 1624
efc2f8de 1625 caps = snd_hda_query_pin_caps(codec, pin_nid);
384a48d7
SW		 1626 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1627 return 0;
1628
efc2f8de 1629 config = snd_hda_codec_get_pincfg(codec, pin_nid);
384a48d7
SW		 1630 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1631 return 0;
1632
75dcbe4d 1633 if (is_haswell_plus(codec))
c88d4e84
TI		 1634 intel_haswell_fixup_connect_list(codec, pin_nid);
1635
384a48d7 1636 pin_idx = spec->num_pins;
bce0d2a8
TI		 1637 per_pin = snd_array_new(&spec->pins);
1638 if (!per_pin)
1639 return -ENOMEM;
384a48d7
SW		 1640
1641 per_pin->pin_nid = pin_nid;
1a6003b5 1642 per_pin->non_pcm = false;
079d88cc 1643
384a48d7
SW		 1644 err = hdmi_read_pin_conn(codec, pin_idx);
1645 if (err < 0)
1646 return err;
079d88cc 1647
079d88cc
WF		 1648 spec->num_pins++;
1649
384a48d7 1650 return 0;
079d88cc
WF		 1651}
1652
384a48d7 1653static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc
WF		 1654{
1655 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1656 struct hdmi_spec_per_cvt *per_cvt;
1657 unsigned int chans;
1658 int err;
079d88cc 1659
384a48d7
SW		 1660 chans = get_wcaps(codec, cvt_nid);
1661 chans = get_wcaps_channels(chans);
1662
bce0d2a8
TI		 1663 per_cvt = snd_array_new(&spec->cvts);
1664 if (!per_cvt)
1665 return -ENOMEM;
384a48d7
SW		 1666
1667 per_cvt->cvt_nid = cvt_nid;
1668 per_cvt->channels_min = 2;
d45e6889 1669 if (chans <= 16) {
384a48d7 1670 per_cvt->channels_max = chans;
d45e6889
TI		 1671 if (chans > spec->channels_max)
1672 spec->channels_max = chans;
1673 }
384a48d7
SW		 1674
1675 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1676 &per_cvt->rates,
1677 &per_cvt->formats,
1678 &per_cvt->maxbps);
1679 if (err < 0)
1680 return err;
1681
bce0d2a8
TI		 1682 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1683 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1684 spec->num_cvts++;
079d88cc
WF		 1685
1686 return 0;
1687}
1688
1689static int hdmi_parse_codec(struct hda_codec *codec)
1690{
1691 hda_nid_t nid;
1692 int i, nodes;
1693
1694 nodes = snd_hda_get_sub_nodes(codec, codec->afg, &nid);
1695 if (!nid || nodes < 0) {
4e76a883 1696 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
079d88cc
WF		 1697 return -EINVAL;
1698 }
1699
1700 for (i = 0; i < nodes; i++, nid++) {
1701 unsigned int caps;
1702 unsigned int type;
1703
efc2f8de 1704 caps = get_wcaps(codec, nid);
079d88cc
WF		 1705 type = get_wcaps_type(caps);
1706
1707 if (!(caps & AC_WCAP_DIGITAL))
1708 continue;
1709
1710 switch (type) {
1711 case AC_WID_AUD_OUT:
384a48d7 1712 hdmi_add_cvt(codec, nid);
079d88cc
WF		 1713 break;
1714 case AC_WID_PIN:
3eaead57 1715 hdmi_add_pin(codec, nid);
079d88cc
WF		 1716 break;
1717 }
1718 }
1719
079d88cc
WF		 1720 return 0;
1721}
1722
84eb01be
TI		 1723/*
1724 */
1a6003b5
TI		 1725static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1726{
1727 struct hda_spdif_out *spdif;
1728 bool non_pcm;
1729
1730 mutex_lock(&codec->spdif_mutex);
1731 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1732 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1733 mutex_unlock(&codec->spdif_mutex);
1734 return non_pcm;
1735}
1736
1737
84eb01be
TI		 1738/*
1739 * HDMI callbacks
1740 */
1741
1742static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1743 struct hda_codec *codec,
1744 unsigned int stream_tag,
1745 unsigned int format,
1746 struct snd_pcm_substream *substream)
1747{
384a48d7
SW		 1748 hda_nid_t cvt_nid = hinfo->nid;
1749 struct hdmi_spec *spec = codec->spec;
4e76a883 1750 int pin_idx = hinfo_to_pin_index(codec, hinfo);
b054087d
TI		 1751 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1752 hda_nid_t pin_nid = per_pin->pin_nid;
1a6003b5 1753 bool non_pcm;
75fae117 1754 int pinctl;
1a6003b5
TI		 1755
1756 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
a4e9a38b 1757 mutex_lock(&per_pin->lock);
b054087d
TI		 1758 per_pin->channels = substream->runtime->channels;
1759 per_pin->setup = true;
384a48d7 1760
b054087d 1761 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
a4e9a38b 1762 mutex_unlock(&per_pin->lock);
84eb01be 1763
75fae117
SW		 1764 if (spec->dyn_pin_out) {
1765 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1766 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1767 snd_hda_codec_write(codec, pin_nid, 0,
1768 AC_VERB_SET_PIN_WIDGET_CONTROL,
1769 pinctl | PIN_OUT);
1770 }
1771
307229d2 1772 return spec->ops.setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
84eb01be
TI		 1773}
1774
8dfaa573
TI		 1775static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1776 struct hda_codec *codec,
1777 struct snd_pcm_substream *substream)
1778{
1779 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1780 return 0;
1781}
1782
f2ad24fa
TI		 1783static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1784 struct hda_codec *codec,
1785 struct snd_pcm_substream *substream)
384a48d7
SW		 1786{
1787 struct hdmi_spec *spec = codec->spec;
1788 int cvt_idx, pin_idx;
1789 struct hdmi_spec_per_cvt *per_cvt;
1790 struct hdmi_spec_per_pin *per_pin;
75fae117 1791 int pinctl;
384a48d7 1792
384a48d7 1793 if (hinfo->nid) {
4e76a883 1794 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
384a48d7
SW		 1795 if (snd_BUG_ON(cvt_idx < 0))
1796 return -EINVAL;
bce0d2a8 1797 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1798
1799 snd_BUG_ON(!per_cvt->assigned);
1800 per_cvt->assigned = 0;
1801 hinfo->nid = 0;
1802
4e76a883 1803 pin_idx = hinfo_to_pin_index(codec, hinfo);
384a48d7
SW		 1804 if (snd_BUG_ON(pin_idx < 0))
1805 return -EINVAL;
bce0d2a8 1806 per_pin = get_pin(spec, pin_idx);
384a48d7 1807
75fae117
SW		 1808 if (spec->dyn_pin_out) {
1809 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1810 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1811 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1812 AC_VERB_SET_PIN_WIDGET_CONTROL,
1813 pinctl & ~PIN_OUT);
1814 }
1815
384a48d7 1816 snd_hda_spdif_ctls_unassign(codec, pin_idx);
cbbaa603 1817
a4e9a38b 1818 mutex_lock(&per_pin->lock);
d45e6889
TI		 1819 per_pin->chmap_set = false;
1820 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
b054087d
TI		 1821
1822 per_pin->setup = false;
1823 per_pin->channels = 0;
a4e9a38b 1824 mutex_unlock(&per_pin->lock);
384a48d7 1825 }
d45e6889 1826
384a48d7
SW		 1827 return 0;
1828}
1829
1830static const struct hda_pcm_ops generic_ops = {
1831 .open = hdmi_pcm_open,
f2ad24fa 1832 .close = hdmi_pcm_close,
384a48d7 1833 .prepare = generic_hdmi_playback_pcm_prepare,
8dfaa573 1834 .cleanup = generic_hdmi_playback_pcm_cleanup,
84eb01be
TI		 1835};
1836
d45e6889
TI		 1837/*
1838 * ALSA API channel-map control callbacks
1839 */
1840static int hdmi_chmap_ctl_info(struct snd_kcontrol *kcontrol,
1841 struct snd_ctl_elem_info *uinfo)
1842{
1843 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1844 struct hda_codec *codec = info->private_data;
1845 struct hdmi_spec *spec = codec->spec;
1846 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1847 uinfo->count = spec->channels_max;
1848 uinfo->value.integer.min = 0;
1849 uinfo->value.integer.max = SNDRV_CHMAP_LAST;
1850 return 0;
1851}
1852
307229d2
AH		 1853static int hdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
1854 int channels)
1855{
1856 /* If the speaker allocation matches the channel count, it is OK.*/
1857 if (cap->channels != channels)
1858 return -1;
1859
1860 /* all channels are remappable freely */
1861 return SNDRV_CTL_TLVT_CHMAP_VAR;
1862}
1863
1864static void hdmi_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
1865 unsigned int *chmap, int channels)
1866{
1867 int count = 0;
1868 int c;
1869
1870 for (c = 7; c >= 0; c--) {
1871 int spk = cap->speakers[c];
1872 if (!spk)
1873 continue;
1874
1875 chmap[count++] = spk_to_chmap(spk);
1876 }
1877
1878 WARN_ON(count != channels);
1879}
1880
d45e6889
TI		 1881static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
1882 unsigned int size, unsigned int __user *tlv)
1883{
1884 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1885 struct hda_codec *codec = info->private_data;
1886 struct hdmi_spec *spec = codec->spec;
d45e6889
TI		 1887 unsigned int __user *dst;
1888 int chs, count = 0;
1889
1890 if (size < 8)
1891 return -ENOMEM;
1892 if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
1893 return -EFAULT;
1894 size -= 8;
1895 dst = tlv + 2;
498dab3a 1896 for (chs = 2; chs <= spec->channels_max; chs++) {
307229d2 1897 int i;
d45e6889
TI		 1898 struct cea_channel_speaker_allocation *cap;
1899 cap = channel_allocations;
1900 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++, cap++) {
1901 int chs_bytes = chs * 4;
307229d2
AH		 1902 int type = spec->ops.chmap_cea_alloc_validate_get_type(cap, chs);
1903 unsigned int tlv_chmap[8];
1904
1905 if (type < 0)
d45e6889 1906 continue;
d45e6889
TI		 1907 if (size < 8)
1908 return -ENOMEM;
307229d2 1909 if (put_user(type, dst) ||
d45e6889
TI		 1910 put_user(chs_bytes, dst + 1))
1911 return -EFAULT;
1912 dst += 2;
1913 size -= 8;
1914 count += 8;
1915 if (size < chs_bytes)
1916 return -ENOMEM;
1917 size -= chs_bytes;
1918 count += chs_bytes;
307229d2
AH		 1919 spec->ops.cea_alloc_to_tlv_chmap(cap, tlv_chmap, chs);
1920 if (copy_to_user(dst, tlv_chmap, chs_bytes))
1921 return -EFAULT;
1922 dst += chs;
d45e6889
TI		 1923 }
1924 }
1925 if (put_user(count, tlv + 1))
1926 return -EFAULT;
1927 return 0;
1928}
1929
1930static int hdmi_chmap_ctl_get(struct snd_kcontrol *kcontrol,
1931 struct snd_ctl_elem_value *ucontrol)
1932{
1933 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1934 struct hda_codec *codec = info->private_data;
1935 struct hdmi_spec *spec = codec->spec;
1936 int pin_idx = kcontrol->private_value;
bce0d2a8 1937 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
d45e6889
TI		 1938 int i;
1939
1940 for (i = 0; i < ARRAY_SIZE(per_pin->chmap); i++)
1941 ucontrol->value.integer.value[i] = per_pin->chmap[i];
1942 return 0;
1943}
1944
1945static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol,
1946 struct snd_ctl_elem_value *ucontrol)
1947{
1948 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1949 struct hda_codec *codec = info->private_data;
1950 struct hdmi_spec *spec = codec->spec;
1951 int pin_idx = kcontrol->private_value;
bce0d2a8 1952 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
d45e6889
TI		 1953 unsigned int ctl_idx;
1954 struct snd_pcm_substream *substream;
1955 unsigned char chmap[8];
307229d2 1956 int i, err, ca, prepared = 0;
d45e6889
TI		 1957
1958 ctl_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
1959 substream = snd_pcm_chmap_substream(info, ctl_idx);
1960 if (!substream || !substream->runtime)
6f54c361 1961 return 0; /* just for avoiding error from alsactl restore */
d45e6889
TI		 1962 switch (substream->runtime->status->state) {
1963 case SNDRV_PCM_STATE_OPEN:
1964 case SNDRV_PCM_STATE_SETUP:
1965 break;
1966 case SNDRV_PCM_STATE_PREPARED:
1967 prepared = 1;
1968 break;
1969 default:
1970 return -EBUSY;
1971 }
1972 memset(chmap, 0, sizeof(chmap));
1973 for (i = 0; i < ARRAY_SIZE(chmap); i++)
1974 chmap[i] = ucontrol->value.integer.value[i];
1975 if (!memcmp(chmap, per_pin->chmap, sizeof(chmap)))
1976 return 0;
1977 ca = hdmi_manual_channel_allocation(ARRAY_SIZE(chmap), chmap);
1978 if (ca < 0)
1979 return -EINVAL;
307229d2
AH		 1980 if (spec->ops.chmap_validate) {
1981 err = spec->ops.chmap_validate(ca, ARRAY_SIZE(chmap), chmap);
1982 if (err)
1983 return err;
1984 }
a4e9a38b 1985 mutex_lock(&per_pin->lock);
d45e6889
TI		 1986 per_pin->chmap_set = true;
1987 memcpy(per_pin->chmap, chmap, sizeof(chmap));
1988 if (prepared)
b054087d 1989 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
a4e9a38b 1990 mutex_unlock(&per_pin->lock);
d45e6889
TI		 1991
1992 return 0;
1993}
1994
84eb01be
TI		 1995static int generic_hdmi_build_pcms(struct hda_codec *codec)
1996{
1997 struct hdmi_spec *spec = codec->spec;
384a48d7 1998 int pin_idx;
84eb01be 1999
384a48d7
SW		 2000 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2001 struct hda_pcm *info;
84eb01be 2002 struct hda_pcm_stream *pstr;
bce0d2a8
TI		 2003 struct hdmi_spec_per_pin *per_pin;
2004
2005 per_pin = get_pin(spec, pin_idx);
2006 sprintf(per_pin->pcm_name, "HDMI %d", pin_idx);
2007 info = snd_array_new(&spec->pcm_rec);
2008 if (!info)
2009 return -ENOMEM;
2010 info->name = per_pin->pcm_name;
84eb01be 2011 info->pcm_type = HDA_PCM_TYPE_HDMI;
d45e6889 2012 info->own_chmap = true;
384a48d7 2013
84eb01be 2014 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
384a48d7
SW		 2015 pstr->substreams = 1;
2016 pstr->ops = generic_ops;
2017 /* other pstr fields are set in open */
84eb01be
TI		 2018 }
2019
384a48d7 2020 codec->num_pcms = spec->num_pins;
bce0d2a8 2021 codec->pcm_info = spec->pcm_rec.list;
384a48d7 2022
84eb01be
TI		 2023 return 0;
2024}
2025
0b6c49b5
DH		 2026static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
2027{
31ef2257 2028 char hdmi_str[32] = "HDMI/DP";
0b6c49b5 2029 struct hdmi_spec *spec = codec->spec;
bce0d2a8
TI		 2030 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2031 int pcmdev = get_pcm_rec(spec, pin_idx)->device;
0b6c49b5 2032
31ef2257
TI		 2033 if (pcmdev > 0)
2034 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
30efd8de
DH		 2035 if (!is_jack_detectable(codec, per_pin->pin_nid))
2036 strncat(hdmi_str, " Phantom",
2037 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
0b6c49b5 2038
31ef2257 2039 return snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str, 0);
0b6c49b5
DH		 2040}
2041
84eb01be
TI		 2042static int generic_hdmi_build_controls(struct hda_codec *codec)
2043{
2044 struct hdmi_spec *spec = codec->spec;
2045 int err;
384a48d7 2046 int pin_idx;
84eb01be 2047
384a48d7 2048 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2049 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
0b6c49b5
DH		 2050
2051 err = generic_hdmi_build_jack(codec, pin_idx);
2052 if (err < 0)
2053 return err;
2054
dcda5806
TI		 2055 err = snd_hda_create_dig_out_ctls(codec,
2056 per_pin->pin_nid,
2057 per_pin->mux_nids[0],
2058 HDA_PCM_TYPE_HDMI);
84eb01be
TI		 2059 if (err < 0)
2060 return err;
384a48d7 2061 snd_hda_spdif_ctls_unassign(codec, pin_idx);
14bc52b8
PLB		 2062
2063 /* add control for ELD Bytes */
bce0d2a8
TI		 2064 err = hdmi_create_eld_ctl(codec, pin_idx,
2065 get_pcm_rec(spec, pin_idx)->device);
14bc52b8
PLB		 2066
2067 if (err < 0)
2068 return err;
31ef2257 2069
82b1d73f 2070 hdmi_present_sense(per_pin, 0);
84eb01be
TI		 2071 }
2072
d45e6889
TI		 2073 /* add channel maps */
2074 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2075 struct snd_pcm_chmap *chmap;
2076 struct snd_kcontrol *kctl;
2077 int i;
2ca320e2
TI		 2078
2079 if (!codec->pcm_info[pin_idx].pcm)
2080 break;
d45e6889
TI		 2081 err = snd_pcm_add_chmap_ctls(codec->pcm_info[pin_idx].pcm,
2082 SNDRV_PCM_STREAM_PLAYBACK,
2083 NULL, 0, pin_idx, &chmap);
2084 if (err < 0)
2085 return err;
2086 /* override handlers */
2087 chmap->private_data = codec;
2088 kctl = chmap->kctl;
2089 for (i = 0; i < kctl->count; i++)
2090 kctl->vd[i].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
2091 kctl->info = hdmi_chmap_ctl_info;
2092 kctl->get = hdmi_chmap_ctl_get;
2093 kctl->put = hdmi_chmap_ctl_put;
2094 kctl->tlv.c = hdmi_chmap_ctl_tlv;
2095 }
2096
84eb01be
TI		 2097 return 0;
2098}
2099
8b8d654b 2100static int generic_hdmi_init_per_pins(struct hda_codec *codec)
84eb01be
TI		 2101{
2102 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 2103 int pin_idx;
2104
2105 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2106 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
84eb01be 2107
744626da 2108 per_pin->codec = codec;
a4e9a38b 2109 mutex_init(&per_pin->lock);
744626da 2110 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
a4e9a38b 2111 eld_proc_new(per_pin, pin_idx);
84eb01be 2112 }
8b8d654b
TI		 2113 return 0;
2114}
2115
2116static int generic_hdmi_init(struct hda_codec *codec)
2117{
2118 struct hdmi_spec *spec = codec->spec;
2119 int pin_idx;
2120
2121 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2122 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
8b8d654b
TI		 2123 hda_nid_t pin_nid = per_pin->pin_nid;
2124
2125 hdmi_init_pin(codec, pin_nid);
20ce9029
DH		 2126 snd_hda_jack_detect_enable_callback(codec, pin_nid, pin_nid,
2127 codec->jackpoll_interval > 0 ? jack_callback : NULL);
8b8d654b 2128 }
84eb01be
TI		 2129 return 0;
2130}
2131
bce0d2a8
TI		 2132static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2133{
2134 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2135 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2136 snd_array_init(&spec->pcm_rec, sizeof(struct hda_pcm), nums);
2137}
2138
2139static void hdmi_array_free(struct hdmi_spec *spec)
2140{
2141 snd_array_free(&spec->pins);
2142 snd_array_free(&spec->cvts);
2143 snd_array_free(&spec->pcm_rec);
2144}
2145
84eb01be
TI		 2146static void generic_hdmi_free(struct hda_codec *codec)
2147{
2148 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 2149 int pin_idx;
2150
2151 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2152 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
84eb01be 2153
744626da 2154 cancel_delayed_work(&per_pin->work);
a4e9a38b 2155 eld_proc_free(per_pin);
384a48d7 2156 }
84eb01be 2157
744626da 2158 flush_workqueue(codec->bus->workq);
bce0d2a8 2159 hdmi_array_free(spec);
84eb01be
TI		 2160 kfree(spec);
2161}
2162
28cb72e5
WX		 2163#ifdef CONFIG_PM
2164static int generic_hdmi_resume(struct hda_codec *codec)
2165{
2166 struct hdmi_spec *spec = codec->spec;
2167 int pin_idx;
2168
2169 generic_hdmi_init(codec);
2170 snd_hda_codec_resume_amp(codec);
2171 snd_hda_codec_resume_cache(codec);
2172
2173 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2174 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2175 hdmi_present_sense(per_pin, 1);
2176 }
2177 return 0;
2178}
2179#endif
2180
fb79e1e0 2181static const struct hda_codec_ops generic_hdmi_patch_ops = {
84eb01be
TI		 2182 .init = generic_hdmi_init,
2183 .free = generic_hdmi_free,
2184 .build_pcms = generic_hdmi_build_pcms,
2185 .build_controls = generic_hdmi_build_controls,
2186 .unsol_event = hdmi_unsol_event,
28cb72e5
WX		 2187#ifdef CONFIG_PM
2188 .resume = generic_hdmi_resume,
2189#endif
84eb01be
TI		 2190};
2191
307229d2
AH		 2192static const struct hdmi_ops generic_standard_hdmi_ops = {
2193 .pin_get_eld = snd_hdmi_get_eld,
2194 .pin_get_slot_channel = hdmi_pin_get_slot_channel,
2195 .pin_set_slot_channel = hdmi_pin_set_slot_channel,
2196 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2197 .pin_hbr_setup = hdmi_pin_hbr_setup,
2198 .setup_stream = hdmi_setup_stream,
2199 .chmap_cea_alloc_validate_get_type = hdmi_chmap_cea_alloc_validate_get_type,
2200 .cea_alloc_to_tlv_chmap = hdmi_cea_alloc_to_tlv_chmap,
2201};
2202
6ffe168f 2203
c88d4e84
TI		 2204static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2205 hda_nid_t nid)
2206{
2207 struct hdmi_spec *spec = codec->spec;
2208 hda_nid_t conns[4];
2209 int nconns;
6ffe168f 2210
c88d4e84
TI		 2211 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2212 if (nconns == spec->num_cvts &&
2213 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
6ffe168f
ML		 2214 return;
2215
c88d4e84 2216 /* override pins connection list */
4e76a883 2217 codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
c88d4e84 2218 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
6ffe168f
ML		 2219}
2220
1611a9c9
ML		 2221#define INTEL_VENDOR_NID 0x08
2222#define INTEL_GET_VENDOR_VERB 0xf81
2223#define INTEL_SET_VENDOR_VERB 0x781
2224#define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2225#define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2226
2227static void intel_haswell_enable_all_pins(struct hda_codec *codec,
17df3f55 2228 bool update_tree)
1611a9c9
ML		 2229{
2230 unsigned int vendor_param;
2231
1611a9c9
ML		 2232 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2233 INTEL_GET_VENDOR_VERB, 0);
2234 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2235 return;
2236
2237 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2238 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2239 INTEL_SET_VENDOR_VERB, vendor_param);
2240 if (vendor_param == -1)
2241 return;
2242
17df3f55
TI		 2243 if (update_tree)
2244 snd_hda_codec_update_widgets(codec);
1611a9c9
ML		 2245}
2246
c88d4e84
TI		 2247static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2248{
2249 unsigned int vendor_param;
2250
2251 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2252 INTEL_GET_VENDOR_VERB, 0);
2253 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2254 return;
2255
2256 /* enable DP1.2 mode */
2257 vendor_param |= INTEL_EN_DP12;
2258 snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
2259 INTEL_SET_VENDOR_VERB, vendor_param);
2260}
2261
17df3f55
TI		 2262/* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2263 * Otherwise you may get severe h/w communication errors.
2264 */
2265static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2266 unsigned int power_state)
2267{
2268 if (power_state == AC_PWRST_D0) {
2269 intel_haswell_enable_all_pins(codec, false);
2270 intel_haswell_fixup_enable_dp12(codec);
2271 }
c88d4e84 2272
17df3f55
TI		 2273 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2274 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2275}
6ffe168f 2276
84eb01be
TI		 2277static int patch_generic_hdmi(struct hda_codec *codec)
2278{
2279 struct hdmi_spec *spec;
84eb01be
TI		 2280
2281 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2282 if (spec == NULL)
2283 return -ENOMEM;
2284
307229d2 2285 spec->ops = generic_standard_hdmi_ops;
84eb01be 2286 codec->spec = spec;
bce0d2a8 2287 hdmi_array_init(spec, 4);
6ffe168f 2288
75dcbe4d 2289 if (is_haswell_plus(codec)) {
17df3f55 2290 intel_haswell_enable_all_pins(codec, true);
c88d4e84 2291 intel_haswell_fixup_enable_dp12(codec);
17df3f55 2292 }
6ffe168f 2293
5b8620bb
ML		 2294 if (is_haswell(codec) || is_valleyview(codec)) {
2295 codec->depop_delay = 0;
2296 }
2297
84eb01be
TI		 2298 if (hdmi_parse_codec(codec) < 0) {
2299 codec->spec = NULL;
2300 kfree(spec);
2301 return -EINVAL;
2302 }
2303 codec->patch_ops = generic_hdmi_patch_ops;
75dcbe4d 2304 if (is_haswell_plus(codec)) {
17df3f55 2305 codec->patch_ops.set_power_state = haswell_set_power_state;
5dc989bd
ML		 2306 codec->dp_mst = true;
2307 }
17df3f55 2308
8b8d654b 2309 generic_hdmi_init_per_pins(codec);
84eb01be 2310
84eb01be
TI		 2311 init_channel_allocations();
2312
2313 return 0;
2314}
2315
3aaf8980
SW		 2316/*
2317 * Shared non-generic implementations
2318 */
2319
2320static int simple_playback_build_pcms(struct hda_codec *codec)
2321{
2322 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2323 struct hda_pcm *info;
8ceb332d
TI		 2324 unsigned int chans;
2325 struct hda_pcm_stream *pstr;
bce0d2a8 2326 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2327
bce0d2a8
TI		 2328 per_cvt = get_cvt(spec, 0);
2329 chans = get_wcaps(codec, per_cvt->cvt_nid);
8ceb332d 2330 chans = get_wcaps_channels(chans);
3aaf8980 2331
bce0d2a8
TI		 2332 info = snd_array_new(&spec->pcm_rec);
2333 if (!info)
2334 return -ENOMEM;
2335 info->name = get_pin(spec, 0)->pcm_name;
2336 sprintf(info->name, "HDMI 0");
8ceb332d
TI		 2337 info->pcm_type = HDA_PCM_TYPE_HDMI;
2338 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2339 *pstr = spec->pcm_playback;
bce0d2a8 2340 pstr->nid = per_cvt->cvt_nid;
8ceb332d
TI		 2341 if (pstr->channels_max <= 2 && chans && chans <= 16)
2342 pstr->channels_max = chans;
3aaf8980 2343
bce0d2a8
TI		 2344 codec->num_pcms = 1;
2345 codec->pcm_info = info;
2346
3aaf8980
SW		 2347 return 0;
2348}
2349
4b6ace9e
TI		 2350/* unsolicited event for jack sensing */
2351static void simple_hdmi_unsol_event(struct hda_codec *codec,
2352 unsigned int res)
2353{
9dd8cf12 2354 snd_hda_jack_set_dirty_all(codec);
4b6ace9e
TI		 2355 snd_hda_jack_report_sync(codec);
2356}
2357
2358/* generic_hdmi_build_jack can be used for simple_hdmi, too,
2359 * as long as spec->pins[] is set correctly
2360 */
2361#define simple_hdmi_build_jack generic_hdmi_build_jack
2362
3aaf8980
SW		 2363static int simple_playback_build_controls(struct hda_codec *codec)
2364{
2365 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2366 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2367 int err;
3aaf8980 2368
bce0d2a8 2369 per_cvt = get_cvt(spec, 0);
c9a6338a
AH		 2370 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2371 per_cvt->cvt_nid,
2372 HDA_PCM_TYPE_HDMI);
8ceb332d
TI		 2373 if (err < 0)
2374 return err;
2375 return simple_hdmi_build_jack(codec, 0);
3aaf8980
SW		 2376}
2377
4f0110ce
TI		 2378static int simple_playback_init(struct hda_codec *codec)
2379{
2380 struct hdmi_spec *spec = codec->spec;
bce0d2a8
TI		 2381 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2382 hda_nid_t pin = per_pin->pin_nid;
8ceb332d
TI		 2383
2384 snd_hda_codec_write(codec, pin, 0,
2385 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2386 /* some codecs require to unmute the pin */
2387 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2388 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2389 AMP_OUT_UNMUTE);
2390 snd_hda_jack_detect_enable(codec, pin, pin);
4f0110ce
TI		 2391 return 0;
2392}
2393
3aaf8980
SW		 2394static void simple_playback_free(struct hda_codec *codec)
2395{
2396 struct hdmi_spec *spec = codec->spec;
2397
bce0d2a8 2398 hdmi_array_free(spec);
3aaf8980
SW		 2399 kfree(spec);
2400}
2401
84eb01be
TI		 2402/*
2403 * Nvidia specific implementations
2404 */
2405
2406#define Nv_VERB_SET_Channel_Allocation 0xF79
2407#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2408#define Nv_VERB_SET_Audio_Protection_On 0xF98
2409#define Nv_VERB_SET_Audio_Protection_Off 0xF99
2410
2411#define nvhdmi_master_con_nid_7x 0x04
2412#define nvhdmi_master_pin_nid_7x 0x05
2413
fb79e1e0 2414static const hda_nid_t nvhdmi_con_nids_7x[4] = {
84eb01be
TI		 2415 /*front, rear, clfe, rear_surr */
2416 0x6, 0x8, 0xa, 0xc,
2417};
2418
ceaa86ba
TI		 2419static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2420 /* set audio protect on */
2421 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2422 /* enable digital output on pin widget */
2423 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2424 {} /* terminator */
2425};
2426
2427static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
84eb01be
TI		 2428 /* set audio protect on */
2429 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2430 /* enable digital output on pin widget */
2431 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2432 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2433 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2434 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2435 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2436 {} /* terminator */
2437};
2438
2439#ifdef LIMITED_RATE_FMT_SUPPORT
2440/* support only the safe format and rate */
2441#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2442#define SUPPORTED_MAXBPS 16
2443#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2444#else
2445/* support all rates and formats */
2446#define SUPPORTED_RATES \
2447 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2448 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2449 SNDRV_PCM_RATE_192000)
2450#define SUPPORTED_MAXBPS 24
2451#define SUPPORTED_FORMATS \
2452 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2453#endif
2454
ceaa86ba
TI		 2455static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2456{
2457 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2458 return 0;
2459}
2460
2461static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
84eb01be 2462{
ceaa86ba 2463 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
84eb01be
TI		 2464 return 0;
2465}
2466
393004b2
ND		 2467static unsigned int channels_2_6_8[] = {
2468 2, 6, 8
2469};
2470
2471static unsigned int channels_2_8[] = {
2472 2, 8
2473};
2474
2475static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2476 .count = ARRAY_SIZE(channels_2_6_8),
2477 .list = channels_2_6_8,
2478 .mask = 0,
2479};
2480
2481static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2482 .count = ARRAY_SIZE(channels_2_8),
2483 .list = channels_2_8,
2484 .mask = 0,
2485};
2486
84eb01be
TI		 2487static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2488 struct hda_codec *codec,
2489 struct snd_pcm_substream *substream)
2490{
2491 struct hdmi_spec *spec = codec->spec;
393004b2
ND		 2492 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2493
2494 switch (codec->preset->id) {
2495 case 0x10de0002:
2496 case 0x10de0003:
2497 case 0x10de0005:
2498 case 0x10de0006:
2499 hw_constraints_channels = &hw_constraints_2_8_channels;
2500 break;
2501 case 0x10de0007:
2502 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2503 break;
2504 default:
2505 break;
2506 }
2507
2508 if (hw_constraints_channels != NULL) {
2509 snd_pcm_hw_constraint_list(substream->runtime, 0,
2510 SNDRV_PCM_HW_PARAM_CHANNELS,
2511 hw_constraints_channels);
ad09fc9d
TI		 2512 } else {
2513 snd_pcm_hw_constraint_step(substream->runtime, 0,
2514 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
393004b2
ND		 2515 }
2516
84eb01be
TI		 2517 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2518}
2519
2520static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2521 struct hda_codec *codec,
2522 struct snd_pcm_substream *substream)
2523{
2524 struct hdmi_spec *spec = codec->spec;
2525 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2526}
2527
2528static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2529 struct hda_codec *codec,
2530 unsigned int stream_tag,
2531 unsigned int format,
2532 struct snd_pcm_substream *substream)
2533{
2534 struct hdmi_spec *spec = codec->spec;
2535 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2536 stream_tag, format, substream);
2537}
2538
d0b1252d
TI		 2539static const struct hda_pcm_stream simple_pcm_playback = {
2540 .substreams = 1,
2541 .channels_min = 2,
2542 .channels_max = 2,
2543 .ops = {
2544 .open = simple_playback_pcm_open,
2545 .close = simple_playback_pcm_close,
2546 .prepare = simple_playback_pcm_prepare
2547 },
2548};
2549
2550static const struct hda_codec_ops simple_hdmi_patch_ops = {
2551 .build_controls = simple_playback_build_controls,
2552 .build_pcms = simple_playback_build_pcms,
2553 .init = simple_playback_init,
2554 .free = simple_playback_free,
250e41ac 2555 .unsol_event = simple_hdmi_unsol_event,
d0b1252d
TI		 2556};
2557
2558static int patch_simple_hdmi(struct hda_codec *codec,
2559 hda_nid_t cvt_nid, hda_nid_t pin_nid)
2560{
2561 struct hdmi_spec *spec;
bce0d2a8
TI		 2562 struct hdmi_spec_per_cvt *per_cvt;
2563 struct hdmi_spec_per_pin *per_pin;
d0b1252d
TI		 2564
2565 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2566 if (!spec)
2567 return -ENOMEM;
2568
2569 codec->spec = spec;
bce0d2a8 2570 hdmi_array_init(spec, 1);
d0b1252d
TI		 2571
2572 spec->multiout.num_dacs = 0; /* no analog */
2573 spec->multiout.max_channels = 2;
2574 spec->multiout.dig_out_nid = cvt_nid;
2575 spec->num_cvts = 1;
2576 spec->num_pins = 1;
bce0d2a8
TI		 2577 per_pin = snd_array_new(&spec->pins);
2578 per_cvt = snd_array_new(&spec->cvts);
2579 if (!per_pin || !per_cvt) {
2580 simple_playback_free(codec);
2581 return -ENOMEM;
2582 }
2583 per_cvt->cvt_nid = cvt_nid;
2584 per_pin->pin_nid = pin_nid;
d0b1252d
TI		 2585 spec->pcm_playback = simple_pcm_playback;
2586
2587 codec->patch_ops = simple_hdmi_patch_ops;
2588
2589 return 0;
2590}
2591
1f348522
AP		 2592static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2593 int channels)
2594{
2595 unsigned int chanmask;
2596 int chan = channels ? (channels - 1) : 1;
2597
2598 switch (channels) {
2599 default:
2600 case 0:
2601 case 2:
2602 chanmask = 0x00;
2603 break;
2604 case 4:
2605 chanmask = 0x08;
2606 break;
2607 case 6:
2608 chanmask = 0x0b;
2609 break;
2610 case 8:
2611 chanmask = 0x13;
2612 break;
2613 }
2614
2615 /* Set the audio infoframe channel allocation and checksum fields. The
2616 * channel count is computed implicitly by the hardware. */
2617 snd_hda_codec_write(codec, 0x1, 0,
2618 Nv_VERB_SET_Channel_Allocation, chanmask);
2619
2620 snd_hda_codec_write(codec, 0x1, 0,
2621 Nv_VERB_SET_Info_Frame_Checksum,
2622 (0x71 - chan - chanmask));
2623}
2624
84eb01be
TI		 2625static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2626 struct hda_codec *codec,
2627 struct snd_pcm_substream *substream)
2628{
2629 struct hdmi_spec *spec = codec->spec;
2630 int i;
2631
2632 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2633 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2634 for (i = 0; i < 4; i++) {
2635 /* set the stream id */
2636 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2637 AC_VERB_SET_CHANNEL_STREAMID, 0);
2638 /* set the stream format */
2639 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2640 AC_VERB_SET_STREAM_FORMAT, 0);
2641 }
2642
1f348522
AP		 2643 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2644 * streams are disabled. */
2645 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2646
84eb01be
TI		 2647 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2648}
2649
2650static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2651 struct hda_codec *codec,
2652 unsigned int stream_tag,
2653 unsigned int format,
2654 struct snd_pcm_substream *substream)
2655{
2656 int chs;
112daa7a 2657 unsigned int dataDCC2, channel_id;
84eb01be 2658 int i;
7c935976 2659 struct hdmi_spec *spec = codec->spec;
e3245cdd 2660 struct hda_spdif_out *spdif;
bce0d2a8 2661 struct hdmi_spec_per_cvt *per_cvt;
84eb01be
TI		 2662
2663 mutex_lock(&codec->spdif_mutex);
bce0d2a8
TI		 2664 per_cvt = get_cvt(spec, 0);
2665 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
84eb01be
TI		 2666
2667 chs = substream->runtime->channels;
84eb01be 2668
84eb01be
TI		 2669 dataDCC2 = 0x2;
2670
84eb01be 2671 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
7c935976 2672 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 2673 snd_hda_codec_write(codec,
2674 nvhdmi_master_con_nid_7x,
2675 0,
2676 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2677 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 2678
2679 /* set the stream id */
2680 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2681 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
2682
2683 /* set the stream format */
2684 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2685 AC_VERB_SET_STREAM_FORMAT, format);
2686
2687 /* turn on again (if needed) */
2688 /* enable and set the channel status audio/data flag */
7c935976 2689 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 2690 snd_hda_codec_write(codec,
2691 nvhdmi_master_con_nid_7x,
2692 0,
2693 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2694 spdif->ctls & 0xff);
84eb01be
TI		 2695 snd_hda_codec_write(codec,
2696 nvhdmi_master_con_nid_7x,
2697 0,
2698 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2699 }
2700
2701 for (i = 0; i < 4; i++) {
2702 if (chs == 2)
2703 channel_id = 0;
2704 else
2705 channel_id = i * 2;
2706
2707 /* turn off SPDIF once;
2708 *otherwise the IEC958 bits won't be updated
2709 */
2710 if (codec->spdif_status_reset &&
7c935976 2711 (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 2712 snd_hda_codec_write(codec,
2713 nvhdmi_con_nids_7x[i],
2714 0,
2715 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2716 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 2717 /* set the stream id */
2718 snd_hda_codec_write(codec,
2719 nvhdmi_con_nids_7x[i],
2720 0,
2721 AC_VERB_SET_CHANNEL_STREAMID,
2722 (stream_tag << 4) | channel_id);
2723 /* set the stream format */
2724 snd_hda_codec_write(codec,
2725 nvhdmi_con_nids_7x[i],
2726 0,
2727 AC_VERB_SET_STREAM_FORMAT,
2728 format);
2729 /* turn on again (if needed) */
2730 /* enable and set the channel status audio/data flag */
2731 if (codec->spdif_status_reset &&
7c935976 2732 (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 2733 snd_hda_codec_write(codec,
2734 nvhdmi_con_nids_7x[i],
2735 0,
2736 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2737 spdif->ctls & 0xff);
84eb01be
TI		 2738 snd_hda_codec_write(codec,
2739 nvhdmi_con_nids_7x[i],
2740 0,
2741 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2742 }
2743 }
2744
1f348522 2745 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
84eb01be
TI		 2746
2747 mutex_unlock(&codec->spdif_mutex);
2748 return 0;
2749}
2750
fb79e1e0 2751static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
84eb01be
TI		 2752 .substreams = 1,
2753 .channels_min = 2,
2754 .channels_max = 8,
2755 .nid = nvhdmi_master_con_nid_7x,
2756 .rates = SUPPORTED_RATES,
2757 .maxbps = SUPPORTED_MAXBPS,
2758 .formats = SUPPORTED_FORMATS,
2759 .ops = {
2760 .open = simple_playback_pcm_open,
2761 .close = nvhdmi_8ch_7x_pcm_close,
2762 .prepare = nvhdmi_8ch_7x_pcm_prepare
2763 },
2764};
2765
84eb01be
TI		 2766static int patch_nvhdmi_2ch(struct hda_codec *codec)
2767{
2768 struct hdmi_spec *spec;
d0b1252d
TI		 2769 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
2770 nvhdmi_master_pin_nid_7x);
2771 if (err < 0)
2772 return err;
84eb01be 2773
ceaa86ba 2774 codec->patch_ops.init = nvhdmi_7x_init_2ch;
d0b1252d
TI		 2775 /* override the PCM rates, etc, as the codec doesn't give full list */
2776 spec = codec->spec;
2777 spec->pcm_playback.rates = SUPPORTED_RATES;
2778 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
2779 spec->pcm_playback.formats = SUPPORTED_FORMATS;
84eb01be
TI		 2780 return 0;
2781}
2782
53775b0d
TI		 2783static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
2784{
2785 struct hdmi_spec *spec = codec->spec;
2786 int err = simple_playback_build_pcms(codec);
bce0d2a8
TI		 2787 if (!err) {
2788 struct hda_pcm *info = get_pcm_rec(spec, 0);
2789 info->own_chmap = true;
2790 }
53775b0d
TI		 2791 return err;
2792}
2793
2794static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
2795{
2796 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2797 struct hda_pcm *info;
53775b0d
TI		 2798 struct snd_pcm_chmap *chmap;
2799 int err;
2800
2801 err = simple_playback_build_controls(codec);
2802 if (err < 0)
2803 return err;
2804
2805 /* add channel maps */
bce0d2a8
TI		 2806 info = get_pcm_rec(spec, 0);
2807 err = snd_pcm_add_chmap_ctls(info->pcm,
53775b0d
TI		 2808 SNDRV_PCM_STREAM_PLAYBACK,
2809 snd_pcm_alt_chmaps, 8, 0, &chmap);
2810 if (err < 0)
2811 return err;
2812 switch (codec->preset->id) {
2813 case 0x10de0002:
2814 case 0x10de0003:
2815 case 0x10de0005:
2816 case 0x10de0006:
2817 chmap->channel_mask = (1U << 2) | (1U << 8);
2818 break;
2819 case 0x10de0007:
2820 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
2821 }
2822 return 0;
2823}
2824
84eb01be
TI		 2825static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
2826{
2827 struct hdmi_spec *spec;
2828 int err = patch_nvhdmi_2ch(codec);
84eb01be
TI		 2829 if (err < 0)
2830 return err;
2831 spec = codec->spec;
2832 spec->multiout.max_channels = 8;
d0b1252d 2833 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
ceaa86ba 2834 codec->patch_ops.init = nvhdmi_7x_init_8ch;
53775b0d
TI		 2835 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
2836 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
1f348522
AP		 2837
2838 /* Initialize the audio infoframe channel mask and checksum to something
2839 * valid */
2840 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2841
84eb01be
TI		 2842 return 0;
2843}
2844
611885bc
AH		 2845/*
2846 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
2847 * - 0x10de0015
2848 * - 0x10de0040
2849 */
2850static int nvhdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
2851 int channels)
2852{
2853 if (cap->ca_index == 0x00 && channels == 2)
2854 return SNDRV_CTL_TLVT_CHMAP_FIXED;
2855
2856 return hdmi_chmap_cea_alloc_validate_get_type(cap, channels);
2857}
2858
2859static int nvhdmi_chmap_validate(int ca, int chs, unsigned char *map)
2860{
2861 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
2862 return -EINVAL;
2863
2864 return 0;
2865}
2866
2867static int patch_nvhdmi(struct hda_codec *codec)
2868{
2869 struct hdmi_spec *spec;
2870 int err;
2871
2872 err = patch_generic_hdmi(codec);
2873 if (err)
2874 return err;
2875
2876 spec = codec->spec;
75fae117 2877 spec->dyn_pin_out = true;
611885bc
AH		 2878
2879 spec->ops.chmap_cea_alloc_validate_get_type =
2880 nvhdmi_chmap_cea_alloc_validate_get_type;
2881 spec->ops.chmap_validate = nvhdmi_chmap_validate;
2882
2883 return 0;
2884}
2885
84eb01be 2886/*
5a613584 2887 * ATI/AMD-specific implementations
84eb01be
TI		 2888 */
2889
5a613584
AH		 2890#define is_amdhdmi_rev3_or_later(codec) \
2891 ((codec)->vendor_id == 0x1002aa01 && ((codec)->revision_id & 0xff00) >= 0x0300)
2892#define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
2893
2894/* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
2895#define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
2896#define ATI_VERB_SET_DOWNMIX_INFO 0x772
2897#define ATI_VERB_SET_MULTICHANNEL_01 0x777
2898#define ATI_VERB_SET_MULTICHANNEL_23 0x778
2899#define ATI_VERB_SET_MULTICHANNEL_45 0x779
2900#define ATI_VERB_SET_MULTICHANNEL_67 0x77a
461cf6b3 2901#define ATI_VERB_SET_HBR_CONTROL 0x77c
5a613584
AH		 2902#define ATI_VERB_SET_MULTICHANNEL_1 0x785
2903#define ATI_VERB_SET_MULTICHANNEL_3 0x786
2904#define ATI_VERB_SET_MULTICHANNEL_5 0x787
2905#define ATI_VERB_SET_MULTICHANNEL_7 0x788
2906#define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
2907#define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
2908#define ATI_VERB_GET_DOWNMIX_INFO 0xf72
2909#define ATI_VERB_GET_MULTICHANNEL_01 0xf77
2910#define ATI_VERB_GET_MULTICHANNEL_23 0xf78
2911#define ATI_VERB_GET_MULTICHANNEL_45 0xf79
2912#define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
461cf6b3 2913#define ATI_VERB_GET_HBR_CONTROL 0xf7c
5a613584
AH		 2914#define ATI_VERB_GET_MULTICHANNEL_1 0xf85
2915#define ATI_VERB_GET_MULTICHANNEL_3 0xf86
2916#define ATI_VERB_GET_MULTICHANNEL_5 0xf87
2917#define ATI_VERB_GET_MULTICHANNEL_7 0xf88
2918#define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
2919
84d69e79
AH		 2920/* AMD specific HDA cvt verbs */
2921#define ATI_VERB_SET_RAMP_RATE 0x770
2922#define ATI_VERB_GET_RAMP_RATE 0xf70
2923
5a613584
AH		 2924#define ATI_OUT_ENABLE 0x1
2925
2926#define ATI_MULTICHANNEL_MODE_PAIRED 0
2927#define ATI_MULTICHANNEL_MODE_SINGLE 1
2928
461cf6b3
AH		 2929#define ATI_HBR_CAPABLE 0x01
2930#define ATI_HBR_ENABLE 0x10
2931
89250f84
AH		 2932static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
2933 unsigned char *buf, int *eld_size)
2934{
2935 /* call hda_eld.c ATI/AMD-specific function */
2936 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
2937 is_amdhdmi_rev3_or_later(codec));
2938}
2939
5a613584
AH		 2940static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
2941 int active_channels, int conn_type)
2942{
2943 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
2944}
2945
2946static int atihdmi_paired_swap_fc_lfe(int pos)
2947{
2948 /*
2949 * ATI/AMD have automatic FC/LFE swap built-in
2950 * when in pairwise mapping mode.
2951 */
2952
2953 switch (pos) {
2954 /* see channel_allocations[].speakers[] */
2955 case 2: return 3;
2956 case 3: return 2;
2957 default: break;
2958 }
2959
2960 return pos;
2961}
2962
2963static int atihdmi_paired_chmap_validate(int ca, int chs, unsigned char *map)
2964{
2965 struct cea_channel_speaker_allocation *cap;
2966 int i, j;
2967
2968 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
2969
2970 cap = &channel_allocations[get_channel_allocation_order(ca)];
2971 for (i = 0; i < chs; ++i) {
2972 int mask = to_spk_mask(map[i]);
2973 bool ok = false;
2974 bool companion_ok = false;
2975
2976 if (!mask)
2977 continue;
2978
2979 for (j = 0 + i % 2; j < 8; j += 2) {
2980 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
2981 if (cap->speakers[chan_idx] == mask) {
2982 /* channel is in a supported position */
2983 ok = true;
2984
2985 if (i % 2 == 0 && i + 1 < chs) {
2986 /* even channel, check the odd companion */
2987 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
2988 int comp_mask_req = to_spk_mask(map[i+1]);
2989 int comp_mask_act = cap->speakers[comp_chan_idx];
2990
2991 if (comp_mask_req == comp_mask_act)
2992 companion_ok = true;
2993 else
2994 return -EINVAL;
2995 }
2996 break;
2997 }
2998 }
2999
3000 if (!ok)
3001 return -EINVAL;
3002
3003 if (companion_ok)
3004 i++; /* companion channel already checked */
3005 }
3006
3007 return 0;
3008}
3009
3010static int atihdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
3011 int hdmi_slot, int stream_channel)
3012{
3013 int verb;
3014 int ati_channel_setup = 0;
3015
3016 if (hdmi_slot > 7)
3017 return -EINVAL;
3018
3019 if (!has_amd_full_remap_support(codec)) {
3020 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3021
3022 /* In case this is an odd slot but without stream channel, do not
3023 * disable the slot since the corresponding even slot could have a
3024 * channel. In case neither have a channel, the slot pair will be
3025 * disabled when this function is called for the even slot. */
3026 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3027 return 0;
3028
3029 hdmi_slot -= hdmi_slot % 2;
3030
3031 if (stream_channel != 0xf)
3032 stream_channel -= stream_channel % 2;
3033 }
3034
3035 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3036
3037 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3038
3039 if (stream_channel != 0xf)
3040 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3041
3042 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3043}
3044
3045static int atihdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
3046 int asp_slot)
3047{
3048 bool was_odd = false;
3049 int ati_asp_slot = asp_slot;
3050 int verb;
3051 int ati_channel_setup;
3052
3053 if (asp_slot > 7)
3054 return -EINVAL;
3055
3056 if (!has_amd_full_remap_support(codec)) {
3057 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3058 if (ati_asp_slot % 2 != 0) {
3059 ati_asp_slot -= 1;
3060 was_odd = true;
3061 }
3062 }
3063
3064 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3065
3066 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3067
3068 if (!(ati_channel_setup & ATI_OUT_ENABLE))
3069 return 0xf;
3070
3071 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3072}
84eb01be 3073
5a613584
AH		 3074static int atihdmi_paired_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
3075 int channels)
3076{
3077 int c;
3078
3079 /*
3080 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3081 * we need to take that into account (a single channel may take 2
3082 * channel slots if we need to carry a silent channel next to it).
3083 * On Rev3+ AMD codecs this function is not used.
3084 */
3085 int chanpairs = 0;
3086
3087 /* We only produce even-numbered channel count TLVs */
3088 if ((channels % 2) != 0)
3089 return -1;
3090
3091 for (c = 0; c < 7; c += 2) {
3092 if (cap->speakers[c] || cap->speakers[c+1])
3093 chanpairs++;
3094 }
3095
3096 if (chanpairs * 2 != channels)
3097 return -1;
3098
3099 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3100}
3101
3102static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
3103 unsigned int *chmap, int channels)
3104{
3105 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3106 int count = 0;
3107 int c;
3108
3109 for (c = 7; c >= 0; c--) {
3110 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3111 int spk = cap->speakers[chan];
3112 if (!spk) {
3113 /* add N/A channel if the companion channel is occupied */
3114 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3115 chmap[count++] = SNDRV_CHMAP_NA;
3116
3117 continue;
3118 }
3119
3120 chmap[count++] = spk_to_chmap(spk);
3121 }
3122
3123 WARN_ON(count != channels);
3124}
3125
461cf6b3
AH		 3126static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3127 bool hbr)
3128{
3129 int hbr_ctl, hbr_ctl_new;
3130
3131 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
13122e6e 3132 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
461cf6b3
AH		 3133 if (hbr)
3134 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3135 else
3136 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3137
4e76a883
TI		 3138 codec_dbg(codec,
3139 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
461cf6b3
AH		 3140 pin_nid,
3141 hbr_ctl == hbr_ctl_new ? "" : "new-",
3142 hbr_ctl_new);
3143
3144 if (hbr_ctl != hbr_ctl_new)
3145 snd_hda_codec_write(codec, pin_nid, 0,
3146 ATI_VERB_SET_HBR_CONTROL,
3147 hbr_ctl_new);
3148
3149 } else if (hbr)
3150 return -EINVAL;
3151
3152 return 0;
3153}
3154
84d69e79
AH		 3155static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3156 hda_nid_t pin_nid, u32 stream_tag, int format)
3157{
3158
3159 if (is_amdhdmi_rev3_or_later(codec)) {
3160 int ramp_rate = 180; /* default as per AMD spec */
3161 /* disable ramp-up/down for non-pcm as per AMD spec */
3162 if (format & AC_FMT_TYPE_NON_PCM)
3163 ramp_rate = 0;
3164
3165 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3166 }
3167
3168 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3169}
3170
3171
5a613584 3172static int atihdmi_init(struct hda_codec *codec)
84eb01be
TI		 3173{
3174 struct hdmi_spec *spec = codec->spec;
5a613584 3175 int pin_idx, err;
84eb01be 3176
5a613584
AH		 3177 err = generic_hdmi_init(codec);
3178
3179 if (err)
84eb01be 3180 return err;
5a613584
AH		 3181
3182 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3183 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3184
3185 /* make sure downmix information in infoframe is zero */
3186 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3187
3188 /* enable channel-wise remap mode if supported */
3189 if (has_amd_full_remap_support(codec))
3190 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3191 ATI_VERB_SET_MULTICHANNEL_MODE,
3192 ATI_MULTICHANNEL_MODE_SINGLE);
84eb01be 3193 }
5a613584 3194
84eb01be
TI		 3195 return 0;
3196}
3197
84eb01be
TI		 3198static int patch_atihdmi(struct hda_codec *codec)
3199{
3200 struct hdmi_spec *spec;
5a613584
AH		 3201 struct hdmi_spec_per_cvt *per_cvt;
3202 int err, cvt_idx;
3203
3204 err = patch_generic_hdmi(codec);
3205
3206 if (err)
d0b1252d 3207 return err;
5a613584
AH		 3208
3209 codec->patch_ops.init = atihdmi_init;
3210
d0b1252d 3211 spec = codec->spec;
5a613584 3212
89250f84 3213 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
5a613584
AH		 3214 spec->ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
3215 spec->ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
3216 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
461cf6b3 3217 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
84d69e79 3218 spec->ops.setup_stream = atihdmi_setup_stream;
5a613584
AH		 3219
3220 if (!has_amd_full_remap_support(codec)) {
3221 /* override to ATI/AMD-specific versions with pairwise mapping */
3222 spec->ops.chmap_cea_alloc_validate_get_type =
3223 atihdmi_paired_chmap_cea_alloc_validate_get_type;
3224 spec->ops.cea_alloc_to_tlv_chmap = atihdmi_paired_cea_alloc_to_tlv_chmap;
3225 spec->ops.chmap_validate = atihdmi_paired_chmap_validate;
3226 }
3227
3228 /* ATI/AMD converters do not advertise all of their capabilities */
3229 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
3230 per_cvt = get_cvt(spec, cvt_idx);
3231 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
3232 per_cvt->rates |= SUPPORTED_RATES;
3233 per_cvt->formats |= SUPPORTED_FORMATS;
3234 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
3235 }
3236
3237 spec->channels_max = max(spec->channels_max, 8u);
3238
84eb01be
TI		 3239 return 0;
3240}
3241
3de5ff88
AL		 3242/* VIA HDMI Implementation */
3243#define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
3244#define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
3245
3de5ff88
AL		 3246static int patch_via_hdmi(struct hda_codec *codec)
3247{
250e41ac 3248 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3de5ff88 3249}
84eb01be 3250
f0639272
TI		 3251/*
3252 * called from hda_codec.c for generic HDMI support
3253 */
3254int snd_hda_parse_hdmi_codec(struct hda_codec *codec)
3255{
3256 return patch_generic_hdmi(codec);
3257}
2698ea98 3258EXPORT_SYMBOL_GPL(snd_hda_parse_hdmi_codec);
f0639272 3259
84eb01be
TI		 3260/*
3261 * patch entries
3262 */
fb79e1e0 3263static const struct hda_codec_preset snd_hda_preset_hdmi[] = {
84eb01be
TI		 3264{ .id = 0x1002793c, .name = "RS600 HDMI", .patch = patch_atihdmi },
3265{ .id = 0x10027919, .name = "RS600 HDMI", .patch = patch_atihdmi },
3266{ .id = 0x1002791a, .name = "RS690/780 HDMI", .patch = patch_atihdmi },
5a613584 3267{ .id = 0x1002aa01, .name = "R6xx HDMI", .patch = patch_atihdmi },
84eb01be
TI		 3268{ .id = 0x10951390, .name = "SiI1390 HDMI", .patch = patch_generic_hdmi },
3269{ .id = 0x10951392, .name = "SiI1392 HDMI", .patch = patch_generic_hdmi },
3270{ .id = 0x17e80047, .name = "Chrontel HDMI", .patch = patch_generic_hdmi },
3271{ .id = 0x10de0002, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3272{ .id = 0x10de0003, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3273{ .id = 0x10de0005, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3274{ .id = 0x10de0006, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3275{ .id = 0x10de0007, .name = "MCP79/7A HDMI", .patch = patch_nvhdmi_8ch_7x },
611885bc
AH		 3276{ .id = 0x10de000a, .name = "GPU 0a HDMI/DP", .patch = patch_nvhdmi },
3277{ .id = 0x10de000b, .name = "GPU 0b HDMI/DP", .patch = patch_nvhdmi },
3278{ .id = 0x10de000c, .name = "MCP89 HDMI", .patch = patch_nvhdmi },
3279{ .id = 0x10de000d, .name = "GPU 0d HDMI/DP", .patch = patch_nvhdmi },
3280{ .id = 0x10de0010, .name = "GPU 10 HDMI/DP", .patch = patch_nvhdmi },
3281{ .id = 0x10de0011, .name = "GPU 11 HDMI/DP", .patch = patch_nvhdmi },
3282{ .id = 0x10de0012, .name = "GPU 12 HDMI/DP", .patch = patch_nvhdmi },
3283{ .id = 0x10de0013, .name = "GPU 13 HDMI/DP", .patch = patch_nvhdmi },
3284{ .id = 0x10de0014, .name = "GPU 14 HDMI/DP", .patch = patch_nvhdmi },
3285{ .id = 0x10de0015, .name = "GPU 15 HDMI/DP", .patch = patch_nvhdmi },
3286{ .id = 0x10de0016, .name = "GPU 16 HDMI/DP", .patch = patch_nvhdmi },
c8900a0f 3287/* 17 is known to be absent */
611885bc
AH		 3288{ .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_nvhdmi },
3289{ .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_nvhdmi },
3290{ .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_nvhdmi },
3291{ .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_nvhdmi },
3292{ .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_nvhdmi },
3293{ .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_nvhdmi },
3294{ .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_nvhdmi },
3295{ .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_nvhdmi },
3296{ .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_nvhdmi },
3297{ .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_nvhdmi },
3298{ .id = 0x10de0051, .name = "GPU 51 HDMI/DP", .patch = patch_nvhdmi },
3299{ .id = 0x10de0060, .name = "GPU 60 HDMI/DP", .patch = patch_nvhdmi },
84eb01be
TI		 3300{ .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch },
3301{ .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch },
3de5ff88
AL		 3302{ .id = 0x11069f80, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
3303{ .id = 0x11069f81, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
3304{ .id = 0x11069f84, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
3305{ .id = 0x11069f85, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
84eb01be
TI		 3306{ .id = 0x80860054, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
3307{ .id = 0x80862801, .name = "Bearlake HDMI", .patch = patch_generic_hdmi },
3308{ .id = 0x80862802, .name = "Cantiga HDMI", .patch = patch_generic_hdmi },
3309{ .id = 0x80862803, .name = "Eaglelake HDMI", .patch = patch_generic_hdmi },
3310{ .id = 0x80862804, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
3311{ .id = 0x80862805, .name = "CougarPoint HDMI", .patch = patch_generic_hdmi },
591e610d 3312{ .id = 0x80862806, .name = "PantherPoint HDMI", .patch = patch_generic_hdmi },
1c76684d 3313{ .id = 0x80862807, .name = "Haswell HDMI", .patch = patch_generic_hdmi },
3adadd28 3314{ .id = 0x80862808, .name = "Broadwell HDMI", .patch = patch_generic_hdmi },
6edc59e6 3315{ .id = 0x80862880, .name = "CedarTrail HDMI", .patch = patch_generic_hdmi },
cc1a95d9 3316{ .id = 0x80862882, .name = "Valleyview2 HDMI", .patch = patch_generic_hdmi },
84eb01be
TI		 3317{ .id = 0x808629fb, .name = "Crestline HDMI", .patch = patch_generic_hdmi },
3318{} /* terminator */
3319};
3320
3321MODULE_ALIAS("snd-hda-codec-id:1002793c");
3322MODULE_ALIAS("snd-hda-codec-id:10027919");
3323MODULE_ALIAS("snd-hda-codec-id:1002791a");
3324MODULE_ALIAS("snd-hda-codec-id:1002aa01");
3325MODULE_ALIAS("snd-hda-codec-id:10951390");
3326MODULE_ALIAS("snd-hda-codec-id:10951392");
3327MODULE_ALIAS("snd-hda-codec-id:10de0002");
3328MODULE_ALIAS("snd-hda-codec-id:10de0003");
3329MODULE_ALIAS("snd-hda-codec-id:10de0005");
3330MODULE_ALIAS("snd-hda-codec-id:10de0006");
3331MODULE_ALIAS("snd-hda-codec-id:10de0007");
3332MODULE_ALIAS("snd-hda-codec-id:10de000a");
3333MODULE_ALIAS("snd-hda-codec-id:10de000b");
3334MODULE_ALIAS("snd-hda-codec-id:10de000c");
3335MODULE_ALIAS("snd-hda-codec-id:10de000d");
3336MODULE_ALIAS("snd-hda-codec-id:10de0010");
3337MODULE_ALIAS("snd-hda-codec-id:10de0011");
3338MODULE_ALIAS("snd-hda-codec-id:10de0012");
3339MODULE_ALIAS("snd-hda-codec-id:10de0013");
3340MODULE_ALIAS("snd-hda-codec-id:10de0014");
c8900a0f
RS		 3341MODULE_ALIAS("snd-hda-codec-id:10de0015");
3342MODULE_ALIAS("snd-hda-codec-id:10de0016");
84eb01be
TI		 3343MODULE_ALIAS("snd-hda-codec-id:10de0018");
3344MODULE_ALIAS("snd-hda-codec-id:10de0019");
3345MODULE_ALIAS("snd-hda-codec-id:10de001a");
3346MODULE_ALIAS("snd-hda-codec-id:10de001b");
3347MODULE_ALIAS("snd-hda-codec-id:10de001c");
3348MODULE_ALIAS("snd-hda-codec-id:10de0040");
3349MODULE_ALIAS("snd-hda-codec-id:10de0041");
3350MODULE_ALIAS("snd-hda-codec-id:10de0042");
3351MODULE_ALIAS("snd-hda-codec-id:10de0043");
3352MODULE_ALIAS("snd-hda-codec-id:10de0044");
7ae48b56 3353MODULE_ALIAS("snd-hda-codec-id:10de0051");
d52392b1 3354MODULE_ALIAS("snd-hda-codec-id:10de0060");
84eb01be
TI		 3355MODULE_ALIAS("snd-hda-codec-id:10de0067");
3356MODULE_ALIAS("snd-hda-codec-id:10de8001");
3de5ff88
AL		 3357MODULE_ALIAS("snd-hda-codec-id:11069f80");
3358MODULE_ALIAS("snd-hda-codec-id:11069f81");
3359MODULE_ALIAS("snd-hda-codec-id:11069f84");
3360MODULE_ALIAS("snd-hda-codec-id:11069f85");
84eb01be
TI		 3361MODULE_ALIAS("snd-hda-codec-id:17e80047");
3362MODULE_ALIAS("snd-hda-codec-id:80860054");
3363MODULE_ALIAS("snd-hda-codec-id:80862801");
3364MODULE_ALIAS("snd-hda-codec-id:80862802");
3365MODULE_ALIAS("snd-hda-codec-id:80862803");
3366MODULE_ALIAS("snd-hda-codec-id:80862804");
3367MODULE_ALIAS("snd-hda-codec-id:80862805");
591e610d 3368MODULE_ALIAS("snd-hda-codec-id:80862806");
1c76684d 3369MODULE_ALIAS("snd-hda-codec-id:80862807");
3adadd28 3370MODULE_ALIAS("snd-hda-codec-id:80862808");
6edc59e6 3371MODULE_ALIAS("snd-hda-codec-id:80862880");
cc1a95d9 3372MODULE_ALIAS("snd-hda-codec-id:80862882");
84eb01be
TI		 3373MODULE_ALIAS("snd-hda-codec-id:808629fb");
3374
3375MODULE_LICENSE("GPL");
3376MODULE_DESCRIPTION("HDMI HD-audio codec");
3377MODULE_ALIAS("snd-hda-codec-intelhdmi");
3378MODULE_ALIAS("snd-hda-codec-nvhdmi");
3379MODULE_ALIAS("snd-hda-codec-atihdmi");
3380
3381static struct hda_codec_preset_list intel_list = {
3382 .preset = snd_hda_preset_hdmi,
3383 .owner = THIS_MODULE,
3384};
3385
3386static int __init patch_hdmi_init(void)
3387{
3388 return snd_hda_add_codec_preset(&intel_list);
3389}
3390
3391static void __exit patch_hdmi_exit(void)
3392{
3393 snd_hda_delete_codec_preset(&intel_list);
3394}
3395
3396module_init(patch_hdmi_init)
3397module_exit(patch_hdmi_exit)
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