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Commit | Line | Data |
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1a59d1b8 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
079d88cc WF |
2 | /* |
3 | * | |
4 | * patch_hdmi.c - routines for HDMI/DisplayPort codecs | |
5 | * | |
6 | * Copyright(c) 2008-2010 Intel Corporation. All rights reserved. | |
84eb01be TI |
7 | * Copyright (c) 2006 ATI Technologies Inc. |
8 | * Copyright (c) 2008 NVIDIA Corp. All rights reserved. | |
9 | * Copyright (c) 2008 Wei Ni <wni@nvidia.com> | |
5a613584 | 10 | * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi> |
079d88cc WF |
11 | * |
12 | * Authors: | |
13 | * Wu Fengguang <wfg@linux.intel.com> | |
14 | * | |
15 | * Maintained by: | |
16 | * Wu Fengguang <wfg@linux.intel.com> | |
079d88cc WF |
17 | */ |
18 | ||
84eb01be TI |
19 | #include <linux/init.h> |
20 | #include <linux/delay.h> | |
ade49db3 | 21 | #include <linux/pci.h> |
84eb01be | 22 | #include <linux/slab.h> |
65a77217 | 23 | #include <linux/module.h> |
aaa23f86 | 24 | #include <linux/pm_runtime.h> |
84eb01be | 25 | #include <sound/core.h> |
07acecc1 | 26 | #include <sound/jack.h> |
433968da | 27 | #include <sound/asoundef.h> |
d45e6889 | 28 | #include <sound/tlv.h> |
25adc137 DH |
29 | #include <sound/hdaudio.h> |
30 | #include <sound/hda_i915.h> | |
67b90cb8 | 31 | #include <sound/hda_chmap.h> |
be57bfff | 32 | #include <sound/hda_codec.h> |
84eb01be | 33 | #include "hda_local.h" |
1835a0f9 | 34 | #include "hda_jack.h" |
e38e486d | 35 | #include "hda_controller.h" |
84eb01be | 36 | |
0ebaa24c TI |
37 | static bool static_hdmi_pcm; |
38 | module_param(static_hdmi_pcm, bool, 0644); | |
39 | MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info"); | |
40 | ||
b392350e TI |
41 | static bool enable_acomp = true; |
42 | module_param(enable_acomp, bool, 0444); | |
43 | MODULE_PARM_DESC(enable_acomp, "Enable audio component binding (default=yes)"); | |
44 | ||
384a48d7 SW |
45 | struct hdmi_spec_per_cvt { |
46 | hda_nid_t cvt_nid; | |
47 | int assigned; | |
48 | unsigned int channels_min; | |
49 | unsigned int channels_max; | |
50 | u32 rates; | |
51 | u64 formats; | |
52 | unsigned int maxbps; | |
53 | }; | |
079d88cc | 54 | |
4eea3091 TI |
55 | /* max. connections to a widget */ |
56 | #define HDA_MAX_CONNECTIONS 32 | |
57 | ||
384a48d7 SW |
58 | struct hdmi_spec_per_pin { |
59 | hda_nid_t pin_nid; | |
9152085d | 60 | int dev_id; |
a76056f2 LY |
61 | /* pin idx, different device entries on the same pin use the same idx */ |
62 | int pin_nid_idx; | |
384a48d7 SW |
63 | int num_mux_nids; |
64 | hda_nid_t mux_nids[HDA_MAX_CONNECTIONS]; | |
2df6742f | 65 | int mux_idx; |
1df5a06a | 66 | hda_nid_t cvt_nid; |
744626da WF |
67 | |
68 | struct hda_codec *codec; | |
384a48d7 | 69 | struct hdmi_eld sink_eld; |
a4e9a38b | 70 | struct mutex lock; |
744626da | 71 | struct delayed_work work; |
2bea241a | 72 | struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/ |
a76056f2 | 73 | int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */ |
c6e8453e | 74 | int repoll_count; |
b054087d TI |
75 | bool setup; /* the stream has been set up by prepare callback */ |
76 | int channels; /* current number of channels */ | |
1a6003b5 | 77 | bool non_pcm; |
d45e6889 TI |
78 | bool chmap_set; /* channel-map override by ALSA API? */ |
79 | unsigned char chmap[8]; /* ALSA API channel-map */ | |
cd6a6503 | 80 | #ifdef CONFIG_SND_PROC_FS |
a4e9a38b TI |
81 | struct snd_info_entry *proc_entry; |
82 | #endif | |
384a48d7 | 83 | }; |
079d88cc | 84 | |
307229d2 AH |
85 | /* operations used by generic code that can be overridden by patches */ |
86 | struct hdmi_ops { | |
87 | int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid, | |
9c32fea8 | 88 | int dev_id, unsigned char *buf, int *eld_size); |
307229d2 | 89 | |
307229d2 | 90 | void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid, |
9c32fea8 | 91 | int dev_id, |
307229d2 AH |
92 | int ca, int active_channels, int conn_type); |
93 | ||
94 | /* enable/disable HBR (HD passthrough) */ | |
9c32fea8 NM |
95 | int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, |
96 | int dev_id, bool hbr); | |
307229d2 AH |
97 | |
98 | int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid, | |
9c32fea8 NM |
99 | hda_nid_t pin_nid, int dev_id, u32 stream_tag, |
100 | int format); | |
307229d2 | 101 | |
4846a67e TI |
102 | void (*pin_cvt_fixup)(struct hda_codec *codec, |
103 | struct hdmi_spec_per_pin *per_pin, | |
104 | hda_nid_t cvt_nid); | |
307229d2 AH |
105 | }; |
106 | ||
2bea241a LY |
107 | struct hdmi_pcm { |
108 | struct hda_pcm *pcm; | |
109 | struct snd_jack *jack; | |
fb087eaa | 110 | struct snd_kcontrol *eld_ctl; |
2bea241a LY |
111 | }; |
112 | ||
384a48d7 | 113 | struct hdmi_spec { |
ade49db3 | 114 | struct hda_codec *codec; |
384a48d7 | 115 | int num_cvts; |
bce0d2a8 TI |
116 | struct snd_array cvts; /* struct hdmi_spec_per_cvt */ |
117 | hda_nid_t cvt_nids[4]; /* only for haswell fix */ | |
079d88cc | 118 | |
9152085d LY |
119 | /* |
120 | * num_pins is the number of virtual pins | |
121 | * for example, there are 3 pins, and each pin | |
122 | * has 4 device entries, then the num_pins is 12 | |
123 | */ | |
384a48d7 | 124 | int num_pins; |
9152085d LY |
125 | /* |
126 | * num_nids is the number of real pins | |
127 | * In the above example, num_nids is 3 | |
128 | */ | |
129 | int num_nids; | |
130 | /* | |
131 | * dev_num is the number of device entries | |
132 | * on each pin. | |
133 | * In the above example, dev_num is 4 | |
134 | */ | |
135 | int dev_num; | |
bce0d2a8 | 136 | struct snd_array pins; /* struct hdmi_spec_per_pin */ |
2bea241a | 137 | struct hdmi_pcm pcm_rec[16]; |
42b29870 | 138 | struct mutex pcm_lock; |
302d5a80 | 139 | struct mutex bind_lock; /* for audio component binding */ |
a76056f2 LY |
140 | /* pcm_bitmap means which pcms have been assigned to pins*/ |
141 | unsigned long pcm_bitmap; | |
2bf3c85a | 142 | int pcm_used; /* counter of pcm_rec[] */ |
ac98379a LY |
143 | /* bitmap shows whether the pcm is opened in user space |
144 | * bit 0 means the first playback PCM (PCM3); | |
145 | * bit 1 means the second playback PCM, and so on. | |
146 | */ | |
147 | unsigned long pcm_in_use; | |
079d88cc | 148 | |
4bd038f9 | 149 | struct hdmi_eld temp_eld; |
307229d2 | 150 | struct hdmi_ops ops; |
75fae117 SW |
151 | |
152 | bool dyn_pin_out; | |
6590faab | 153 | bool dyn_pcm_assign; |
cb45722b | 154 | bool intel_hsw_fixup; /* apply Intel platform-specific fixups */ |
079d88cc | 155 | /* |
5a613584 | 156 | * Non-generic VIA/NVIDIA specific |
079d88cc WF |
157 | */ |
158 | struct hda_multi_out multiout; | |
d0b1252d | 159 | struct hda_pcm_stream pcm_playback; |
25adc137 | 160 | |
ade49db3 TI |
161 | bool use_acomp_notifier; /* use eld_notify callback for hotplug */ |
162 | bool acomp_registered; /* audio component registered in this driver */ | |
ae891abe | 163 | struct drm_audio_component_audio_ops drm_audio_ops; |
ade49db3 | 164 | int (*port2pin)(struct hda_codec *, int); /* reverse port/pin mapping */ |
67b90cb8 SP |
165 | |
166 | struct hdac_chmap chmap; | |
a87a4d23 | 167 | hda_nid_t vendor_nid; |
b0d8bc50 JK |
168 | const int *port_map; |
169 | int port_num; | |
079d88cc WF |
170 | }; |
171 | ||
a57942bf | 172 | #ifdef CONFIG_SND_HDA_COMPONENT |
691be973 TI |
173 | static inline bool codec_has_acomp(struct hda_codec *codec) |
174 | { | |
175 | struct hdmi_spec *spec = codec->spec; | |
176 | return spec->use_acomp_notifier; | |
177 | } | |
f4e3040b TI |
178 | #else |
179 | #define codec_has_acomp(codec) false | |
180 | #endif | |
079d88cc WF |
181 | |
182 | struct hdmi_audio_infoframe { | |
183 | u8 type; /* 0x84 */ | |
184 | u8 ver; /* 0x01 */ | |
185 | u8 len; /* 0x0a */ | |
186 | ||
53d7d69d WF |
187 | u8 checksum; |
188 | ||
079d88cc WF |
189 | u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */ |
190 | u8 SS01_SF24; | |
191 | u8 CXT04; | |
192 | u8 CA; | |
193 | u8 LFEPBL01_LSV36_DM_INH7; | |
53d7d69d WF |
194 | }; |
195 | ||
196 | struct dp_audio_infoframe { | |
197 | u8 type; /* 0x84 */ | |
198 | u8 len; /* 0x1b */ | |
199 | u8 ver; /* 0x11 << 2 */ | |
200 | ||
201 | u8 CC02_CT47; /* match with HDMI infoframe from this on */ | |
202 | u8 SS01_SF24; | |
203 | u8 CXT04; | |
204 | u8 CA; | |
205 | u8 LFEPBL01_LSV36_DM_INH7; | |
079d88cc WF |
206 | }; |
207 | ||
2b203dbb TI |
208 | union audio_infoframe { |
209 | struct hdmi_audio_infoframe hdmi; | |
210 | struct dp_audio_infoframe dp; | |
211 | u8 bytes[0]; | |
212 | }; | |
213 | ||
079d88cc WF |
214 | /* |
215 | * HDMI routines | |
216 | */ | |
217 | ||
bce0d2a8 TI |
218 | #define get_pin(spec, idx) \ |
219 | ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx)) | |
220 | #define get_cvt(spec, idx) \ | |
221 | ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx)) | |
2bea241a LY |
222 | /* obtain hdmi_pcm object assigned to idx */ |
223 | #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx]) | |
224 | /* obtain hda_pcm object assigned to idx */ | |
225 | #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm) | |
bce0d2a8 | 226 | |
9152085d LY |
227 | static int pin_id_to_pin_index(struct hda_codec *codec, |
228 | hda_nid_t pin_nid, int dev_id) | |
079d88cc | 229 | { |
4e76a883 | 230 | struct hdmi_spec *spec = codec->spec; |
384a48d7 | 231 | int pin_idx; |
9152085d | 232 | struct hdmi_spec_per_pin *per_pin; |
079d88cc | 233 | |
9152085d LY |
234 | /* |
235 | * (dev_id == -1) means it is NON-MST pin | |
236 | * return the first virtual pin on this port | |
237 | */ | |
238 | if (dev_id == -1) | |
239 | dev_id = 0; | |
240 | ||
241 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { | |
242 | per_pin = get_pin(spec, pin_idx); | |
243 | if ((per_pin->pin_nid == pin_nid) && | |
244 | (per_pin->dev_id == dev_id)) | |
384a48d7 | 245 | return pin_idx; |
9152085d | 246 | } |
079d88cc | 247 | |
4e76a883 | 248 | codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid); |
384a48d7 SW |
249 | return -EINVAL; |
250 | } | |
251 | ||
2bf3c85a LY |
252 | static int hinfo_to_pcm_index(struct hda_codec *codec, |
253 | struct hda_pcm_stream *hinfo) | |
254 | { | |
255 | struct hdmi_spec *spec = codec->spec; | |
256 | int pcm_idx; | |
257 | ||
258 | for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) | |
259 | if (get_pcm_rec(spec, pcm_idx)->stream == hinfo) | |
260 | return pcm_idx; | |
261 | ||
262 | codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo); | |
263 | return -EINVAL; | |
264 | } | |
265 | ||
4e76a883 | 266 | static int hinfo_to_pin_index(struct hda_codec *codec, |
384a48d7 SW |
267 | struct hda_pcm_stream *hinfo) |
268 | { | |
4e76a883 | 269 | struct hdmi_spec *spec = codec->spec; |
6590faab | 270 | struct hdmi_spec_per_pin *per_pin; |
384a48d7 SW |
271 | int pin_idx; |
272 | ||
6590faab LY |
273 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { |
274 | per_pin = get_pin(spec, pin_idx); | |
2bea241a LY |
275 | if (per_pin->pcm && |
276 | per_pin->pcm->pcm->stream == hinfo) | |
384a48d7 | 277 | return pin_idx; |
6590faab | 278 | } |
384a48d7 | 279 | |
6590faab | 280 | codec_dbg(codec, "HDMI: hinfo %p not registered\n", hinfo); |
384a48d7 SW |
281 | return -EINVAL; |
282 | } | |
283 | ||
022f344b LY |
284 | static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec, |
285 | int pcm_idx) | |
286 | { | |
287 | int i; | |
288 | struct hdmi_spec_per_pin *per_pin; | |
289 | ||
290 | for (i = 0; i < spec->num_pins; i++) { | |
291 | per_pin = get_pin(spec, i); | |
292 | if (per_pin->pcm_idx == pcm_idx) | |
293 | return per_pin; | |
294 | } | |
295 | return NULL; | |
296 | } | |
297 | ||
4e76a883 | 298 | static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid) |
384a48d7 | 299 | { |
4e76a883 | 300 | struct hdmi_spec *spec = codec->spec; |
384a48d7 SW |
301 | int cvt_idx; |
302 | ||
303 | for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) | |
bce0d2a8 | 304 | if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid) |
384a48d7 SW |
305 | return cvt_idx; |
306 | ||
4e76a883 | 307 | codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid); |
079d88cc WF |
308 | return -EINVAL; |
309 | } | |
310 | ||
14bc52b8 PLB |
311 | static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol, |
312 | struct snd_ctl_elem_info *uinfo) | |
313 | { | |
314 | struct hda_codec *codec = snd_kcontrol_chip(kcontrol); | |
68e03de9 | 315 | struct hdmi_spec *spec = codec->spec; |
a4e9a38b | 316 | struct hdmi_spec_per_pin *per_pin; |
68e03de9 | 317 | struct hdmi_eld *eld; |
fb087eaa | 318 | int pcm_idx; |
14bc52b8 | 319 | |
14bc52b8 PLB |
320 | uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; |
321 | ||
fb087eaa LY |
322 | pcm_idx = kcontrol->private_value; |
323 | mutex_lock(&spec->pcm_lock); | |
324 | per_pin = pcm_idx_to_pin(spec, pcm_idx); | |
325 | if (!per_pin) { | |
326 | /* no pin is bound to the pcm */ | |
327 | uinfo->count = 0; | |
f69548ff | 328 | goto unlock; |
fb087eaa | 329 | } |
a4e9a38b | 330 | eld = &per_pin->sink_eld; |
68e03de9 | 331 | uinfo->count = eld->eld_valid ? eld->eld_size : 0; |
14bc52b8 | 332 | |
f69548ff TI |
333 | unlock: |
334 | mutex_unlock(&spec->pcm_lock); | |
14bc52b8 PLB |
335 | return 0; |
336 | } | |
337 | ||
338 | static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol, | |
339 | struct snd_ctl_elem_value *ucontrol) | |
340 | { | |
341 | struct hda_codec *codec = snd_kcontrol_chip(kcontrol); | |
68e03de9 | 342 | struct hdmi_spec *spec = codec->spec; |
a4e9a38b | 343 | struct hdmi_spec_per_pin *per_pin; |
68e03de9 | 344 | struct hdmi_eld *eld; |
fb087eaa | 345 | int pcm_idx; |
f69548ff | 346 | int err = 0; |
14bc52b8 | 347 | |
fb087eaa LY |
348 | pcm_idx = kcontrol->private_value; |
349 | mutex_lock(&spec->pcm_lock); | |
350 | per_pin = pcm_idx_to_pin(spec, pcm_idx); | |
351 | if (!per_pin) { | |
352 | /* no pin is bound to the pcm */ | |
353 | memset(ucontrol->value.bytes.data, 0, | |
354 | ARRAY_SIZE(ucontrol->value.bytes.data)); | |
f69548ff | 355 | goto unlock; |
fb087eaa | 356 | } |
68e03de9 | 357 | |
f69548ff | 358 | eld = &per_pin->sink_eld; |
360a8245 DH |
359 | if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) || |
360 | eld->eld_size > ELD_MAX_SIZE) { | |
68e03de9 | 361 | snd_BUG(); |
f69548ff TI |
362 | err = -EINVAL; |
363 | goto unlock; | |
68e03de9 DH |
364 | } |
365 | ||
366 | memset(ucontrol->value.bytes.data, 0, | |
367 | ARRAY_SIZE(ucontrol->value.bytes.data)); | |
368 | if (eld->eld_valid) | |
369 | memcpy(ucontrol->value.bytes.data, eld->eld_buffer, | |
370 | eld->eld_size); | |
14bc52b8 | 371 | |
f69548ff TI |
372 | unlock: |
373 | mutex_unlock(&spec->pcm_lock); | |
374 | return err; | |
14bc52b8 PLB |
375 | } |
376 | ||
f3b827e0 | 377 | static const struct snd_kcontrol_new eld_bytes_ctl = { |
fbd3eb7f TI |
378 | .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE | |
379 | SNDRV_CTL_ELEM_ACCESS_SKIP_CHECK, | |
14bc52b8 PLB |
380 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, |
381 | .name = "ELD", | |
382 | .info = hdmi_eld_ctl_info, | |
383 | .get = hdmi_eld_ctl_get, | |
384 | }; | |
385 | ||
fb087eaa | 386 | static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx, |
14bc52b8 PLB |
387 | int device) |
388 | { | |
389 | struct snd_kcontrol *kctl; | |
390 | struct hdmi_spec *spec = codec->spec; | |
391 | int err; | |
392 | ||
393 | kctl = snd_ctl_new1(&eld_bytes_ctl, codec); | |
394 | if (!kctl) | |
395 | return -ENOMEM; | |
fb087eaa | 396 | kctl->private_value = pcm_idx; |
14bc52b8 PLB |
397 | kctl->id.device = device; |
398 | ||
fb087eaa LY |
399 | /* no pin nid is associated with the kctl now |
400 | * tbd: associate pin nid to eld ctl later | |
401 | */ | |
402 | err = snd_hda_ctl_add(codec, 0, kctl); | |
14bc52b8 PLB |
403 | if (err < 0) |
404 | return err; | |
405 | ||
fb087eaa | 406 | get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl; |
14bc52b8 PLB |
407 | return 0; |
408 | } | |
409 | ||
079d88cc WF |
410 | #ifdef BE_PARANOID |
411 | static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, | |
412 | int *packet_index, int *byte_index) | |
413 | { | |
414 | int val; | |
415 | ||
416 | val = snd_hda_codec_read(codec, pin_nid, 0, | |
417 | AC_VERB_GET_HDMI_DIP_INDEX, 0); | |
418 | ||
419 | *packet_index = val >> 5; | |
420 | *byte_index = val & 0x1f; | |
421 | } | |
422 | #endif | |
423 | ||
424 | static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, | |
425 | int packet_index, int byte_index) | |
426 | { | |
427 | int val; | |
428 | ||
429 | val = (packet_index << 5) | (byte_index & 0x1f); | |
430 | ||
431 | snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val); | |
432 | } | |
433 | ||
434 | static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid, | |
435 | unsigned char val) | |
436 | { | |
437 | snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val); | |
438 | } | |
439 | ||
384a48d7 | 440 | static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid) |
079d88cc | 441 | { |
75fae117 SW |
442 | struct hdmi_spec *spec = codec->spec; |
443 | int pin_out; | |
444 | ||
079d88cc WF |
445 | /* Unmute */ |
446 | if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) | |
447 | snd_hda_codec_write(codec, pin_nid, 0, | |
448 | AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE); | |
75fae117 SW |
449 | |
450 | if (spec->dyn_pin_out) | |
451 | /* Disable pin out until stream is active */ | |
452 | pin_out = 0; | |
453 | else | |
454 | /* Enable pin out: some machines with GM965 gets broken output | |
455 | * when the pin is disabled or changed while using with HDMI | |
456 | */ | |
457 | pin_out = PIN_OUT; | |
458 | ||
079d88cc | 459 | snd_hda_codec_write(codec, pin_nid, 0, |
75fae117 | 460 | AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out); |
079d88cc WF |
461 | } |
462 | ||
a4e9a38b TI |
463 | /* |
464 | * ELD proc files | |
465 | */ | |
466 | ||
cd6a6503 | 467 | #ifdef CONFIG_SND_PROC_FS |
a4e9a38b TI |
468 | static void print_eld_info(struct snd_info_entry *entry, |
469 | struct snd_info_buffer *buffer) | |
470 | { | |
471 | struct hdmi_spec_per_pin *per_pin = entry->private_data; | |
472 | ||
473 | mutex_lock(&per_pin->lock); | |
474 | snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer); | |
475 | mutex_unlock(&per_pin->lock); | |
476 | } | |
477 | ||
478 | static void write_eld_info(struct snd_info_entry *entry, | |
479 | struct snd_info_buffer *buffer) | |
480 | { | |
481 | struct hdmi_spec_per_pin *per_pin = entry->private_data; | |
482 | ||
483 | mutex_lock(&per_pin->lock); | |
484 | snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer); | |
485 | mutex_unlock(&per_pin->lock); | |
486 | } | |
487 | ||
488 | static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index) | |
489 | { | |
490 | char name[32]; | |
491 | struct hda_codec *codec = per_pin->codec; | |
492 | struct snd_info_entry *entry; | |
493 | int err; | |
494 | ||
495 | snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index); | |
6efdd851 | 496 | err = snd_card_proc_new(codec->card, name, &entry); |
a4e9a38b TI |
497 | if (err < 0) |
498 | return err; | |
499 | ||
500 | snd_info_set_text_ops(entry, per_pin, print_eld_info); | |
501 | entry->c.text.write = write_eld_info; | |
6a73cf46 | 502 | entry->mode |= 0200; |
a4e9a38b TI |
503 | per_pin->proc_entry = entry; |
504 | ||
505 | return 0; | |
506 | } | |
507 | ||
508 | static void eld_proc_free(struct hdmi_spec_per_pin *per_pin) | |
509 | { | |
1947a114 | 510 | if (!per_pin->codec->bus->shutdown) { |
c560a679 | 511 | snd_info_free_entry(per_pin->proc_entry); |
a4e9a38b TI |
512 | per_pin->proc_entry = NULL; |
513 | } | |
514 | } | |
515 | #else | |
b55447a7 TI |
516 | static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin, |
517 | int index) | |
a4e9a38b TI |
518 | { |
519 | return 0; | |
520 | } | |
b55447a7 | 521 | static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin) |
a4e9a38b TI |
522 | { |
523 | } | |
524 | #endif | |
079d88cc | 525 | |
079d88cc WF |
526 | /* |
527 | * Audio InfoFrame routines | |
528 | */ | |
529 | ||
530 | /* | |
531 | * Enable Audio InfoFrame Transmission | |
532 | */ | |
533 | static void hdmi_start_infoframe_trans(struct hda_codec *codec, | |
534 | hda_nid_t pin_nid) | |
535 | { | |
536 | hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); | |
537 | snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, | |
538 | AC_DIPXMIT_BEST); | |
539 | } | |
540 | ||
541 | /* | |
542 | * Disable Audio InfoFrame Transmission | |
543 | */ | |
544 | static void hdmi_stop_infoframe_trans(struct hda_codec *codec, | |
545 | hda_nid_t pin_nid) | |
546 | { | |
547 | hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); | |
548 | snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, | |
549 | AC_DIPXMIT_DISABLE); | |
550 | } | |
551 | ||
552 | static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid) | |
553 | { | |
554 | #ifdef CONFIG_SND_DEBUG_VERBOSE | |
555 | int i; | |
556 | int size; | |
557 | ||
558 | size = snd_hdmi_get_eld_size(codec, pin_nid); | |
4e76a883 | 559 | codec_dbg(codec, "HDMI: ELD buf size is %d\n", size); |
079d88cc WF |
560 | |
561 | for (i = 0; i < 8; i++) { | |
562 | size = snd_hda_codec_read(codec, pin_nid, 0, | |
563 | AC_VERB_GET_HDMI_DIP_SIZE, i); | |
4e76a883 | 564 | codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size); |
079d88cc WF |
565 | } |
566 | #endif | |
567 | } | |
568 | ||
569 | static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid) | |
570 | { | |
571 | #ifdef BE_PARANOID | |
572 | int i, j; | |
573 | int size; | |
574 | int pi, bi; | |
575 | for (i = 0; i < 8; i++) { | |
576 | size = snd_hda_codec_read(codec, pin_nid, 0, | |
577 | AC_VERB_GET_HDMI_DIP_SIZE, i); | |
578 | if (size == 0) | |
579 | continue; | |
580 | ||
581 | hdmi_set_dip_index(codec, pin_nid, i, 0x0); | |
582 | for (j = 1; j < 1000; j++) { | |
583 | hdmi_write_dip_byte(codec, pin_nid, 0x0); | |
584 | hdmi_get_dip_index(codec, pin_nid, &pi, &bi); | |
585 | if (pi != i) | |
4e76a883 | 586 | codec_dbg(codec, "dip index %d: %d != %d\n", |
079d88cc WF |
587 | bi, pi, i); |
588 | if (bi == 0) /* byte index wrapped around */ | |
589 | break; | |
590 | } | |
4e76a883 | 591 | codec_dbg(codec, |
079d88cc WF |
592 | "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n", |
593 | i, size, j); | |
594 | } | |
595 | #endif | |
596 | } | |
597 | ||
53d7d69d | 598 | static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai) |
079d88cc | 599 | { |
53d7d69d | 600 | u8 *bytes = (u8 *)hdmi_ai; |
079d88cc WF |
601 | u8 sum = 0; |
602 | int i; | |
603 | ||
53d7d69d | 604 | hdmi_ai->checksum = 0; |
079d88cc | 605 | |
53d7d69d | 606 | for (i = 0; i < sizeof(*hdmi_ai); i++) |
079d88cc WF |
607 | sum += bytes[i]; |
608 | ||
53d7d69d | 609 | hdmi_ai->checksum = -sum; |
079d88cc WF |
610 | } |
611 | ||
612 | static void hdmi_fill_audio_infoframe(struct hda_codec *codec, | |
613 | hda_nid_t pin_nid, | |
53d7d69d | 614 | u8 *dip, int size) |
079d88cc | 615 | { |
079d88cc WF |
616 | int i; |
617 | ||
618 | hdmi_debug_dip_size(codec, pin_nid); | |
619 | hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */ | |
620 | ||
079d88cc | 621 | hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); |
53d7d69d WF |
622 | for (i = 0; i < size; i++) |
623 | hdmi_write_dip_byte(codec, pin_nid, dip[i]); | |
079d88cc WF |
624 | } |
625 | ||
626 | static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid, | |
53d7d69d | 627 | u8 *dip, int size) |
079d88cc | 628 | { |
079d88cc WF |
629 | u8 val; |
630 | int i; | |
631 | ||
632 | if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0) | |
633 | != AC_DIPXMIT_BEST) | |
634 | return false; | |
635 | ||
636 | hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); | |
53d7d69d | 637 | for (i = 0; i < size; i++) { |
079d88cc WF |
638 | val = snd_hda_codec_read(codec, pin_nid, 0, |
639 | AC_VERB_GET_HDMI_DIP_DATA, 0); | |
53d7d69d | 640 | if (val != dip[i]) |
079d88cc WF |
641 | return false; |
642 | } | |
643 | ||
644 | return true; | |
645 | } | |
646 | ||
9c32fea8 NM |
647 | static int hdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, |
648 | int dev_id, unsigned char *buf, int *eld_size) | |
649 | { | |
650 | snd_hda_set_dev_select(codec, nid, dev_id); | |
651 | ||
652 | return snd_hdmi_get_eld(codec, nid, buf, eld_size); | |
653 | } | |
654 | ||
307229d2 | 655 | static void hdmi_pin_setup_infoframe(struct hda_codec *codec, |
9c32fea8 | 656 | hda_nid_t pin_nid, int dev_id, |
307229d2 AH |
657 | int ca, int active_channels, |
658 | int conn_type) | |
659 | { | |
660 | union audio_infoframe ai; | |
661 | ||
caaf5ef9 | 662 | memset(&ai, 0, sizeof(ai)); |
307229d2 AH |
663 | if (conn_type == 0) { /* HDMI */ |
664 | struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi; | |
665 | ||
666 | hdmi_ai->type = 0x84; | |
667 | hdmi_ai->ver = 0x01; | |
668 | hdmi_ai->len = 0x0a; | |
669 | hdmi_ai->CC02_CT47 = active_channels - 1; | |
670 | hdmi_ai->CA = ca; | |
671 | hdmi_checksum_audio_infoframe(hdmi_ai); | |
672 | } else if (conn_type == 1) { /* DisplayPort */ | |
673 | struct dp_audio_infoframe *dp_ai = &ai.dp; | |
674 | ||
675 | dp_ai->type = 0x84; | |
676 | dp_ai->len = 0x1b; | |
677 | dp_ai->ver = 0x11 << 2; | |
678 | dp_ai->CC02_CT47 = active_channels - 1; | |
679 | dp_ai->CA = ca; | |
680 | } else { | |
4e76a883 | 681 | codec_dbg(codec, "HDMI: unknown connection type at pin %d\n", |
307229d2 AH |
682 | pin_nid); |
683 | return; | |
684 | } | |
685 | ||
9c32fea8 NM |
686 | snd_hda_set_dev_select(codec, pin_nid, dev_id); |
687 | ||
307229d2 AH |
688 | /* |
689 | * sizeof(ai) is used instead of sizeof(*hdmi_ai) or | |
690 | * sizeof(*dp_ai) to avoid partial match/update problems when | |
691 | * the user switches between HDMI/DP monitors. | |
692 | */ | |
693 | if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes, | |
694 | sizeof(ai))) { | |
4e76a883 TI |
695 | codec_dbg(codec, |
696 | "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n", | |
307229d2 AH |
697 | pin_nid, |
698 | active_channels, ca); | |
699 | hdmi_stop_infoframe_trans(codec, pin_nid); | |
700 | hdmi_fill_audio_infoframe(codec, pin_nid, | |
701 | ai.bytes, sizeof(ai)); | |
702 | hdmi_start_infoframe_trans(codec, pin_nid); | |
703 | } | |
704 | } | |
705 | ||
b054087d TI |
706 | static void hdmi_setup_audio_infoframe(struct hda_codec *codec, |
707 | struct hdmi_spec_per_pin *per_pin, | |
708 | bool non_pcm) | |
079d88cc | 709 | { |
307229d2 | 710 | struct hdmi_spec *spec = codec->spec; |
739ffee9 | 711 | struct hdac_chmap *chmap = &spec->chmap; |
384a48d7 | 712 | hda_nid_t pin_nid = per_pin->pin_nid; |
9c32fea8 | 713 | int dev_id = per_pin->dev_id; |
b054087d | 714 | int channels = per_pin->channels; |
1df5a06a | 715 | int active_channels; |
384a48d7 | 716 | struct hdmi_eld *eld; |
828cb4ed | 717 | int ca; |
079d88cc | 718 | |
b054087d TI |
719 | if (!channels) |
720 | return; | |
721 | ||
9c32fea8 NM |
722 | snd_hda_set_dev_select(codec, pin_nid, dev_id); |
723 | ||
44bb6d0c TI |
724 | /* some HW (e.g. HSW+) needs reprogramming the amp at each time */ |
725 | if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) | |
58f7d28d ML |
726 | snd_hda_codec_write(codec, pin_nid, 0, |
727 | AC_VERB_SET_AMP_GAIN_MUTE, | |
728 | AMP_OUT_UNMUTE); | |
729 | ||
bce0d2a8 | 730 | eld = &per_pin->sink_eld; |
079d88cc | 731 | |
bb63f726 | 732 | ca = snd_hdac_channel_allocation(&codec->core, |
828cb4ed SP |
733 | eld->info.spk_alloc, channels, |
734 | per_pin->chmap_set, non_pcm, per_pin->chmap); | |
384a48d7 | 735 | |
bb63f726 | 736 | active_channels = snd_hdac_get_active_channels(ca); |
1df5a06a | 737 | |
739ffee9 SP |
738 | chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid, |
739 | active_channels); | |
1df5a06a | 740 | |
39edac70 AH |
741 | /* |
742 | * always configure channel mapping, it may have been changed by the | |
743 | * user in the meantime | |
744 | */ | |
bb63f726 | 745 | snd_hdac_setup_channel_mapping(&spec->chmap, |
828cb4ed SP |
746 | pin_nid, non_pcm, ca, channels, |
747 | per_pin->chmap, per_pin->chmap_set); | |
39edac70 | 748 | |
9c32fea8 NM |
749 | spec->ops.pin_setup_infoframe(codec, pin_nid, dev_id, |
750 | ca, active_channels, eld->info.conn_type); | |
433968da | 751 | |
1a6003b5 | 752 | per_pin->non_pcm = non_pcm; |
079d88cc WF |
753 | } |
754 | ||
079d88cc WF |
755 | /* |
756 | * Unsolicited events | |
757 | */ | |
758 | ||
db845402 | 759 | static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll); |
38faddb1 | 760 | |
9152085d LY |
761 | static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid, |
762 | int dev_id) | |
079d88cc WF |
763 | { |
764 | struct hdmi_spec *spec = codec->spec; | |
9152085d | 765 | int pin_idx = pin_id_to_pin_index(codec, nid, dev_id); |
1a4f69d5 | 766 | |
20ce9029 DH |
767 | if (pin_idx < 0) |
768 | return; | |
aaa23f86 | 769 | mutex_lock(&spec->pcm_lock); |
db845402 | 770 | hdmi_present_sense(get_pin(spec, pin_idx), 1); |
aaa23f86 | 771 | mutex_unlock(&spec->pcm_lock); |
20ce9029 DH |
772 | } |
773 | ||
1a4f69d5 TI |
774 | static void jack_callback(struct hda_codec *codec, |
775 | struct hda_jack_callback *jack) | |
776 | { | |
ade49db3 TI |
777 | /* stop polling when notification is enabled */ |
778 | if (codec_has_acomp(codec)) | |
779 | return; | |
780 | ||
5204a05d | 781 | check_presence_and_report(codec, jack->nid, jack->dev_id); |
1a4f69d5 TI |
782 | } |
783 | ||
165c0946 TI |
784 | static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res, |
785 | struct hda_jack_tbl *jack) | |
20ce9029 | 786 | { |
3a93897e | 787 | jack->jack_dirty = 1; |
079d88cc | 788 | |
4e76a883 | 789 | codec_dbg(codec, |
2e59e5ab | 790 | "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n", |
5204a05d | 791 | codec->addr, jack->nid, jack->dev_id, !!(res & AC_UNSOL_RES_IA), |
fae3d88a | 792 | !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV)); |
079d88cc | 793 | |
5204a05d | 794 | check_presence_and_report(codec, jack->nid, jack->dev_id); |
079d88cc WF |
795 | } |
796 | ||
797 | static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res) | |
798 | { | |
799 | int tag = res >> AC_UNSOL_RES_TAG_SHIFT; | |
800 | int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; | |
801 | int cp_state = !!(res & AC_UNSOL_RES_CP_STATE); | |
802 | int cp_ready = !!(res & AC_UNSOL_RES_CP_READY); | |
803 | ||
4e76a883 | 804 | codec_info(codec, |
e9ea8e8f | 805 | "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n", |
384a48d7 | 806 | codec->addr, |
079d88cc WF |
807 | tag, |
808 | subtag, | |
809 | cp_state, | |
810 | cp_ready); | |
811 | ||
812 | /* TODO */ | |
75663c09 | 813 | if (cp_state) { |
079d88cc | 814 | ; |
75663c09 PLB |
815 | } |
816 | if (cp_ready) { | |
079d88cc | 817 | ; |
75663c09 | 818 | } |
079d88cc WF |
819 | } |
820 | ||
821 | ||
822 | static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res) | |
823 | { | |
079d88cc WF |
824 | int tag = res >> AC_UNSOL_RES_TAG_SHIFT; |
825 | int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; | |
5204a05d | 826 | struct hda_jack_tbl *jack; |
079d88cc | 827 | |
ade49db3 TI |
828 | if (codec_has_acomp(codec)) |
829 | return; | |
830 | ||
5204a05d NM |
831 | if (codec->dp_mst) { |
832 | int dev_entry = | |
833 | (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT; | |
834 | ||
835 | jack = snd_hda_jack_tbl_get_from_tag(codec, tag, dev_entry); | |
836 | } else { | |
837 | jack = snd_hda_jack_tbl_get_from_tag(codec, tag, 0); | |
838 | } | |
839 | ||
840 | if (!jack) { | |
4e76a883 | 841 | codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag); |
079d88cc WF |
842 | return; |
843 | } | |
844 | ||
845 | if (subtag == 0) | |
165c0946 | 846 | hdmi_intrinsic_event(codec, res, jack); |
079d88cc WF |
847 | else |
848 | hdmi_non_intrinsic_event(codec, res); | |
849 | } | |
850 | ||
58f7d28d | 851 | static void haswell_verify_D0(struct hda_codec *codec, |
53b434f0 | 852 | hda_nid_t cvt_nid, hda_nid_t nid) |
83f26ad2 | 853 | { |
58f7d28d | 854 | int pwr; |
83f26ad2 | 855 | |
53b434f0 WX |
856 | /* For Haswell, the converter 1/2 may keep in D3 state after bootup, |
857 | * thus pins could only choose converter 0 for use. Make sure the | |
858 | * converters are in correct power state */ | |
fd678cac | 859 | if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0)) |
53b434f0 WX |
860 | snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0); |
861 | ||
fd678cac | 862 | if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) { |
83f26ad2 DH |
863 | snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE, |
864 | AC_PWRST_D0); | |
865 | msleep(40); | |
866 | pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0); | |
867 | pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT; | |
4e76a883 | 868 | codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr); |
83f26ad2 | 869 | } |
83f26ad2 DH |
870 | } |
871 | ||
079d88cc WF |
872 | /* |
873 | * Callbacks | |
874 | */ | |
875 | ||
92f10b3f TI |
876 | /* HBR should be Non-PCM, 8 channels */ |
877 | #define is_hbr_format(format) \ | |
878 | ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7) | |
879 | ||
307229d2 | 880 | static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, |
9c32fea8 | 881 | int dev_id, bool hbr) |
079d88cc | 882 | { |
307229d2 | 883 | int pinctl, new_pinctl; |
83f26ad2 | 884 | |
384a48d7 | 885 | if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) { |
9c32fea8 | 886 | snd_hda_set_dev_select(codec, pin_nid, dev_id); |
384a48d7 | 887 | pinctl = snd_hda_codec_read(codec, pin_nid, 0, |
ea87d1c4 AH |
888 | AC_VERB_GET_PIN_WIDGET_CONTROL, 0); |
889 | ||
13122e6e AH |
890 | if (pinctl < 0) |
891 | return hbr ? -EINVAL : 0; | |
892 | ||
ea87d1c4 | 893 | new_pinctl = pinctl & ~AC_PINCTL_EPT; |
307229d2 | 894 | if (hbr) |
ea87d1c4 AH |
895 | new_pinctl |= AC_PINCTL_EPT_HBR; |
896 | else | |
897 | new_pinctl |= AC_PINCTL_EPT_NATIVE; | |
898 | ||
4e76a883 TI |
899 | codec_dbg(codec, |
900 | "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n", | |
384a48d7 | 901 | pin_nid, |
ea87d1c4 AH |
902 | pinctl == new_pinctl ? "" : "new-", |
903 | new_pinctl); | |
904 | ||
905 | if (pinctl != new_pinctl) | |
384a48d7 | 906 | snd_hda_codec_write(codec, pin_nid, 0, |
ea87d1c4 AH |
907 | AC_VERB_SET_PIN_WIDGET_CONTROL, |
908 | new_pinctl); | |
307229d2 AH |
909 | } else if (hbr) |
910 | return -EINVAL; | |
ea87d1c4 | 911 | |
307229d2 AH |
912 | return 0; |
913 | } | |
914 | ||
915 | static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, | |
9c32fea8 NM |
916 | hda_nid_t pin_nid, int dev_id, |
917 | u32 stream_tag, int format) | |
307229d2 AH |
918 | { |
919 | struct hdmi_spec *spec = codec->spec; | |
5a5d718f | 920 | unsigned int param; |
307229d2 AH |
921 | int err; |
922 | ||
9c32fea8 NM |
923 | err = spec->ops.pin_hbr_setup(codec, pin_nid, dev_id, |
924 | is_hbr_format(format)); | |
307229d2 AH |
925 | |
926 | if (err) { | |
4e76a883 | 927 | codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n"); |
307229d2 | 928 | return err; |
ea87d1c4 | 929 | } |
079d88cc | 930 | |
cb45722b | 931 | if (spec->intel_hsw_fixup) { |
5a5d718f SP |
932 | |
933 | /* | |
934 | * on recent platforms IEC Coding Type is required for HBR | |
935 | * support, read current Digital Converter settings and set | |
936 | * ICT bitfield if needed. | |
937 | */ | |
938 | param = snd_hda_codec_read(codec, cvt_nid, 0, | |
939 | AC_VERB_GET_DIGI_CONVERT_1, 0); | |
940 | ||
941 | param = (param >> 16) & ~(AC_DIG3_ICT); | |
942 | ||
943 | /* on recent platforms ICT mode is required for HBR support */ | |
944 | if (is_hbr_format(format)) | |
945 | param |= 0x1; | |
946 | ||
947 | snd_hda_codec_write(codec, cvt_nid, 0, | |
948 | AC_VERB_SET_DIGI_CONVERT_3, param); | |
949 | } | |
950 | ||
384a48d7 | 951 | snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format); |
ea87d1c4 | 952 | return 0; |
079d88cc WF |
953 | } |
954 | ||
42b29870 LY |
955 | /* Try to find an available converter |
956 | * If pin_idx is less then zero, just try to find an available converter. | |
957 | * Otherwise, try to find an available converter and get the cvt mux index | |
958 | * of the pin. | |
959 | */ | |
7ef166b8 | 960 | static int hdmi_choose_cvt(struct hda_codec *codec, |
4846a67e | 961 | int pin_idx, int *cvt_id) |
bbbe3390 TI |
962 | { |
963 | struct hdmi_spec *spec = codec->spec; | |
384a48d7 | 964 | struct hdmi_spec_per_pin *per_pin; |
384a48d7 | 965 | struct hdmi_spec_per_cvt *per_cvt = NULL; |
7ef166b8 | 966 | int cvt_idx, mux_idx = 0; |
bbbe3390 | 967 | |
42b29870 LY |
968 | /* pin_idx < 0 means no pin will be bound to the converter */ |
969 | if (pin_idx < 0) | |
970 | per_pin = NULL; | |
971 | else | |
972 | per_pin = get_pin(spec, pin_idx); | |
384a48d7 SW |
973 | |
974 | /* Dynamically assign converter to stream */ | |
975 | for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { | |
bce0d2a8 | 976 | per_cvt = get_cvt(spec, cvt_idx); |
bbbe3390 | 977 | |
384a48d7 SW |
978 | /* Must not already be assigned */ |
979 | if (per_cvt->assigned) | |
980 | continue; | |
42b29870 LY |
981 | if (per_pin == NULL) |
982 | break; | |
384a48d7 SW |
983 | /* Must be in pin's mux's list of converters */ |
984 | for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) | |
985 | if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid) | |
986 | break; | |
987 | /* Not in mux list */ | |
988 | if (mux_idx == per_pin->num_mux_nids) | |
989 | continue; | |
990 | break; | |
991 | } | |
7ef166b8 | 992 | |
384a48d7 SW |
993 | /* No free converters */ |
994 | if (cvt_idx == spec->num_cvts) | |
42b29870 | 995 | return -EBUSY; |
384a48d7 | 996 | |
42b29870 LY |
997 | if (per_pin != NULL) |
998 | per_pin->mux_idx = mux_idx; | |
2df6742f | 999 | |
7ef166b8 WX |
1000 | if (cvt_id) |
1001 | *cvt_id = cvt_idx; | |
7ef166b8 WX |
1002 | |
1003 | return 0; | |
1004 | } | |
1005 | ||
2df6742f ML |
1006 | /* Assure the pin select the right convetor */ |
1007 | static void intel_verify_pin_cvt_connect(struct hda_codec *codec, | |
1008 | struct hdmi_spec_per_pin *per_pin) | |
1009 | { | |
1010 | hda_nid_t pin_nid = per_pin->pin_nid; | |
1011 | int mux_idx, curr; | |
1012 | ||
1013 | mux_idx = per_pin->mux_idx; | |
1014 | curr = snd_hda_codec_read(codec, pin_nid, 0, | |
1015 | AC_VERB_GET_CONNECT_SEL, 0); | |
1016 | if (curr != mux_idx) | |
1017 | snd_hda_codec_write_cache(codec, pin_nid, 0, | |
1018 | AC_VERB_SET_CONNECT_SEL, | |
1019 | mux_idx); | |
1020 | } | |
1021 | ||
42b29870 LY |
1022 | /* get the mux index for the converter of the pins |
1023 | * converter's mux index is the same for all pins on Intel platform | |
1024 | */ | |
1025 | static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec, | |
1026 | hda_nid_t cvt_nid) | |
1027 | { | |
1028 | int i; | |
1029 | ||
1030 | for (i = 0; i < spec->num_cvts; i++) | |
1031 | if (spec->cvt_nids[i] == cvt_nid) | |
1032 | return i; | |
1033 | return -EINVAL; | |
1034 | } | |
1035 | ||
300016b9 ML |
1036 | /* Intel HDMI workaround to fix audio routing issue: |
1037 | * For some Intel display codecs, pins share the same connection list. | |
1038 | * So a conveter can be selected by multiple pins and playback on any of these | |
1039 | * pins will generate sound on the external display, because audio flows from | |
1040 | * the same converter to the display pipeline. Also muting one pin may make | |
1041 | * other pins have no sound output. | |
1042 | * So this function assures that an assigned converter for a pin is not selected | |
1043 | * by any other pins. | |
1044 | */ | |
1045 | static void intel_not_share_assigned_cvt(struct hda_codec *codec, | |
9152085d LY |
1046 | hda_nid_t pin_nid, |
1047 | int dev_id, int mux_idx) | |
7ef166b8 WX |
1048 | { |
1049 | struct hdmi_spec *spec = codec->spec; | |
7639a06c | 1050 | hda_nid_t nid; |
f82d7d16 ML |
1051 | int cvt_idx, curr; |
1052 | struct hdmi_spec_per_cvt *per_cvt; | |
9152085d LY |
1053 | struct hdmi_spec_per_pin *per_pin; |
1054 | int pin_idx; | |
1055 | ||
1056 | /* configure the pins connections */ | |
1057 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { | |
1058 | int dev_id_saved; | |
1059 | int dev_num; | |
7ef166b8 | 1060 | |
9152085d LY |
1061 | per_pin = get_pin(spec, pin_idx); |
1062 | /* | |
1063 | * pin not connected to monitor | |
1064 | * no need to operate on it | |
1065 | */ | |
1066 | if (!per_pin->pcm) | |
1067 | continue; | |
f82d7d16 | 1068 | |
9152085d LY |
1069 | if ((per_pin->pin_nid == pin_nid) && |
1070 | (per_pin->dev_id == dev_id)) | |
f82d7d16 | 1071 | continue; |
7ef166b8 | 1072 | |
9152085d LY |
1073 | /* |
1074 | * if per_pin->dev_id >= dev_num, | |
1075 | * snd_hda_get_dev_select() will fail, | |
1076 | * and the following operation is unpredictable. | |
1077 | * So skip this situation. | |
1078 | */ | |
1079 | dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1; | |
1080 | if (per_pin->dev_id >= dev_num) | |
7ef166b8 WX |
1081 | continue; |
1082 | ||
9152085d LY |
1083 | nid = per_pin->pin_nid; |
1084 | ||
1085 | /* | |
1086 | * Calling this function should not impact | |
1087 | * on the device entry selection | |
1088 | * So let's save the dev id for each pin, | |
1089 | * and restore it when return | |
1090 | */ | |
1091 | dev_id_saved = snd_hda_get_dev_select(codec, nid); | |
1092 | snd_hda_set_dev_select(codec, nid, per_pin->dev_id); | |
f82d7d16 | 1093 | curr = snd_hda_codec_read(codec, nid, 0, |
7ef166b8 | 1094 | AC_VERB_GET_CONNECT_SEL, 0); |
9152085d LY |
1095 | if (curr != mux_idx) { |
1096 | snd_hda_set_dev_select(codec, nid, dev_id_saved); | |
f82d7d16 | 1097 | continue; |
9152085d LY |
1098 | } |
1099 | ||
7ef166b8 | 1100 | |
f82d7d16 ML |
1101 | /* choose an unassigned converter. The conveters in the |
1102 | * connection list are in the same order as in the codec. | |
1103 | */ | |
1104 | for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { | |
1105 | per_cvt = get_cvt(spec, cvt_idx); | |
1106 | if (!per_cvt->assigned) { | |
4e76a883 TI |
1107 | codec_dbg(codec, |
1108 | "choose cvt %d for pin nid %d\n", | |
f82d7d16 ML |
1109 | cvt_idx, nid); |
1110 | snd_hda_codec_write_cache(codec, nid, 0, | |
7ef166b8 | 1111 | AC_VERB_SET_CONNECT_SEL, |
f82d7d16 ML |
1112 | cvt_idx); |
1113 | break; | |
1114 | } | |
7ef166b8 | 1115 | } |
9152085d | 1116 | snd_hda_set_dev_select(codec, nid, dev_id_saved); |
7ef166b8 WX |
1117 | } |
1118 | } | |
1119 | ||
42b29870 LY |
1120 | /* A wrapper of intel_not_share_asigned_cvt() */ |
1121 | static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec, | |
9152085d | 1122 | hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid) |
42b29870 LY |
1123 | { |
1124 | int mux_idx; | |
1125 | struct hdmi_spec *spec = codec->spec; | |
1126 | ||
42b29870 LY |
1127 | /* On Intel platform, the mapping of converter nid to |
1128 | * mux index of the pins are always the same. | |
1129 | * The pin nid may be 0, this means all pins will not | |
1130 | * share the converter. | |
1131 | */ | |
1132 | mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid); | |
1133 | if (mux_idx >= 0) | |
9152085d | 1134 | intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx); |
42b29870 LY |
1135 | } |
1136 | ||
4846a67e TI |
1137 | /* skeleton caller of pin_cvt_fixup ops */ |
1138 | static void pin_cvt_fixup(struct hda_codec *codec, | |
1139 | struct hdmi_spec_per_pin *per_pin, | |
1140 | hda_nid_t cvt_nid) | |
1141 | { | |
1142 | struct hdmi_spec *spec = codec->spec; | |
1143 | ||
1144 | if (spec->ops.pin_cvt_fixup) | |
1145 | spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid); | |
1146 | } | |
1147 | ||
42b29870 LY |
1148 | /* called in hdmi_pcm_open when no pin is assigned to the PCM |
1149 | * in dyn_pcm_assign mode. | |
1150 | */ | |
1151 | static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo, | |
1152 | struct hda_codec *codec, | |
1153 | struct snd_pcm_substream *substream) | |
1154 | { | |
1155 | struct hdmi_spec *spec = codec->spec; | |
1156 | struct snd_pcm_runtime *runtime = substream->runtime; | |
ac98379a | 1157 | int cvt_idx, pcm_idx; |
42b29870 LY |
1158 | struct hdmi_spec_per_cvt *per_cvt = NULL; |
1159 | int err; | |
1160 | ||
ac98379a LY |
1161 | pcm_idx = hinfo_to_pcm_index(codec, hinfo); |
1162 | if (pcm_idx < 0) | |
1163 | return -EINVAL; | |
1164 | ||
4846a67e | 1165 | err = hdmi_choose_cvt(codec, -1, &cvt_idx); |
42b29870 LY |
1166 | if (err) |
1167 | return err; | |
1168 | ||
1169 | per_cvt = get_cvt(spec, cvt_idx); | |
1170 | per_cvt->assigned = 1; | |
1171 | hinfo->nid = per_cvt->cvt_nid; | |
1172 | ||
4846a67e | 1173 | pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid); |
42b29870 | 1174 | |
ac98379a | 1175 | set_bit(pcm_idx, &spec->pcm_in_use); |
42b29870 LY |
1176 | /* todo: setup spdif ctls assign */ |
1177 | ||
1178 | /* Initially set the converter's capabilities */ | |
1179 | hinfo->channels_min = per_cvt->channels_min; | |
1180 | hinfo->channels_max = per_cvt->channels_max; | |
1181 | hinfo->rates = per_cvt->rates; | |
1182 | hinfo->formats = per_cvt->formats; | |
1183 | hinfo->maxbps = per_cvt->maxbps; | |
1184 | ||
1185 | /* Store the updated parameters */ | |
1186 | runtime->hw.channels_min = hinfo->channels_min; | |
1187 | runtime->hw.channels_max = hinfo->channels_max; | |
1188 | runtime->hw.formats = hinfo->formats; | |
1189 | runtime->hw.rates = hinfo->rates; | |
1190 | ||
1191 | snd_pcm_hw_constraint_step(substream->runtime, 0, | |
1192 | SNDRV_PCM_HW_PARAM_CHANNELS, 2); | |
1193 | return 0; | |
1194 | } | |
1195 | ||
7ef166b8 WX |
1196 | /* |
1197 | * HDA PCM callbacks | |
1198 | */ | |
1199 | static int hdmi_pcm_open(struct hda_pcm_stream *hinfo, | |
1200 | struct hda_codec *codec, | |
1201 | struct snd_pcm_substream *substream) | |
1202 | { | |
1203 | struct hdmi_spec *spec = codec->spec; | |
1204 | struct snd_pcm_runtime *runtime = substream->runtime; | |
4846a67e | 1205 | int pin_idx, cvt_idx, pcm_idx; |
7ef166b8 WX |
1206 | struct hdmi_spec_per_pin *per_pin; |
1207 | struct hdmi_eld *eld; | |
1208 | struct hdmi_spec_per_cvt *per_cvt = NULL; | |
1209 | int err; | |
1210 | ||
1211 | /* Validate hinfo */ | |
2bf3c85a LY |
1212 | pcm_idx = hinfo_to_pcm_index(codec, hinfo); |
1213 | if (pcm_idx < 0) | |
7ef166b8 | 1214 | return -EINVAL; |
2bf3c85a | 1215 | |
42b29870 | 1216 | mutex_lock(&spec->pcm_lock); |
4e76a883 | 1217 | pin_idx = hinfo_to_pin_index(codec, hinfo); |
42b29870 LY |
1218 | if (!spec->dyn_pcm_assign) { |
1219 | if (snd_BUG_ON(pin_idx < 0)) { | |
f69548ff TI |
1220 | err = -EINVAL; |
1221 | goto unlock; | |
42b29870 LY |
1222 | } |
1223 | } else { | |
1224 | /* no pin is assigned to the PCM | |
1225 | * PA need pcm open successfully when probe | |
1226 | */ | |
1227 | if (pin_idx < 0) { | |
1228 | err = hdmi_pcm_open_no_pin(hinfo, codec, substream); | |
f69548ff | 1229 | goto unlock; |
42b29870 LY |
1230 | } |
1231 | } | |
7ef166b8 | 1232 | |
4846a67e | 1233 | err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx); |
f69548ff TI |
1234 | if (err < 0) |
1235 | goto unlock; | |
7ef166b8 WX |
1236 | |
1237 | per_cvt = get_cvt(spec, cvt_idx); | |
384a48d7 SW |
1238 | /* Claim converter */ |
1239 | per_cvt->assigned = 1; | |
42b29870 | 1240 | |
ac98379a | 1241 | set_bit(pcm_idx, &spec->pcm_in_use); |
42b29870 | 1242 | per_pin = get_pin(spec, pin_idx); |
1df5a06a | 1243 | per_pin->cvt_nid = per_cvt->cvt_nid; |
384a48d7 SW |
1244 | hinfo->nid = per_cvt->cvt_nid; |
1245 | ||
e38e486d TI |
1246 | /* flip stripe flag for the assigned stream if supported */ |
1247 | if (get_wcaps(codec, per_cvt->cvt_nid) & AC_WCAP_STRIPE) | |
1248 | azx_stream(get_azx_dev(substream))->stripe = 1; | |
1249 | ||
9152085d | 1250 | snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id); |
bddee96b | 1251 | snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, |
384a48d7 | 1252 | AC_VERB_SET_CONNECT_SEL, |
4846a67e | 1253 | per_pin->mux_idx); |
7ef166b8 WX |
1254 | |
1255 | /* configure unused pins to choose other converters */ | |
4846a67e | 1256 | pin_cvt_fixup(codec, per_pin, 0); |
7ef166b8 | 1257 | |
2bf3c85a | 1258 | snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid); |
bbbe3390 | 1259 | |
2def8172 | 1260 | /* Initially set the converter's capabilities */ |
384a48d7 SW |
1261 | hinfo->channels_min = per_cvt->channels_min; |
1262 | hinfo->channels_max = per_cvt->channels_max; | |
1263 | hinfo->rates = per_cvt->rates; | |
1264 | hinfo->formats = per_cvt->formats; | |
1265 | hinfo->maxbps = per_cvt->maxbps; | |
2def8172 | 1266 | |
42b29870 | 1267 | eld = &per_pin->sink_eld; |
384a48d7 | 1268 | /* Restrict capabilities by ELD if this isn't disabled */ |
c3d52105 | 1269 | if (!static_hdmi_pcm && eld->eld_valid) { |
1613d6b4 | 1270 | snd_hdmi_eld_update_pcm_info(&eld->info, hinfo); |
bbbe3390 | 1271 | if (hinfo->channels_min > hinfo->channels_max || |
2ad779b7 TI |
1272 | !hinfo->rates || !hinfo->formats) { |
1273 | per_cvt->assigned = 0; | |
1274 | hinfo->nid = 0; | |
2bf3c85a | 1275 | snd_hda_spdif_ctls_unassign(codec, pcm_idx); |
f69548ff TI |
1276 | err = -ENODEV; |
1277 | goto unlock; | |
2ad779b7 | 1278 | } |
bbbe3390 | 1279 | } |
2def8172 SW |
1280 | |
1281 | /* Store the updated parameters */ | |
639cef0e TI |
1282 | runtime->hw.channels_min = hinfo->channels_min; |
1283 | runtime->hw.channels_max = hinfo->channels_max; | |
1284 | runtime->hw.formats = hinfo->formats; | |
1285 | runtime->hw.rates = hinfo->rates; | |
4fe2ca14 TI |
1286 | |
1287 | snd_pcm_hw_constraint_step(substream->runtime, 0, | |
1288 | SNDRV_PCM_HW_PARAM_CHANNELS, 2); | |
f69548ff TI |
1289 | unlock: |
1290 | mutex_unlock(&spec->pcm_lock); | |
1291 | return err; | |
bbbe3390 TI |
1292 | } |
1293 | ||
079d88cc WF |
1294 | /* |
1295 | * HDA/HDMI auto parsing | |
1296 | */ | |
384a48d7 | 1297 | static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx) |
079d88cc WF |
1298 | { |
1299 | struct hdmi_spec *spec = codec->spec; | |
bce0d2a8 | 1300 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); |
384a48d7 | 1301 | hda_nid_t pin_nid = per_pin->pin_nid; |
9c32fea8 | 1302 | int dev_id = per_pin->dev_id; |
ae254888 | 1303 | int conns; |
079d88cc WF |
1304 | |
1305 | if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) { | |
4e76a883 TI |
1306 | codec_warn(codec, |
1307 | "HDMI: pin %d wcaps %#x does not support connection list\n", | |
079d88cc WF |
1308 | pin_nid, get_wcaps(codec, pin_nid)); |
1309 | return -EINVAL; | |
1310 | } | |
1311 | ||
9c32fea8 NM |
1312 | snd_hda_set_dev_select(codec, pin_nid, dev_id); |
1313 | ||
ae254888 KV |
1314 | if (spec->intel_hsw_fixup) { |
1315 | conns = spec->num_cvts; | |
1316 | memcpy(per_pin->mux_nids, spec->cvt_nids, | |
1317 | sizeof(hda_nid_t) * conns); | |
1318 | } else { | |
1319 | conns = snd_hda_get_raw_connections(codec, pin_nid, | |
1320 | per_pin->mux_nids, | |
1321 | HDA_MAX_CONNECTIONS); | |
1322 | } | |
1323 | ||
9152085d | 1324 | /* all the device entries on the same pin have the same conn list */ |
ae254888 | 1325 | per_pin->num_mux_nids = conns; |
079d88cc WF |
1326 | |
1327 | return 0; | |
1328 | } | |
1329 | ||
a76056f2 | 1330 | static int hdmi_find_pcm_slot(struct hdmi_spec *spec, |
5398e94f | 1331 | struct hdmi_spec_per_pin *per_pin) |
a76056f2 LY |
1332 | { |
1333 | int i; | |
1334 | ||
5398e94f | 1335 | /* |
0c0fe9e6 KV |
1336 | * generic_hdmi_build_pcms() may allocate extra PCMs on some |
1337 | * platforms (with maximum of 'num_nids + dev_num - 1') | |
5398e94f NM |
1338 | * |
1339 | * The per_pin of pin_nid_idx=n and dev_id=m prefers to get pcm-n | |
1340 | * if m==0. This guarantees that dynamic pcm assignments are compatible | |
0c0fe9e6 | 1341 | * with the legacy static per_pin-pcm assignment that existed in the |
5398e94f NM |
1342 | * days before DP-MST. |
1343 | * | |
643a2cc9 TI |
1344 | * Intel DP-MST prefers this legacy behavior for compatibility, too. |
1345 | * | |
5398e94f NM |
1346 | * per_pin of m!=0 prefers to get pcm=(num_nids + (m - 1)). |
1347 | */ | |
0c0fe9e6 | 1348 | |
643a2cc9 | 1349 | if (per_pin->dev_id == 0 || spec->intel_hsw_fixup) { |
0c0fe9e6 KV |
1350 | if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap)) |
1351 | return per_pin->pin_nid_idx; | |
1352 | } else { | |
1353 | i = spec->num_nids + (per_pin->dev_id - 1); | |
1354 | if (i < spec->pcm_used && !(test_bit(i, &spec->pcm_bitmap))) | |
1355 | return i; | |
5398e94f NM |
1356 | } |
1357 | ||
1358 | /* have a second try; check the area over num_nids */ | |
9152085d | 1359 | for (i = spec->num_nids; i < spec->pcm_used; i++) { |
a76056f2 LY |
1360 | if (!test_bit(i, &spec->pcm_bitmap)) |
1361 | return i; | |
1362 | } | |
1363 | ||
1364 | /* the last try; check the empty slots in pins */ | |
9152085d | 1365 | for (i = 0; i < spec->num_nids; i++) { |
a76056f2 LY |
1366 | if (!test_bit(i, &spec->pcm_bitmap)) |
1367 | return i; | |
1368 | } | |
1369 | return -EBUSY; | |
1370 | } | |
1371 | ||
1372 | static void hdmi_attach_hda_pcm(struct hdmi_spec *spec, | |
1373 | struct hdmi_spec_per_pin *per_pin) | |
1374 | { | |
1375 | int idx; | |
1376 | ||
1377 | /* pcm already be attached to the pin */ | |
1378 | if (per_pin->pcm) | |
1379 | return; | |
1380 | idx = hdmi_find_pcm_slot(spec, per_pin); | |
d10a80de | 1381 | if (idx == -EBUSY) |
a76056f2 LY |
1382 | return; |
1383 | per_pin->pcm_idx = idx; | |
2bea241a | 1384 | per_pin->pcm = get_hdmi_pcm(spec, idx); |
a76056f2 LY |
1385 | set_bit(idx, &spec->pcm_bitmap); |
1386 | } | |
1387 | ||
1388 | static void hdmi_detach_hda_pcm(struct hdmi_spec *spec, | |
1389 | struct hdmi_spec_per_pin *per_pin) | |
1390 | { | |
1391 | int idx; | |
1392 | ||
1393 | /* pcm already be detached from the pin */ | |
1394 | if (!per_pin->pcm) | |
1395 | return; | |
1396 | idx = per_pin->pcm_idx; | |
1397 | per_pin->pcm_idx = -1; | |
1398 | per_pin->pcm = NULL; | |
1399 | if (idx >= 0 && idx < spec->pcm_used) | |
1400 | clear_bit(idx, &spec->pcm_bitmap); | |
1401 | } | |
1402 | ||
ac98379a LY |
1403 | static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec, |
1404 | struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid) | |
1405 | { | |
1406 | int mux_idx; | |
1407 | ||
1408 | for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) | |
1409 | if (per_pin->mux_nids[mux_idx] == cvt_nid) | |
1410 | break; | |
1411 | return mux_idx; | |
1412 | } | |
1413 | ||
1414 | static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid); | |
1415 | ||
1416 | static void hdmi_pcm_setup_pin(struct hdmi_spec *spec, | |
1417 | struct hdmi_spec_per_pin *per_pin) | |
1418 | { | |
1419 | struct hda_codec *codec = per_pin->codec; | |
1420 | struct hda_pcm *pcm; | |
1421 | struct hda_pcm_stream *hinfo; | |
1422 | struct snd_pcm_substream *substream; | |
1423 | int mux_idx; | |
1424 | bool non_pcm; | |
1425 | ||
1426 | if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) | |
2bea241a | 1427 | pcm = get_pcm_rec(spec, per_pin->pcm_idx); |
ac98379a LY |
1428 | else |
1429 | return; | |
8a7d6003 TI |
1430 | if (!pcm->pcm) |
1431 | return; | |
ac98379a LY |
1432 | if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use)) |
1433 | return; | |
1434 | ||
1435 | /* hdmi audio only uses playback and one substream */ | |
1436 | hinfo = pcm->stream; | |
1437 | substream = pcm->pcm->streams[0].substream; | |
1438 | ||
1439 | per_pin->cvt_nid = hinfo->nid; | |
1440 | ||
1441 | mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid); | |
9152085d LY |
1442 | if (mux_idx < per_pin->num_mux_nids) { |
1443 | snd_hda_set_dev_select(codec, per_pin->pin_nid, | |
1444 | per_pin->dev_id); | |
ac98379a LY |
1445 | snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, |
1446 | AC_VERB_SET_CONNECT_SEL, | |
1447 | mux_idx); | |
9152085d | 1448 | } |
ac98379a LY |
1449 | snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid); |
1450 | ||
1451 | non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid); | |
1452 | if (substream->runtime) | |
1453 | per_pin->channels = substream->runtime->channels; | |
1454 | per_pin->setup = true; | |
1455 | per_pin->mux_idx = mux_idx; | |
1456 | ||
1457 | hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); | |
1458 | } | |
1459 | ||
1460 | static void hdmi_pcm_reset_pin(struct hdmi_spec *spec, | |
1461 | struct hdmi_spec_per_pin *per_pin) | |
1462 | { | |
1463 | if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) | |
1464 | snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx); | |
1465 | ||
1466 | per_pin->chmap_set = false; | |
1467 | memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); | |
1468 | ||
1469 | per_pin->setup = false; | |
1470 | per_pin->channels = 0; | |
1471 | } | |
1472 | ||
adf615a6 TI |
1473 | static struct snd_jack *pin_idx_to_pcm_jack(struct hda_codec *codec, |
1474 | struct hdmi_spec_per_pin *per_pin) | |
1475 | { | |
1476 | struct hdmi_spec *spec = codec->spec; | |
1477 | ||
1478 | if (per_pin->pcm_idx >= 0) | |
1479 | return spec->pcm_rec[per_pin->pcm_idx].jack; | |
1480 | else | |
1481 | return NULL; | |
1482 | } | |
1483 | ||
e90247f9 TI |
1484 | /* update per_pin ELD from the given new ELD; |
1485 | * setup info frame and notification accordingly | |
adf615a6 | 1486 | * also notify ELD kctl and report jack status changes |
e90247f9 | 1487 | */ |
adf615a6 | 1488 | static void update_eld(struct hda_codec *codec, |
e90247f9 | 1489 | struct hdmi_spec_per_pin *per_pin, |
adf615a6 TI |
1490 | struct hdmi_eld *eld, |
1491 | int repoll) | |
e90247f9 TI |
1492 | { |
1493 | struct hdmi_eld *pin_eld = &per_pin->sink_eld; | |
a76056f2 | 1494 | struct hdmi_spec *spec = codec->spec; |
adf615a6 | 1495 | struct snd_jack *pcm_jack; |
e90247f9 TI |
1496 | bool old_eld_valid = pin_eld->eld_valid; |
1497 | bool eld_changed; | |
f953e72c | 1498 | int pcm_idx; |
e90247f9 | 1499 | |
adf615a6 TI |
1500 | if (eld->eld_valid) { |
1501 | if (eld->eld_size <= 0 || | |
1502 | snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer, | |
1503 | eld->eld_size) < 0) { | |
1504 | eld->eld_valid = false; | |
1505 | if (repoll) { | |
1506 | schedule_delayed_work(&per_pin->work, | |
1507 | msecs_to_jiffies(300)); | |
1508 | return; | |
1509 | } | |
1510 | } | |
1511 | } | |
1512 | ||
1513 | if (!eld->eld_valid || eld->eld_size <= 0) { | |
1514 | eld->eld_valid = false; | |
1515 | eld->eld_size = 0; | |
1516 | } | |
1517 | ||
fb087eaa LY |
1518 | /* for monitor disconnection, save pcm_idx firstly */ |
1519 | pcm_idx = per_pin->pcm_idx; | |
adf615a6 TI |
1520 | |
1521 | /* | |
1522 | * pcm_idx >=0 before update_eld() means it is in monitor | |
1523 | * disconnected event. Jack must be fetched before update_eld(). | |
1524 | */ | |
1525 | pcm_jack = pin_idx_to_pcm_jack(codec, per_pin); | |
1526 | ||
a76056f2 | 1527 | if (spec->dyn_pcm_assign) { |
ac98379a | 1528 | if (eld->eld_valid) { |
a76056f2 | 1529 | hdmi_attach_hda_pcm(spec, per_pin); |
ac98379a LY |
1530 | hdmi_pcm_setup_pin(spec, per_pin); |
1531 | } else { | |
1532 | hdmi_pcm_reset_pin(spec, per_pin); | |
a76056f2 | 1533 | hdmi_detach_hda_pcm(spec, per_pin); |
ac98379a | 1534 | } |
a76056f2 | 1535 | } |
fb087eaa LY |
1536 | /* if pcm_idx == -1, it means this is in monitor connection event |
1537 | * we can get the correct pcm_idx now. | |
1538 | */ | |
1539 | if (pcm_idx == -1) | |
1540 | pcm_idx = per_pin->pcm_idx; | |
adf615a6 TI |
1541 | if (!pcm_jack) |
1542 | pcm_jack = pin_idx_to_pcm_jack(codec, per_pin); | |
a76056f2 | 1543 | |
e90247f9 TI |
1544 | if (eld->eld_valid) |
1545 | snd_hdmi_show_eld(codec, &eld->info); | |
1546 | ||
1547 | eld_changed = (pin_eld->eld_valid != eld->eld_valid); | |
551626ec TI |
1548 | eld_changed |= (pin_eld->monitor_present != eld->monitor_present); |
1549 | if (!eld_changed && eld->eld_valid && pin_eld->eld_valid) | |
e90247f9 TI |
1550 | if (pin_eld->eld_size != eld->eld_size || |
1551 | memcmp(pin_eld->eld_buffer, eld->eld_buffer, | |
1552 | eld->eld_size) != 0) | |
1553 | eld_changed = true; | |
1554 | ||
551626ec TI |
1555 | if (eld_changed) { |
1556 | pin_eld->monitor_present = eld->monitor_present; | |
1557 | pin_eld->eld_valid = eld->eld_valid; | |
1558 | pin_eld->eld_size = eld->eld_size; | |
1559 | if (eld->eld_valid) | |
1560 | memcpy(pin_eld->eld_buffer, eld->eld_buffer, | |
1561 | eld->eld_size); | |
1562 | pin_eld->info = eld->info; | |
1563 | } | |
e90247f9 TI |
1564 | |
1565 | /* | |
1566 | * Re-setup pin and infoframe. This is needed e.g. when | |
1567 | * - sink is first plugged-in | |
1568 | * - transcoder can change during stream playback on Haswell | |
1569 | * and this can make HW reset converter selection on a pin. | |
1570 | */ | |
1571 | if (eld->eld_valid && !old_eld_valid && per_pin->setup) { | |
4846a67e | 1572 | pin_cvt_fixup(codec, per_pin, 0); |
e90247f9 TI |
1573 | hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); |
1574 | } | |
1575 | ||
fb087eaa | 1576 | if (eld_changed && pcm_idx >= 0) |
e90247f9 TI |
1577 | snd_ctl_notify(codec->card, |
1578 | SNDRV_CTL_EVENT_MASK_VALUE | | |
1579 | SNDRV_CTL_EVENT_MASK_INFO, | |
fb087eaa | 1580 | &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id); |
e90247f9 | 1581 | |
adf615a6 | 1582 | if (eld_changed && pcm_jack) |
db845402 TI |
1583 | snd_jack_report(pcm_jack, |
1584 | (eld->monitor_present && eld->eld_valid) ? | |
1585 | SND_JACK_AVOUT : 0); | |
c7e661a1 | 1586 | } |
db845402 | 1587 | |
788d441a | 1588 | /* update ELD and jack state via HD-audio verbs */ |
db845402 | 1589 | static void hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin, |
788d441a | 1590 | int repoll) |
079d88cc | 1591 | { |
744626da | 1592 | struct hda_codec *codec = per_pin->codec; |
4bd038f9 DH |
1593 | struct hdmi_spec *spec = codec->spec; |
1594 | struct hdmi_eld *eld = &spec->temp_eld; | |
744626da | 1595 | hda_nid_t pin_nid = per_pin->pin_nid; |
9c32fea8 | 1596 | int dev_id = per_pin->dev_id; |
5d44f927 SW |
1597 | /* |
1598 | * Always execute a GetPinSense verb here, even when called from | |
1599 | * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited | |
1600 | * response's PD bit is not the real PD value, but indicates that | |
1601 | * the real PD value changed. An older version of the HD-audio | |
1602 | * specification worked this way. Hence, we just ignore the data in | |
1603 | * the unsolicited response to avoid custom WARs. | |
1604 | */ | |
da4a7a39 | 1605 | int present; |
ae47e2ec TI |
1606 | int ret; |
1607 | ||
1608 | ret = snd_hda_power_up_pm(codec); | |
1609 | if (ret < 0 && pm_runtime_suspended(hda_codec_dev(codec))) | |
1610 | goto out; | |
079d88cc | 1611 | |
9c32fea8 | 1612 | present = snd_hda_jack_pin_sense(codec, pin_nid, dev_id); |
da4a7a39 | 1613 | |
a4e9a38b | 1614 | mutex_lock(&per_pin->lock); |
c44da62b TI |
1615 | eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE); |
1616 | if (eld->monitor_present) | |
4bd038f9 DH |
1617 | eld->eld_valid = !!(present & AC_PINSENSE_ELDV); |
1618 | else | |
1619 | eld->eld_valid = false; | |
079d88cc | 1620 | |
4e76a883 | 1621 | codec_dbg(codec, |
384a48d7 | 1622 | "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n", |
c44da62b | 1623 | codec->addr, pin_nid, eld->monitor_present, eld->eld_valid); |
5d44f927 | 1624 | |
4bd038f9 | 1625 | if (eld->eld_valid) { |
9c32fea8 NM |
1626 | if (spec->ops.pin_get_eld(codec, pin_nid, dev_id, |
1627 | eld->eld_buffer, &eld->eld_size) < 0) | |
4bd038f9 | 1628 | eld->eld_valid = false; |
744626da | 1629 | } |
4bd038f9 | 1630 | |
adf615a6 | 1631 | update_eld(codec, per_pin, eld, repoll); |
c7e661a1 | 1632 | mutex_unlock(&per_pin->lock); |
ae47e2ec TI |
1633 | out: |
1634 | snd_hda_power_down_pm(codec); | |
3184270e LY |
1635 | } |
1636 | ||
788d441a TI |
1637 | /* update ELD and jack state via audio component */ |
1638 | static void sync_eld_via_acomp(struct hda_codec *codec, | |
1639 | struct hdmi_spec_per_pin *per_pin) | |
1640 | { | |
788d441a TI |
1641 | struct hdmi_spec *spec = codec->spec; |
1642 | struct hdmi_eld *eld = &spec->temp_eld; | |
788d441a | 1643 | |
e2dc7d7d | 1644 | mutex_lock(&per_pin->lock); |
c64c1437 | 1645 | eld->monitor_present = false; |
adf615a6 | 1646 | eld->eld_size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid, |
9152085d LY |
1647 | per_pin->dev_id, &eld->monitor_present, |
1648 | eld->eld_buffer, ELD_MAX_SIZE); | |
adf615a6 TI |
1649 | eld->eld_valid = (eld->eld_size > 0); |
1650 | update_eld(codec, per_pin, eld, 0); | |
e2dc7d7d | 1651 | mutex_unlock(&per_pin->lock); |
788d441a TI |
1652 | } |
1653 | ||
db845402 | 1654 | static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll) |
788d441a TI |
1655 | { |
1656 | struct hda_codec *codec = per_pin->codec; | |
1657 | ||
ae47e2ec | 1658 | if (!codec_has_acomp(codec)) |
db845402 | 1659 | hdmi_present_sense_via_verbs(per_pin, repoll); |
ae47e2ec | 1660 | else |
788d441a | 1661 | sync_eld_via_acomp(codec, per_pin); |
788d441a TI |
1662 | } |
1663 | ||
744626da WF |
1664 | static void hdmi_repoll_eld(struct work_struct *work) |
1665 | { | |
1666 | struct hdmi_spec_per_pin *per_pin = | |
1667 | container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work); | |
aaa23f86 CW |
1668 | struct hda_codec *codec = per_pin->codec; |
1669 | struct hdmi_spec *spec = codec->spec; | |
8c2e6728 HW |
1670 | struct hda_jack_tbl *jack; |
1671 | ||
5204a05d NM |
1672 | jack = snd_hda_jack_tbl_get_mst(codec, per_pin->pin_nid, |
1673 | per_pin->dev_id); | |
8c2e6728 HW |
1674 | if (jack) |
1675 | jack->jack_dirty = 1; | |
744626da | 1676 | |
c6e8453e WF |
1677 | if (per_pin->repoll_count++ > 6) |
1678 | per_pin->repoll_count = 0; | |
1679 | ||
aaa23f86 | 1680 | mutex_lock(&spec->pcm_lock); |
db845402 | 1681 | hdmi_present_sense(per_pin, per_pin->repoll_count); |
aaa23f86 | 1682 | mutex_unlock(&spec->pcm_lock); |
744626da WF |
1683 | } |
1684 | ||
079d88cc WF |
1685 | static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid) |
1686 | { | |
1687 | struct hdmi_spec *spec = codec->spec; | |
384a48d7 SW |
1688 | unsigned int caps, config; |
1689 | int pin_idx; | |
1690 | struct hdmi_spec_per_pin *per_pin; | |
07acecc1 | 1691 | int err; |
9152085d | 1692 | int dev_num, i; |
079d88cc | 1693 | |
efc2f8de | 1694 | caps = snd_hda_query_pin_caps(codec, pin_nid); |
384a48d7 SW |
1695 | if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP))) |
1696 | return 0; | |
1697 | ||
9152085d LY |
1698 | /* |
1699 | * For DP MST audio, Configuration Default is the same for | |
1700 | * all device entries on the same pin | |
1701 | */ | |
efc2f8de | 1702 | config = snd_hda_codec_get_pincfg(codec, pin_nid); |
384a48d7 SW |
1703 | if (get_defcfg_connect(config) == AC_JACK_PORT_NONE) |
1704 | return 0; | |
1705 | ||
9152085d LY |
1706 | /* |
1707 | * To simplify the implementation, malloc all | |
1708 | * the virtual pins in the initialization statically | |
1709 | */ | |
cb45722b | 1710 | if (spec->intel_hsw_fixup) { |
9152085d LY |
1711 | /* |
1712 | * On Intel platforms, device entries number is | |
1713 | * changed dynamically. If there is a DP MST | |
1714 | * hub connected, the device entries number is 3. | |
1715 | * Otherwise, it is 1. | |
1716 | * Here we manually set dev_num to 3, so that | |
1717 | * we can initialize all the device entries when | |
1718 | * bootup statically. | |
1719 | */ | |
1720 | dev_num = 3; | |
1721 | spec->dev_num = 3; | |
1722 | } else if (spec->dyn_pcm_assign && codec->dp_mst) { | |
1723 | dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1; | |
1724 | /* | |
1725 | * spec->dev_num is the maxinum number of device entries | |
1726 | * among all the pins | |
1727 | */ | |
1728 | spec->dev_num = (spec->dev_num > dev_num) ? | |
1729 | spec->dev_num : dev_num; | |
1730 | } else { | |
1731 | /* | |
1732 | * If the platform doesn't support DP MST, | |
1733 | * manually set dev_num to 1. This means | |
1734 | * the pin has only one device entry. | |
1735 | */ | |
1736 | dev_num = 1; | |
1737 | spec->dev_num = 1; | |
2bea241a | 1738 | } |
079d88cc | 1739 | |
9152085d LY |
1740 | for (i = 0; i < dev_num; i++) { |
1741 | pin_idx = spec->num_pins; | |
1742 | per_pin = snd_array_new(&spec->pins); | |
079d88cc | 1743 | |
9152085d LY |
1744 | if (!per_pin) |
1745 | return -ENOMEM; | |
1746 | ||
1747 | if (spec->dyn_pcm_assign) { | |
1748 | per_pin->pcm = NULL; | |
1749 | per_pin->pcm_idx = -1; | |
1750 | } else { | |
1751 | per_pin->pcm = get_hdmi_pcm(spec, pin_idx); | |
1752 | per_pin->pcm_idx = pin_idx; | |
1753 | } | |
1754 | per_pin->pin_nid = pin_nid; | |
1755 | per_pin->pin_nid_idx = spec->num_nids; | |
1756 | per_pin->dev_id = i; | |
1757 | per_pin->non_pcm = false; | |
1758 | snd_hda_set_dev_select(codec, pin_nid, i); | |
9152085d LY |
1759 | err = hdmi_read_pin_conn(codec, pin_idx); |
1760 | if (err < 0) | |
1761 | return err; | |
1762 | spec->num_pins++; | |
1763 | } | |
1764 | spec->num_nids++; | |
079d88cc | 1765 | |
384a48d7 | 1766 | return 0; |
079d88cc WF |
1767 | } |
1768 | ||
384a48d7 | 1769 | static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) |
079d88cc WF |
1770 | { |
1771 | struct hdmi_spec *spec = codec->spec; | |
384a48d7 SW |
1772 | struct hdmi_spec_per_cvt *per_cvt; |
1773 | unsigned int chans; | |
1774 | int err; | |
079d88cc | 1775 | |
384a48d7 SW |
1776 | chans = get_wcaps(codec, cvt_nid); |
1777 | chans = get_wcaps_channels(chans); | |
1778 | ||
bce0d2a8 TI |
1779 | per_cvt = snd_array_new(&spec->cvts); |
1780 | if (!per_cvt) | |
1781 | return -ENOMEM; | |
384a48d7 SW |
1782 | |
1783 | per_cvt->cvt_nid = cvt_nid; | |
1784 | per_cvt->channels_min = 2; | |
d45e6889 | 1785 | if (chans <= 16) { |
384a48d7 | 1786 | per_cvt->channels_max = chans; |
67b90cb8 SP |
1787 | if (chans > spec->chmap.channels_max) |
1788 | spec->chmap.channels_max = chans; | |
d45e6889 | 1789 | } |
384a48d7 SW |
1790 | |
1791 | err = snd_hda_query_supported_pcm(codec, cvt_nid, | |
1792 | &per_cvt->rates, | |
1793 | &per_cvt->formats, | |
1794 | &per_cvt->maxbps); | |
1795 | if (err < 0) | |
1796 | return err; | |
1797 | ||
bce0d2a8 TI |
1798 | if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids)) |
1799 | spec->cvt_nids[spec->num_cvts] = cvt_nid; | |
1800 | spec->num_cvts++; | |
079d88cc WF |
1801 | |
1802 | return 0; | |
1803 | } | |
1804 | ||
1805 | static int hdmi_parse_codec(struct hda_codec *codec) | |
1806 | { | |
1807 | hda_nid_t nid; | |
1808 | int i, nodes; | |
1809 | ||
7639a06c | 1810 | nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid); |
079d88cc | 1811 | if (!nid || nodes < 0) { |
4e76a883 | 1812 | codec_warn(codec, "HDMI: failed to get afg sub nodes\n"); |
079d88cc WF |
1813 | return -EINVAL; |
1814 | } | |
1815 | ||
1816 | for (i = 0; i < nodes; i++, nid++) { | |
1817 | unsigned int caps; | |
1818 | unsigned int type; | |
1819 | ||
efc2f8de | 1820 | caps = get_wcaps(codec, nid); |
079d88cc WF |
1821 | type = get_wcaps_type(caps); |
1822 | ||
1823 | if (!(caps & AC_WCAP_DIGITAL)) | |
1824 | continue; | |
1825 | ||
1826 | switch (type) { | |
1827 | case AC_WID_AUD_OUT: | |
384a48d7 | 1828 | hdmi_add_cvt(codec, nid); |
079d88cc WF |
1829 | break; |
1830 | case AC_WID_PIN: | |
3eaead57 | 1831 | hdmi_add_pin(codec, nid); |
079d88cc WF |
1832 | break; |
1833 | } | |
1834 | } | |
1835 | ||
079d88cc WF |
1836 | return 0; |
1837 | } | |
1838 | ||
84eb01be TI |
1839 | /* |
1840 | */ | |
1a6003b5 TI |
1841 | static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) |
1842 | { | |
1843 | struct hda_spdif_out *spdif; | |
1844 | bool non_pcm; | |
1845 | ||
1846 | mutex_lock(&codec->spdif_mutex); | |
1847 | spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid); | |
960a581e LY |
1848 | /* Add sanity check to pass klockwork check. |
1849 | * This should never happen. | |
1850 | */ | |
a2f64724 WB |
1851 | if (WARN_ON(spdif == NULL)) { |
1852 | mutex_unlock(&codec->spdif_mutex); | |
960a581e | 1853 | return true; |
a2f64724 | 1854 | } |
1a6003b5 TI |
1855 | non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO); |
1856 | mutex_unlock(&codec->spdif_mutex); | |
1857 | return non_pcm; | |
1858 | } | |
1859 | ||
84eb01be TI |
1860 | /* |
1861 | * HDMI callbacks | |
1862 | */ | |
1863 | ||
1864 | static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo, | |
1865 | struct hda_codec *codec, | |
1866 | unsigned int stream_tag, | |
1867 | unsigned int format, | |
1868 | struct snd_pcm_substream *substream) | |
1869 | { | |
384a48d7 SW |
1870 | hda_nid_t cvt_nid = hinfo->nid; |
1871 | struct hdmi_spec *spec = codec->spec; | |
42b29870 LY |
1872 | int pin_idx; |
1873 | struct hdmi_spec_per_pin *per_pin; | |
ddd621fb | 1874 | struct snd_pcm_runtime *runtime = substream->runtime; |
1a6003b5 | 1875 | bool non_pcm; |
053b0559 | 1876 | int pinctl, stripe; |
f69548ff | 1877 | int err = 0; |
1a6003b5 | 1878 | |
42b29870 LY |
1879 | mutex_lock(&spec->pcm_lock); |
1880 | pin_idx = hinfo_to_pin_index(codec, hinfo); | |
1881 | if (spec->dyn_pcm_assign && pin_idx < 0) { | |
1882 | /* when dyn_pcm_assign and pcm is not bound to a pin | |
1883 | * skip pin setup and return 0 to make audio playback | |
1884 | * be ongoing | |
1885 | */ | |
4846a67e | 1886 | pin_cvt_fixup(codec, NULL, cvt_nid); |
42b29870 LY |
1887 | snd_hda_codec_setup_stream(codec, cvt_nid, |
1888 | stream_tag, 0, format); | |
f69548ff | 1889 | goto unlock; |
42b29870 | 1890 | } |
1a6003b5 | 1891 | |
42b29870 | 1892 | if (snd_BUG_ON(pin_idx < 0)) { |
f69548ff TI |
1893 | err = -EINVAL; |
1894 | goto unlock; | |
42b29870 LY |
1895 | } |
1896 | per_pin = get_pin(spec, pin_idx); | |
4846a67e TI |
1897 | |
1898 | /* Verify pin:cvt selections to avoid silent audio after S3. | |
1899 | * After S3, the audio driver restores pin:cvt selections | |
1900 | * but this can happen before gfx is ready and such selection | |
1901 | * is overlooked by HW. Thus multiple pins can share a same | |
1902 | * default convertor and mute control will affect each other, | |
1903 | * which can cause a resumed audio playback become silent | |
1904 | * after S3. | |
1905 | */ | |
1906 | pin_cvt_fixup(codec, per_pin, 0); | |
2df6742f | 1907 | |
ddd621fb LY |
1908 | /* Call sync_audio_rate to set the N/CTS/M manually if necessary */ |
1909 | /* Todo: add DP1.2 MST audio support later */ | |
93a9ff15 | 1910 | if (codec_has_acomp(codec)) |
9c32fea8 NM |
1911 | snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid, |
1912 | per_pin->dev_id, runtime->rate); | |
ddd621fb | 1913 | |
1a6003b5 | 1914 | non_pcm = check_non_pcm_per_cvt(codec, cvt_nid); |
a4e9a38b | 1915 | mutex_lock(&per_pin->lock); |
b054087d TI |
1916 | per_pin->channels = substream->runtime->channels; |
1917 | per_pin->setup = true; | |
384a48d7 | 1918 | |
053b0559 SP |
1919 | if (get_wcaps(codec, cvt_nid) & AC_WCAP_STRIPE) { |
1920 | stripe = snd_hdac_get_stream_stripe_ctl(&codec->bus->core, | |
1921 | substream); | |
1922 | snd_hda_codec_write(codec, cvt_nid, 0, | |
1923 | AC_VERB_SET_STRIPE_CONTROL, | |
1924 | stripe); | |
1925 | } | |
1926 | ||
b054087d | 1927 | hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); |
a4e9a38b | 1928 | mutex_unlock(&per_pin->lock); |
75fae117 | 1929 | if (spec->dyn_pin_out) { |
9c32fea8 NM |
1930 | snd_hda_set_dev_select(codec, per_pin->pin_nid, |
1931 | per_pin->dev_id); | |
1932 | pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, | |
75fae117 | 1933 | AC_VERB_GET_PIN_WIDGET_CONTROL, 0); |
9c32fea8 | 1934 | snd_hda_codec_write(codec, per_pin->pin_nid, 0, |
75fae117 SW |
1935 | AC_VERB_SET_PIN_WIDGET_CONTROL, |
1936 | pinctl | PIN_OUT); | |
1937 | } | |
1938 | ||
9152085d | 1939 | /* snd_hda_set_dev_select() has been called before */ |
9c32fea8 NM |
1940 | err = spec->ops.setup_stream(codec, cvt_nid, per_pin->pin_nid, |
1941 | per_pin->dev_id, stream_tag, format); | |
f69548ff | 1942 | unlock: |
42b29870 LY |
1943 | mutex_unlock(&spec->pcm_lock); |
1944 | return err; | |
84eb01be TI |
1945 | } |
1946 | ||
8dfaa573 TI |
1947 | static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, |
1948 | struct hda_codec *codec, | |
1949 | struct snd_pcm_substream *substream) | |
1950 | { | |
1951 | snd_hda_codec_cleanup_stream(codec, hinfo->nid); | |
1952 | return 0; | |
1953 | } | |
1954 | ||
f2ad24fa TI |
1955 | static int hdmi_pcm_close(struct hda_pcm_stream *hinfo, |
1956 | struct hda_codec *codec, | |
1957 | struct snd_pcm_substream *substream) | |
384a48d7 SW |
1958 | { |
1959 | struct hdmi_spec *spec = codec->spec; | |
2bf3c85a | 1960 | int cvt_idx, pin_idx, pcm_idx; |
384a48d7 SW |
1961 | struct hdmi_spec_per_cvt *per_cvt; |
1962 | struct hdmi_spec_per_pin *per_pin; | |
75fae117 | 1963 | int pinctl; |
f69548ff | 1964 | int err = 0; |
384a48d7 | 1965 | |
384a48d7 | 1966 | if (hinfo->nid) { |
2bf3c85a LY |
1967 | pcm_idx = hinfo_to_pcm_index(codec, hinfo); |
1968 | if (snd_BUG_ON(pcm_idx < 0)) | |
1969 | return -EINVAL; | |
4e76a883 | 1970 | cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid); |
384a48d7 SW |
1971 | if (snd_BUG_ON(cvt_idx < 0)) |
1972 | return -EINVAL; | |
bce0d2a8 | 1973 | per_cvt = get_cvt(spec, cvt_idx); |
384a48d7 SW |
1974 | |
1975 | snd_BUG_ON(!per_cvt->assigned); | |
1976 | per_cvt->assigned = 0; | |
1977 | hinfo->nid = 0; | |
1978 | ||
6fd739c0 TI |
1979 | azx_stream(get_azx_dev(substream))->stripe = 0; |
1980 | ||
42b29870 | 1981 | mutex_lock(&spec->pcm_lock); |
b09887f8 | 1982 | snd_hda_spdif_ctls_unassign(codec, pcm_idx); |
ac98379a | 1983 | clear_bit(pcm_idx, &spec->pcm_in_use); |
4e76a883 | 1984 | pin_idx = hinfo_to_pin_index(codec, hinfo); |
f69548ff TI |
1985 | if (spec->dyn_pcm_assign && pin_idx < 0) |
1986 | goto unlock; | |
42b29870 LY |
1987 | |
1988 | if (snd_BUG_ON(pin_idx < 0)) { | |
f69548ff TI |
1989 | err = -EINVAL; |
1990 | goto unlock; | |
42b29870 | 1991 | } |
bce0d2a8 | 1992 | per_pin = get_pin(spec, pin_idx); |
384a48d7 | 1993 | |
75fae117 | 1994 | if (spec->dyn_pin_out) { |
9c32fea8 NM |
1995 | snd_hda_set_dev_select(codec, per_pin->pin_nid, |
1996 | per_pin->dev_id); | |
75fae117 SW |
1997 | pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, |
1998 | AC_VERB_GET_PIN_WIDGET_CONTROL, 0); | |
1999 | snd_hda_codec_write(codec, per_pin->pin_nid, 0, | |
2000 | AC_VERB_SET_PIN_WIDGET_CONTROL, | |
2001 | pinctl & ~PIN_OUT); | |
2002 | } | |
2003 | ||
a4e9a38b | 2004 | mutex_lock(&per_pin->lock); |
d45e6889 TI |
2005 | per_pin->chmap_set = false; |
2006 | memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); | |
b054087d TI |
2007 | |
2008 | per_pin->setup = false; | |
2009 | per_pin->channels = 0; | |
a4e9a38b | 2010 | mutex_unlock(&per_pin->lock); |
f69548ff | 2011 | unlock: |
42b29870 | 2012 | mutex_unlock(&spec->pcm_lock); |
384a48d7 | 2013 | } |
d45e6889 | 2014 | |
f69548ff | 2015 | return err; |
384a48d7 SW |
2016 | } |
2017 | ||
2018 | static const struct hda_pcm_ops generic_ops = { | |
2019 | .open = hdmi_pcm_open, | |
f2ad24fa | 2020 | .close = hdmi_pcm_close, |
384a48d7 | 2021 | .prepare = generic_hdmi_playback_pcm_prepare, |
8dfaa573 | 2022 | .cleanup = generic_hdmi_playback_pcm_cleanup, |
84eb01be TI |
2023 | }; |
2024 | ||
44fde3b8 SP |
2025 | static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx) |
2026 | { | |
2027 | struct hda_codec *codec = container_of(hdac, struct hda_codec, core); | |
2028 | struct hdmi_spec *spec = codec->spec; | |
2029 | struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); | |
2030 | ||
2031 | if (!per_pin) | |
2032 | return 0; | |
2033 | ||
2034 | return per_pin->sink_eld.info.spk_alloc; | |
2035 | } | |
2036 | ||
9b3dc8aa SP |
2037 | static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx, |
2038 | unsigned char *chmap) | |
2039 | { | |
2040 | struct hda_codec *codec = container_of(hdac, struct hda_codec, core); | |
2041 | struct hdmi_spec *spec = codec->spec; | |
2042 | struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); | |
2043 | ||
2044 | /* chmap is already set to 0 in caller */ | |
2045 | if (!per_pin) | |
2046 | return; | |
2047 | ||
2048 | memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap)); | |
2049 | } | |
2050 | ||
2051 | static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx, | |
2052 | unsigned char *chmap, int prepared) | |
2053 | { | |
2054 | struct hda_codec *codec = container_of(hdac, struct hda_codec, core); | |
2055 | struct hdmi_spec *spec = codec->spec; | |
2056 | struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); | |
2057 | ||
ed0739b5 LY |
2058 | if (!per_pin) |
2059 | return; | |
9b3dc8aa SP |
2060 | mutex_lock(&per_pin->lock); |
2061 | per_pin->chmap_set = true; | |
2062 | memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap)); | |
2063 | if (prepared) | |
2064 | hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); | |
2065 | mutex_unlock(&per_pin->lock); | |
2066 | } | |
2067 | ||
2068 | static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx) | |
2069 | { | |
2070 | struct hda_codec *codec = container_of(hdac, struct hda_codec, core); | |
2071 | struct hdmi_spec *spec = codec->spec; | |
2072 | struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); | |
2073 | ||
2074 | return per_pin ? true:false; | |
2075 | } | |
2076 | ||
84eb01be TI |
2077 | static int generic_hdmi_build_pcms(struct hda_codec *codec) |
2078 | { | |
2079 | struct hdmi_spec *spec = codec->spec; | |
2a2edfbb | 2080 | int idx, pcm_num; |
84eb01be | 2081 | |
9152085d LY |
2082 | /* |
2083 | * for non-mst mode, pcm number is the same as before | |
2a2edfbb KV |
2084 | * for DP MST mode without extra PCM, pcm number is same |
2085 | * for DP MST mode with extra PCMs, pcm number is | |
2086 | * (nid number + dev_num - 1) | |
2087 | * dev_num is the device entry number in a pin | |
9152085d | 2088 | */ |
2a2edfbb KV |
2089 | |
2090 | if (codec->mst_no_extra_pcms) | |
2091 | pcm_num = spec->num_nids; | |
2092 | else | |
2093 | pcm_num = spec->num_nids + spec->dev_num - 1; | |
2094 | ||
2095 | codec_dbg(codec, "hdmi: pcm_num set to %d\n", pcm_num); | |
2096 | ||
2097 | for (idx = 0; idx < pcm_num; idx++) { | |
384a48d7 | 2098 | struct hda_pcm *info; |
84eb01be | 2099 | struct hda_pcm_stream *pstr; |
bce0d2a8 | 2100 | |
9152085d | 2101 | info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx); |
bce0d2a8 TI |
2102 | if (!info) |
2103 | return -ENOMEM; | |
2bea241a | 2104 | |
9152085d | 2105 | spec->pcm_rec[idx].pcm = info; |
2bf3c85a | 2106 | spec->pcm_used++; |
84eb01be | 2107 | info->pcm_type = HDA_PCM_TYPE_HDMI; |
d45e6889 | 2108 | info->own_chmap = true; |
384a48d7 | 2109 | |
84eb01be | 2110 | pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; |
384a48d7 SW |
2111 | pstr->substreams = 1; |
2112 | pstr->ops = generic_ops; | |
9152085d LY |
2113 | /* pcm number is less than 16 */ |
2114 | if (spec->pcm_used >= 16) | |
2115 | break; | |
384a48d7 | 2116 | /* other pstr fields are set in open */ |
84eb01be TI |
2117 | } |
2118 | ||
2119 | return 0; | |
2120 | } | |
2121 | ||
25e4abb3 | 2122 | static void free_hdmi_jack_priv(struct snd_jack *jack) |
788d441a | 2123 | { |
25e4abb3 | 2124 | struct hdmi_pcm *pcm = jack->private_data; |
788d441a | 2125 | |
25e4abb3 | 2126 | pcm->jack = NULL; |
788d441a TI |
2127 | } |
2128 | ||
db845402 | 2129 | static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx) |
788d441a | 2130 | { |
db845402 TI |
2131 | char hdmi_str[32] = "HDMI/DP"; |
2132 | struct hdmi_spec *spec = codec->spec; | |
2133 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, pcm_idx); | |
788d441a | 2134 | struct snd_jack *jack; |
db845402 | 2135 | int pcmdev = get_pcm_rec(spec, pcm_idx)->device; |
788d441a TI |
2136 | int err; |
2137 | ||
db845402 TI |
2138 | if (pcmdev > 0) |
2139 | sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev); | |
2140 | if (!spec->dyn_pcm_assign && | |
2141 | !is_jack_detectable(codec, per_pin->pin_nid)) | |
2142 | strncat(hdmi_str, " Phantom", | |
2143 | sizeof(hdmi_str) - strlen(hdmi_str) - 1); | |
2144 | ||
2145 | err = snd_jack_new(codec->card, hdmi_str, SND_JACK_AVOUT, &jack, | |
788d441a TI |
2146 | true, false); |
2147 | if (err < 0) | |
2148 | return err; | |
25e4abb3 LY |
2149 | |
2150 | spec->pcm_rec[pcm_idx].jack = jack; | |
2151 | jack->private_data = &spec->pcm_rec[pcm_idx]; | |
2152 | jack->private_free = free_hdmi_jack_priv; | |
788d441a TI |
2153 | return 0; |
2154 | } | |
2155 | ||
84eb01be TI |
2156 | static int generic_hdmi_build_controls(struct hda_codec *codec) |
2157 | { | |
2158 | struct hdmi_spec *spec = codec->spec; | |
1f7f51a6 | 2159 | int dev, err; |
25e4abb3 | 2160 | int pin_idx, pcm_idx; |
84eb01be | 2161 | |
25e4abb3 | 2162 | for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { |
8a7d6003 TI |
2163 | if (!get_pcm_rec(spec, pcm_idx)->pcm) { |
2164 | /* no PCM: mark this for skipping permanently */ | |
2165 | set_bit(pcm_idx, &spec->pcm_bitmap); | |
2166 | continue; | |
2167 | } | |
2168 | ||
25e4abb3 | 2169 | err = generic_hdmi_build_jack(codec, pcm_idx); |
0b6c49b5 DH |
2170 | if (err < 0) |
2171 | return err; | |
2172 | ||
b09887f8 LY |
2173 | /* create the spdif for each pcm |
2174 | * pin will be bound when monitor is connected | |
2175 | */ | |
2176 | if (spec->dyn_pcm_assign) | |
2177 | err = snd_hda_create_dig_out_ctls(codec, | |
2178 | 0, spec->cvt_nids[0], | |
2179 | HDA_PCM_TYPE_HDMI); | |
2180 | else { | |
2181 | struct hdmi_spec_per_pin *per_pin = | |
2182 | get_pin(spec, pcm_idx); | |
2183 | err = snd_hda_create_dig_out_ctls(codec, | |
dcda5806 TI |
2184 | per_pin->pin_nid, |
2185 | per_pin->mux_nids[0], | |
2186 | HDA_PCM_TYPE_HDMI); | |
b09887f8 | 2187 | } |
84eb01be TI |
2188 | if (err < 0) |
2189 | return err; | |
b09887f8 | 2190 | snd_hda_spdif_ctls_unassign(codec, pcm_idx); |
14bc52b8 | 2191 | |
1f7f51a6 WY |
2192 | dev = get_pcm_rec(spec, pcm_idx)->device; |
2193 | if (dev != SNDRV_PCM_INVALID_DEVICE) { | |
2194 | /* add control for ELD Bytes */ | |
2195 | err = hdmi_create_eld_ctl(codec, pcm_idx, dev); | |
2196 | if (err < 0) | |
2197 | return err; | |
2198 | } | |
fb087eaa LY |
2199 | } |
2200 | ||
2201 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { | |
2202 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); | |
ca76282b | 2203 | struct hdmi_eld *pin_eld = &per_pin->sink_eld; |
31ef2257 | 2204 | |
ca76282b | 2205 | pin_eld->eld_valid = false; |
82b1d73f | 2206 | hdmi_present_sense(per_pin, 0); |
84eb01be TI |
2207 | } |
2208 | ||
d45e6889 | 2209 | /* add channel maps */ |
022f344b | 2210 | for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { |
bbbc7e85 | 2211 | struct hda_pcm *pcm; |
2ca320e2 | 2212 | |
022f344b | 2213 | pcm = get_pcm_rec(spec, pcm_idx); |
bbbc7e85 | 2214 | if (!pcm || !pcm->pcm) |
2ca320e2 | 2215 | break; |
2f6e8a85 | 2216 | err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap); |
d45e6889 TI |
2217 | if (err < 0) |
2218 | return err; | |
d45e6889 TI |
2219 | } |
2220 | ||
84eb01be TI |
2221 | return 0; |
2222 | } | |
2223 | ||
8b8d654b | 2224 | static int generic_hdmi_init_per_pins(struct hda_codec *codec) |
84eb01be TI |
2225 | { |
2226 | struct hdmi_spec *spec = codec->spec; | |
384a48d7 SW |
2227 | int pin_idx; |
2228 | ||
2229 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { | |
bce0d2a8 | 2230 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); |
84eb01be | 2231 | |
744626da | 2232 | per_pin->codec = codec; |
a4e9a38b | 2233 | mutex_init(&per_pin->lock); |
744626da | 2234 | INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld); |
a4e9a38b | 2235 | eld_proc_new(per_pin, pin_idx); |
84eb01be | 2236 | } |
8b8d654b TI |
2237 | return 0; |
2238 | } | |
2239 | ||
2240 | static int generic_hdmi_init(struct hda_codec *codec) | |
2241 | { | |
2242 | struct hdmi_spec *spec = codec->spec; | |
2243 | int pin_idx; | |
2244 | ||
302d5a80 | 2245 | mutex_lock(&spec->bind_lock); |
8b8d654b | 2246 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { |
bce0d2a8 | 2247 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); |
8b8d654b | 2248 | hda_nid_t pin_nid = per_pin->pin_nid; |
9152085d | 2249 | int dev_id = per_pin->dev_id; |
8b8d654b | 2250 | |
9152085d | 2251 | snd_hda_set_dev_select(codec, pin_nid, dev_id); |
8b8d654b | 2252 | hdmi_init_pin(codec, pin_nid); |
ade49db3 TI |
2253 | if (codec_has_acomp(codec)) |
2254 | continue; | |
db845402 TI |
2255 | snd_hda_jack_detect_enable_callback_mst(codec, pin_nid, dev_id, |
2256 | jack_callback); | |
8b8d654b | 2257 | } |
302d5a80 | 2258 | mutex_unlock(&spec->bind_lock); |
84eb01be TI |
2259 | return 0; |
2260 | } | |
2261 | ||
bce0d2a8 TI |
2262 | static void hdmi_array_init(struct hdmi_spec *spec, int nums) |
2263 | { | |
2264 | snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums); | |
2265 | snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums); | |
bce0d2a8 TI |
2266 | } |
2267 | ||
2268 | static void hdmi_array_free(struct hdmi_spec *spec) | |
2269 | { | |
2270 | snd_array_free(&spec->pins); | |
2271 | snd_array_free(&spec->cvts); | |
bce0d2a8 TI |
2272 | } |
2273 | ||
a686632f TI |
2274 | static void generic_spec_free(struct hda_codec *codec) |
2275 | { | |
2276 | struct hdmi_spec *spec = codec->spec; | |
2277 | ||
2278 | if (spec) { | |
2279 | hdmi_array_free(spec); | |
2280 | kfree(spec); | |
2281 | codec->spec = NULL; | |
2282 | } | |
2283 | codec->dp_mst = false; | |
2284 | } | |
2285 | ||
84eb01be TI |
2286 | static void generic_hdmi_free(struct hda_codec *codec) |
2287 | { | |
2288 | struct hdmi_spec *spec = codec->spec; | |
25e4abb3 | 2289 | int pin_idx, pcm_idx; |
384a48d7 | 2290 | |
ade49db3 TI |
2291 | if (spec->acomp_registered) { |
2292 | snd_hdac_acomp_exit(&codec->bus->core); | |
2293 | } else if (codec_has_acomp(codec)) { | |
a57942bf | 2294 | snd_hdac_acomp_register_notifier(&codec->bus->core, NULL); |
4914da2f | 2295 | } |
10a95945 | 2296 | codec->relaxed_resume = 0; |
25adc137 | 2297 | |
384a48d7 | 2298 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { |
bce0d2a8 | 2299 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); |
2f35c630 | 2300 | cancel_delayed_work_sync(&per_pin->work); |
a4e9a38b | 2301 | eld_proc_free(per_pin); |
25e4abb3 LY |
2302 | } |
2303 | ||
2304 | for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { | |
2305 | if (spec->pcm_rec[pcm_idx].jack == NULL) | |
2306 | continue; | |
2307 | if (spec->dyn_pcm_assign) | |
2308 | snd_device_free(codec->card, | |
2309 | spec->pcm_rec[pcm_idx].jack); | |
2310 | else | |
2311 | spec->pcm_rec[pcm_idx].jack = NULL; | |
384a48d7 | 2312 | } |
84eb01be | 2313 | |
a686632f | 2314 | generic_spec_free(codec); |
84eb01be TI |
2315 | } |
2316 | ||
28cb72e5 WX |
2317 | #ifdef CONFIG_PM |
2318 | static int generic_hdmi_resume(struct hda_codec *codec) | |
2319 | { | |
2320 | struct hdmi_spec *spec = codec->spec; | |
2321 | int pin_idx; | |
2322 | ||
a2833683 | 2323 | codec->patch_ops.init(codec); |
1a462be5 | 2324 | snd_hda_regmap_sync(codec); |
28cb72e5 WX |
2325 | |
2326 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { | |
2327 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); | |
2328 | hdmi_present_sense(per_pin, 1); | |
2329 | } | |
2330 | return 0; | |
2331 | } | |
2332 | #endif | |
2333 | ||
fb79e1e0 | 2334 | static const struct hda_codec_ops generic_hdmi_patch_ops = { |
84eb01be TI |
2335 | .init = generic_hdmi_init, |
2336 | .free = generic_hdmi_free, | |
2337 | .build_pcms = generic_hdmi_build_pcms, | |
2338 | .build_controls = generic_hdmi_build_controls, | |
2339 | .unsol_event = hdmi_unsol_event, | |
28cb72e5 WX |
2340 | #ifdef CONFIG_PM |
2341 | .resume = generic_hdmi_resume, | |
2342 | #endif | |
84eb01be TI |
2343 | }; |
2344 | ||
307229d2 | 2345 | static const struct hdmi_ops generic_standard_hdmi_ops = { |
9c32fea8 | 2346 | .pin_get_eld = hdmi_pin_get_eld, |
307229d2 AH |
2347 | .pin_setup_infoframe = hdmi_pin_setup_infoframe, |
2348 | .pin_hbr_setup = hdmi_pin_hbr_setup, | |
2349 | .setup_stream = hdmi_setup_stream, | |
67b90cb8 SP |
2350 | }; |
2351 | ||
a686632f TI |
2352 | /* allocate codec->spec and assign/initialize generic parser ops */ |
2353 | static int alloc_generic_hdmi(struct hda_codec *codec) | |
2354 | { | |
2355 | struct hdmi_spec *spec; | |
2356 | ||
2357 | spec = kzalloc(sizeof(*spec), GFP_KERNEL); | |
2358 | if (!spec) | |
2359 | return -ENOMEM; | |
2360 | ||
ade49db3 | 2361 | spec->codec = codec; |
a686632f | 2362 | spec->ops = generic_standard_hdmi_ops; |
9152085d | 2363 | spec->dev_num = 1; /* initialize to 1 */ |
a686632f | 2364 | mutex_init(&spec->pcm_lock); |
302d5a80 | 2365 | mutex_init(&spec->bind_lock); |
a686632f TI |
2366 | snd_hdac_register_chmap_ops(&codec->core, &spec->chmap); |
2367 | ||
2368 | spec->chmap.ops.get_chmap = hdmi_get_chmap; | |
2369 | spec->chmap.ops.set_chmap = hdmi_set_chmap; | |
2370 | spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached; | |
44fde3b8 | 2371 | spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc, |
a686632f TI |
2372 | |
2373 | codec->spec = spec; | |
2374 | hdmi_array_init(spec, 4); | |
2375 | ||
2376 | codec->patch_ops = generic_hdmi_patch_ops; | |
2377 | ||
2378 | return 0; | |
2379 | } | |
2380 | ||
2381 | /* generic HDMI parser */ | |
2382 | static int patch_generic_hdmi(struct hda_codec *codec) | |
2383 | { | |
2384 | int err; | |
2385 | ||
2386 | err = alloc_generic_hdmi(codec); | |
2387 | if (err < 0) | |
2388 | return err; | |
2389 | ||
2390 | err = hdmi_parse_codec(codec); | |
2391 | if (err < 0) { | |
2392 | generic_spec_free(codec); | |
2393 | return err; | |
2394 | } | |
2395 | ||
2396 | generic_hdmi_init_per_pins(codec); | |
2397 | return 0; | |
2398 | } | |
2399 | ||
ade49db3 TI |
2400 | /* |
2401 | * generic audio component binding | |
2402 | */ | |
2403 | ||
2404 | /* turn on / off the unsol event jack detection dynamically */ | |
2405 | static void reprogram_jack_detect(struct hda_codec *codec, hda_nid_t nid, | |
5204a05d | 2406 | int dev_id, bool use_acomp) |
ade49db3 TI |
2407 | { |
2408 | struct hda_jack_tbl *tbl; | |
2409 | ||
5204a05d | 2410 | tbl = snd_hda_jack_tbl_get_mst(codec, nid, dev_id); |
ade49db3 TI |
2411 | if (tbl) { |
2412 | /* clear unsol even if component notifier is used, or re-enable | |
2413 | * if notifier is cleared | |
2414 | */ | |
2415 | unsigned int val = use_acomp ? 0 : (AC_USRSP_EN | tbl->tag); | |
2416 | snd_hda_codec_write_cache(codec, nid, 0, | |
2417 | AC_VERB_SET_UNSOLICITED_ENABLE, val); | |
ade49db3 TI |
2418 | } |
2419 | } | |
2420 | ||
2421 | /* set up / clear component notifier dynamically */ | |
2422 | static void generic_acomp_notifier_set(struct drm_audio_component *acomp, | |
2423 | bool use_acomp) | |
2424 | { | |
2425 | struct hdmi_spec *spec; | |
2426 | int i; | |
2427 | ||
2428 | spec = container_of(acomp->audio_ops, struct hdmi_spec, drm_audio_ops); | |
302d5a80 | 2429 | mutex_lock(&spec->bind_lock); |
ade49db3 TI |
2430 | spec->use_acomp_notifier = use_acomp; |
2431 | spec->codec->relaxed_resume = use_acomp; | |
2432 | /* reprogram each jack detection logic depending on the notifier */ | |
db845402 TI |
2433 | for (i = 0; i < spec->num_pins; i++) |
2434 | reprogram_jack_detect(spec->codec, | |
2435 | get_pin(spec, i)->pin_nid, | |
2436 | get_pin(spec, i)->dev_id, | |
2437 | use_acomp); | |
302d5a80 | 2438 | mutex_unlock(&spec->bind_lock); |
ade49db3 TI |
2439 | } |
2440 | ||
2441 | /* enable / disable the notifier via master bind / unbind */ | |
2442 | static int generic_acomp_master_bind(struct device *dev, | |
2443 | struct drm_audio_component *acomp) | |
2444 | { | |
2445 | generic_acomp_notifier_set(acomp, true); | |
2446 | return 0; | |
2447 | } | |
2448 | ||
2449 | static void generic_acomp_master_unbind(struct device *dev, | |
2450 | struct drm_audio_component *acomp) | |
2451 | { | |
2452 | generic_acomp_notifier_set(acomp, false); | |
2453 | } | |
2454 | ||
2455 | /* check whether both HD-audio and DRM PCI devices belong to the same bus */ | |
2456 | static int match_bound_vga(struct device *dev, int subtype, void *data) | |
2457 | { | |
2458 | struct hdac_bus *bus = data; | |
2459 | struct pci_dev *pci, *master; | |
2460 | ||
2461 | if (!dev_is_pci(dev) || !dev_is_pci(bus->dev)) | |
2462 | return 0; | |
2463 | master = to_pci_dev(bus->dev); | |
2464 | pci = to_pci_dev(dev); | |
2465 | return master->bus == pci->bus; | |
2466 | } | |
2467 | ||
2468 | /* audio component notifier for AMD/Nvidia HDMI codecs */ | |
2469 | static void generic_acomp_pin_eld_notify(void *audio_ptr, int port, int dev_id) | |
2470 | { | |
2471 | struct hda_codec *codec = audio_ptr; | |
2472 | struct hdmi_spec *spec = codec->spec; | |
2473 | hda_nid_t pin_nid = spec->port2pin(codec, port); | |
2474 | ||
2475 | if (!pin_nid) | |
2476 | return; | |
2477 | if (get_wcaps_type(get_wcaps(codec, pin_nid)) != AC_WID_PIN) | |
2478 | return; | |
2479 | /* skip notification during system suspend (but not in runtime PM); | |
2480 | * the state will be updated at resume | |
2481 | */ | |
2482 | if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0) | |
2483 | return; | |
2484 | /* ditto during suspend/resume process itself */ | |
2485 | if (snd_hdac_is_in_pm(&codec->core)) | |
2486 | return; | |
2487 | ||
2488 | check_presence_and_report(codec, pin_nid, dev_id); | |
2489 | } | |
2490 | ||
2491 | /* set up the private drm_audio_ops from the template */ | |
2492 | static void setup_drm_audio_ops(struct hda_codec *codec, | |
2493 | const struct drm_audio_component_audio_ops *ops) | |
2494 | { | |
2495 | struct hdmi_spec *spec = codec->spec; | |
2496 | ||
2497 | spec->drm_audio_ops.audio_ptr = codec; | |
2498 | /* intel_audio_codec_enable() or intel_audio_codec_disable() | |
2499 | * will call pin_eld_notify with using audio_ptr pointer | |
2500 | * We need make sure audio_ptr is really setup | |
2501 | */ | |
2502 | wmb(); | |
2503 | spec->drm_audio_ops.pin2port = ops->pin2port; | |
2504 | spec->drm_audio_ops.pin_eld_notify = ops->pin_eld_notify; | |
2505 | spec->drm_audio_ops.master_bind = ops->master_bind; | |
2506 | spec->drm_audio_ops.master_unbind = ops->master_unbind; | |
2507 | } | |
2508 | ||
2509 | /* initialize the generic HDMI audio component */ | |
2510 | static void generic_acomp_init(struct hda_codec *codec, | |
2511 | const struct drm_audio_component_audio_ops *ops, | |
2512 | int (*port2pin)(struct hda_codec *, int)) | |
2513 | { | |
2514 | struct hdmi_spec *spec = codec->spec; | |
2515 | ||
b392350e TI |
2516 | if (!enable_acomp) { |
2517 | codec_info(codec, "audio component disabled by module option\n"); | |
2518 | return; | |
2519 | } | |
2520 | ||
ade49db3 TI |
2521 | spec->port2pin = port2pin; |
2522 | setup_drm_audio_ops(codec, ops); | |
2523 | if (!snd_hdac_acomp_init(&codec->bus->core, &spec->drm_audio_ops, | |
dd23e1d5 | 2524 | match_bound_vga, 0)) { |
ade49db3 | 2525 | spec->acomp_registered = true; |
dd23e1d5 TI |
2526 | codec->bus->keep_power = 0; |
2527 | } | |
ade49db3 TI |
2528 | } |
2529 | ||
a686632f TI |
2530 | /* |
2531 | * Intel codec parsers and helpers | |
2532 | */ | |
2533 | ||
b0d8bc50 JK |
2534 | #define INTEL_GET_VENDOR_VERB 0xf81 |
2535 | #define INTEL_SET_VENDOR_VERB 0x781 | |
2536 | #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */ | |
2537 | #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */ | |
1611a9c9 ML |
2538 | |
2539 | static void intel_haswell_enable_all_pins(struct hda_codec *codec, | |
17df3f55 | 2540 | bool update_tree) |
1611a9c9 ML |
2541 | { |
2542 | unsigned int vendor_param; | |
a87a4d23 | 2543 | struct hdmi_spec *spec = codec->spec; |
1611a9c9 | 2544 | |
a87a4d23 | 2545 | vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, |
1611a9c9 ML |
2546 | INTEL_GET_VENDOR_VERB, 0); |
2547 | if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS) | |
2548 | return; | |
2549 | ||
2550 | vendor_param |= INTEL_EN_ALL_PIN_CVTS; | |
a87a4d23 | 2551 | vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, |
1611a9c9 ML |
2552 | INTEL_SET_VENDOR_VERB, vendor_param); |
2553 | if (vendor_param == -1) | |
2554 | return; | |
2555 | ||
17df3f55 TI |
2556 | if (update_tree) |
2557 | snd_hda_codec_update_widgets(codec); | |
1611a9c9 ML |
2558 | } |
2559 | ||
c88d4e84 TI |
2560 | static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec) |
2561 | { | |
2562 | unsigned int vendor_param; | |
a87a4d23 | 2563 | struct hdmi_spec *spec = codec->spec; |
c88d4e84 | 2564 | |
a87a4d23 | 2565 | vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, |
c88d4e84 TI |
2566 | INTEL_GET_VENDOR_VERB, 0); |
2567 | if (vendor_param == -1 || vendor_param & INTEL_EN_DP12) | |
2568 | return; | |
2569 | ||
2570 | /* enable DP1.2 mode */ | |
2571 | vendor_param |= INTEL_EN_DP12; | |
a551d914 | 2572 | snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB); |
a87a4d23 | 2573 | snd_hda_codec_write_cache(codec, spec->vendor_nid, 0, |
c88d4e84 TI |
2574 | INTEL_SET_VENDOR_VERB, vendor_param); |
2575 | } | |
2576 | ||
17df3f55 TI |
2577 | /* Haswell needs to re-issue the vendor-specific verbs before turning to D0. |
2578 | * Otherwise you may get severe h/w communication errors. | |
2579 | */ | |
2580 | static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg, | |
2581 | unsigned int power_state) | |
2582 | { | |
2583 | if (power_state == AC_PWRST_D0) { | |
2584 | intel_haswell_enable_all_pins(codec, false); | |
2585 | intel_haswell_fixup_enable_dp12(codec); | |
2586 | } | |
c88d4e84 | 2587 | |
17df3f55 TI |
2588 | snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state); |
2589 | snd_hda_codec_set_power_to_all(codec, fg, power_state); | |
2590 | } | |
6ffe168f | 2591 | |
a57942bf TI |
2592 | /* There is a fixed mapping between audio pin node and display port. |
2593 | * on SNB, IVY, HSW, BSW, SKL, BXT, KBL: | |
2594 | * Pin Widget 5 - PORT B (port = 1 in i915 driver) | |
2595 | * Pin Widget 6 - PORT C (port = 2 in i915 driver) | |
2596 | * Pin Widget 7 - PORT D (port = 3 in i915 driver) | |
2597 | * | |
2598 | * on VLV, ILK: | |
2599 | * Pin Widget 4 - PORT B (port = 1 in i915 driver) | |
2600 | * Pin Widget 5 - PORT C (port = 2 in i915 driver) | |
2601 | * Pin Widget 6 - PORT D (port = 3 in i915 driver) | |
2602 | */ | |
2603 | static int intel_base_nid(struct hda_codec *codec) | |
2604 | { | |
2605 | switch (codec->core.vendor_id) { | |
2606 | case 0x80860054: /* ILK */ | |
2607 | case 0x80862804: /* ILK */ | |
2608 | case 0x80862882: /* VLV */ | |
2609 | return 4; | |
2610 | default: | |
2611 | return 5; | |
2612 | } | |
2613 | } | |
2614 | ||
2615 | static int intel_pin2port(void *audio_ptr, int pin_nid) | |
2616 | { | |
b0d8bc50 JK |
2617 | struct hda_codec *codec = audio_ptr; |
2618 | struct hdmi_spec *spec = codec->spec; | |
2619 | int base_nid, i; | |
a57942bf | 2620 | |
b0d8bc50 JK |
2621 | if (!spec->port_num) { |
2622 | base_nid = intel_base_nid(codec); | |
2623 | if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3)) | |
2624 | return -1; | |
c8e3eb9b | 2625 | return pin_nid - base_nid + 1; |
b0d8bc50 JK |
2626 | } |
2627 | ||
2628 | /* | |
2629 | * looking for the pin number in the mapping table and return | |
2630 | * the index which indicate the port number | |
2631 | */ | |
2632 | for (i = 0; i < spec->port_num; i++) { | |
2633 | if (pin_nid == spec->port_map[i]) | |
d577cf76 | 2634 | return i; |
b0d8bc50 JK |
2635 | } |
2636 | ||
b0d8bc50 JK |
2637 | codec_info(codec, "Can't find the HDMI/DP port for pin %d\n", pin_nid); |
2638 | return -1; | |
a57942bf TI |
2639 | } |
2640 | ||
3140aafb TI |
2641 | static int intel_port2pin(struct hda_codec *codec, int port) |
2642 | { | |
2643 | struct hdmi_spec *spec = codec->spec; | |
2644 | ||
2645 | if (!spec->port_num) { | |
2646 | /* we assume only from port-B to port-D */ | |
2647 | if (port < 1 || port > 3) | |
2648 | return 0; | |
3140aafb TI |
2649 | return port + intel_base_nid(codec) - 1; |
2650 | } | |
2651 | ||
d577cf76 | 2652 | if (port < 0 || port >= spec->port_num) |
3140aafb | 2653 | return 0; |
d577cf76 | 2654 | return spec->port_map[port]; |
3140aafb TI |
2655 | } |
2656 | ||
f9318941 | 2657 | static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe) |
25adc137 DH |
2658 | { |
2659 | struct hda_codec *codec = audio_ptr; | |
7ff652ff | 2660 | int pin_nid; |
9152085d | 2661 | int dev_id = pipe; |
25adc137 | 2662 | |
3140aafb TI |
2663 | pin_nid = intel_port2pin(codec, port); |
2664 | if (!pin_nid) | |
4f8e4f35 | 2665 | return; |
8ae743e8 TI |
2666 | /* skip notification during system suspend (but not in runtime PM); |
2667 | * the state will be updated at resume | |
2668 | */ | |
2669 | if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0) | |
2670 | return; | |
eb399d3c | 2671 | /* ditto during suspend/resume process itself */ |
feb20fae | 2672 | if (snd_hdac_is_in_pm(&codec->core)) |
eb399d3c | 2673 | return; |
8ae743e8 | 2674 | |
bb03ed21 | 2675 | snd_hdac_i915_set_bclk(&codec->bus->core); |
9152085d | 2676 | check_presence_and_report(codec, pin_nid, dev_id); |
25adc137 DH |
2677 | } |
2678 | ||
ade49db3 TI |
2679 | static const struct drm_audio_component_audio_ops intel_audio_ops = { |
2680 | .pin2port = intel_pin2port, | |
2681 | .pin_eld_notify = intel_pin_eld_notify, | |
2682 | }; | |
2683 | ||
a686632f TI |
2684 | /* register i915 component pin_eld_notify callback */ |
2685 | static void register_i915_notifier(struct hda_codec *codec) | |
84eb01be | 2686 | { |
a686632f | 2687 | struct hdmi_spec *spec = codec->spec; |
84eb01be | 2688 | |
a686632f | 2689 | spec->use_acomp_notifier = true; |
ade49db3 TI |
2690 | spec->port2pin = intel_port2pin; |
2691 | setup_drm_audio_ops(codec, &intel_audio_ops); | |
a57942bf | 2692 | snd_hdac_acomp_register_notifier(&codec->bus->core, |
82887c0b | 2693 | &spec->drm_audio_ops); |
4914da2f TI |
2694 | /* no need for forcible resume for jack check thanks to notifier */ |
2695 | codec->relaxed_resume = 1; | |
a686632f | 2696 | } |
84eb01be | 2697 | |
2c1c9b86 TI |
2698 | /* setup_stream ops override for HSW+ */ |
2699 | static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, | |
9c32fea8 NM |
2700 | hda_nid_t pin_nid, int dev_id, u32 stream_tag, |
2701 | int format) | |
2c1c9b86 TI |
2702 | { |
2703 | haswell_verify_D0(codec, cvt_nid, pin_nid); | |
9c32fea8 NM |
2704 | return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id, |
2705 | stream_tag, format); | |
2c1c9b86 | 2706 | } |
739ffee9 | 2707 | |
4846a67e TI |
2708 | /* pin_cvt_fixup ops override for HSW+ and VLV+ */ |
2709 | static void i915_pin_cvt_fixup(struct hda_codec *codec, | |
2710 | struct hdmi_spec_per_pin *per_pin, | |
2711 | hda_nid_t cvt_nid) | |
2712 | { | |
2713 | if (per_pin) { | |
9152085d LY |
2714 | snd_hda_set_dev_select(codec, per_pin->pin_nid, |
2715 | per_pin->dev_id); | |
4846a67e TI |
2716 | intel_verify_pin_cvt_connect(codec, per_pin); |
2717 | intel_not_share_assigned_cvt(codec, per_pin->pin_nid, | |
9152085d | 2718 | per_pin->dev_id, per_pin->mux_idx); |
4846a67e | 2719 | } else { |
9152085d | 2720 | intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid); |
4846a67e TI |
2721 | } |
2722 | } | |
739ffee9 | 2723 | |
43f6c8d9 TI |
2724 | /* precondition and allocation for Intel codecs */ |
2725 | static int alloc_intel_hdmi(struct hda_codec *codec) | |
a686632f | 2726 | { |
f2dbe87c TI |
2727 | int err; |
2728 | ||
43f6c8d9 | 2729 | /* requires i915 binding */ |
a686632f TI |
2730 | if (!codec->bus->core.audio_component) { |
2731 | codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n"); | |
fdd49c51 TI |
2732 | /* set probe_id here to prevent generic fallback binding */ |
2733 | codec->probe_id = HDA_CODEC_ID_SKIP_PROBE; | |
a686632f | 2734 | return -ENODEV; |
691be973 | 2735 | } |
55913110 | 2736 | |
f2dbe87c TI |
2737 | err = alloc_generic_hdmi(codec); |
2738 | if (err < 0) | |
2739 | return err; | |
2740 | /* no need to handle unsol events */ | |
2741 | codec->patch_ops.unsol_event = NULL; | |
2742 | return 0; | |
43f6c8d9 TI |
2743 | } |
2744 | ||
2745 | /* parse and post-process for Intel codecs */ | |
2746 | static int parse_intel_hdmi(struct hda_codec *codec) | |
2747 | { | |
2928fa0a KV |
2748 | int err, retries = 3; |
2749 | ||
2750 | do { | |
2751 | err = hdmi_parse_codec(codec); | |
2752 | } while (err < 0 && retries--); | |
43f6c8d9 | 2753 | |
43f6c8d9 TI |
2754 | if (err < 0) { |
2755 | generic_spec_free(codec); | |
2756 | return err; | |
2757 | } | |
2758 | ||
2759 | generic_hdmi_init_per_pins(codec); | |
2760 | register_i915_notifier(codec); | |
2761 | return 0; | |
2762 | } | |
2763 | ||
2764 | /* Intel Haswell and onwards; audio component with eld notifier */ | |
b0d8bc50 JK |
2765 | static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid, |
2766 | const int *port_map, int port_num) | |
43f6c8d9 TI |
2767 | { |
2768 | struct hdmi_spec *spec; | |
2769 | int err; | |
2770 | ||
2771 | err = alloc_intel_hdmi(codec); | |
a686632f TI |
2772 | if (err < 0) |
2773 | return err; | |
2774 | spec = codec->spec; | |
9152085d LY |
2775 | codec->dp_mst = true; |
2776 | spec->dyn_pcm_assign = true; | |
a87a4d23 | 2777 | spec->vendor_nid = vendor_nid; |
b0d8bc50 JK |
2778 | spec->port_map = port_map; |
2779 | spec->port_num = port_num; | |
cb45722b | 2780 | spec->intel_hsw_fixup = true; |
6ffe168f | 2781 | |
a686632f TI |
2782 | intel_haswell_enable_all_pins(codec, true); |
2783 | intel_haswell_fixup_enable_dp12(codec); | |
2784 | ||
46594d33 | 2785 | codec->display_power_control = 1; |
2bd1f73f | 2786 | |
a686632f | 2787 | codec->patch_ops.set_power_state = haswell_set_power_state; |
a686632f TI |
2788 | codec->depop_delay = 0; |
2789 | codec->auto_runtime_pm = 1; | |
2790 | ||
2c1c9b86 | 2791 | spec->ops.setup_stream = i915_hsw_setup_stream; |
4846a67e | 2792 | spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; |
2c1c9b86 | 2793 | |
43f6c8d9 | 2794 | return parse_intel_hdmi(codec); |
a686632f TI |
2795 | } |
2796 | ||
a87a4d23 ACDO |
2797 | static int patch_i915_hsw_hdmi(struct hda_codec *codec) |
2798 | { | |
b0d8bc50 | 2799 | return intel_hsw_common_init(codec, 0x08, NULL, 0); |
a87a4d23 ACDO |
2800 | } |
2801 | ||
2802 | static int patch_i915_glk_hdmi(struct hda_codec *codec) | |
2803 | { | |
b0d8bc50 JK |
2804 | return intel_hsw_common_init(codec, 0x0b, NULL, 0); |
2805 | } | |
2806 | ||
2807 | static int patch_i915_icl_hdmi(struct hda_codec *codec) | |
2808 | { | |
2809 | /* | |
2810 | * pin to port mapping table where the value indicate the pin number and | |
d577cf76 | 2811 | * the index indicate the port number. |
b0d8bc50 | 2812 | */ |
d577cf76 | 2813 | static const int map[] = {0x0, 0x4, 0x6, 0x8, 0xa, 0xb}; |
b0d8bc50 JK |
2814 | |
2815 | return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map)); | |
a87a4d23 ACDO |
2816 | } |
2817 | ||
9a11ba73 KV |
2818 | static int patch_i915_tgl_hdmi(struct hda_codec *codec) |
2819 | { | |
2820 | /* | |
2821 | * pin to port mapping table where the value indicate the pin number and | |
d577cf76 | 2822 | * the index indicate the port number. |
9a11ba73 KV |
2823 | */ |
2824 | static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf}; | |
2825 | ||
2826 | return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map)); | |
2827 | } | |
2828 | ||
7ff652ff | 2829 | /* Intel Baytrail and Braswell; with eld notifier */ |
a686632f TI |
2830 | static int patch_i915_byt_hdmi(struct hda_codec *codec) |
2831 | { | |
2832 | struct hdmi_spec *spec; | |
2833 | int err; | |
2834 | ||
43f6c8d9 | 2835 | err = alloc_intel_hdmi(codec); |
a686632f TI |
2836 | if (err < 0) |
2837 | return err; | |
2838 | spec = codec->spec; | |
2377c3c3 | 2839 | |
a686632f TI |
2840 | /* For Valleyview/Cherryview, only the display codec is in the display |
2841 | * power well and can use link_power ops to request/release the power. | |
2842 | */ | |
029d92c2 | 2843 | codec->display_power_control = 1; |
84eb01be | 2844 | |
a686632f TI |
2845 | codec->depop_delay = 0; |
2846 | codec->auto_runtime_pm = 1; | |
84eb01be | 2847 | |
4846a67e TI |
2848 | spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; |
2849 | ||
43f6c8d9 | 2850 | return parse_intel_hdmi(codec); |
84eb01be TI |
2851 | } |
2852 | ||
7ff652ff | 2853 | /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */ |
e85015a3 TI |
2854 | static int patch_i915_cpt_hdmi(struct hda_codec *codec) |
2855 | { | |
e85015a3 TI |
2856 | int err; |
2857 | ||
43f6c8d9 | 2858 | err = alloc_intel_hdmi(codec); |
e85015a3 TI |
2859 | if (err < 0) |
2860 | return err; | |
43f6c8d9 | 2861 | return parse_intel_hdmi(codec); |
84eb01be TI |
2862 | } |
2863 | ||
3aaf8980 SW |
2864 | /* |
2865 | * Shared non-generic implementations | |
2866 | */ | |
2867 | ||
2868 | static int simple_playback_build_pcms(struct hda_codec *codec) | |
2869 | { | |
2870 | struct hdmi_spec *spec = codec->spec; | |
bce0d2a8 | 2871 | struct hda_pcm *info; |
8ceb332d TI |
2872 | unsigned int chans; |
2873 | struct hda_pcm_stream *pstr; | |
bce0d2a8 | 2874 | struct hdmi_spec_per_cvt *per_cvt; |
3aaf8980 | 2875 | |
bce0d2a8 TI |
2876 | per_cvt = get_cvt(spec, 0); |
2877 | chans = get_wcaps(codec, per_cvt->cvt_nid); | |
8ceb332d | 2878 | chans = get_wcaps_channels(chans); |
3aaf8980 | 2879 | |
bbbc7e85 | 2880 | info = snd_hda_codec_pcm_new(codec, "HDMI 0"); |
bce0d2a8 TI |
2881 | if (!info) |
2882 | return -ENOMEM; | |
2bea241a | 2883 | spec->pcm_rec[0].pcm = info; |
8ceb332d TI |
2884 | info->pcm_type = HDA_PCM_TYPE_HDMI; |
2885 | pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; | |
2886 | *pstr = spec->pcm_playback; | |
bce0d2a8 | 2887 | pstr->nid = per_cvt->cvt_nid; |
8ceb332d TI |
2888 | if (pstr->channels_max <= 2 && chans && chans <= 16) |
2889 | pstr->channels_max = chans; | |
3aaf8980 SW |
2890 | |
2891 | return 0; | |
2892 | } | |
2893 | ||
4b6ace9e TI |
2894 | /* unsolicited event for jack sensing */ |
2895 | static void simple_hdmi_unsol_event(struct hda_codec *codec, | |
2896 | unsigned int res) | |
2897 | { | |
9dd8cf12 | 2898 | snd_hda_jack_set_dirty_all(codec); |
4b6ace9e TI |
2899 | snd_hda_jack_report_sync(codec); |
2900 | } | |
2901 | ||
2902 | /* generic_hdmi_build_jack can be used for simple_hdmi, too, | |
2903 | * as long as spec->pins[] is set correctly | |
2904 | */ | |
2905 | #define simple_hdmi_build_jack generic_hdmi_build_jack | |
2906 | ||
3aaf8980 SW |
2907 | static int simple_playback_build_controls(struct hda_codec *codec) |
2908 | { | |
2909 | struct hdmi_spec *spec = codec->spec; | |
bce0d2a8 | 2910 | struct hdmi_spec_per_cvt *per_cvt; |
3aaf8980 | 2911 | int err; |
3aaf8980 | 2912 | |
bce0d2a8 | 2913 | per_cvt = get_cvt(spec, 0); |
c9a6338a AH |
2914 | err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid, |
2915 | per_cvt->cvt_nid, | |
2916 | HDA_PCM_TYPE_HDMI); | |
8ceb332d TI |
2917 | if (err < 0) |
2918 | return err; | |
2919 | return simple_hdmi_build_jack(codec, 0); | |
3aaf8980 SW |
2920 | } |
2921 | ||
4f0110ce TI |
2922 | static int simple_playback_init(struct hda_codec *codec) |
2923 | { | |
2924 | struct hdmi_spec *spec = codec->spec; | |
bce0d2a8 TI |
2925 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0); |
2926 | hda_nid_t pin = per_pin->pin_nid; | |
8ceb332d TI |
2927 | |
2928 | snd_hda_codec_write(codec, pin, 0, | |
2929 | AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT); | |
2930 | /* some codecs require to unmute the pin */ | |
2931 | if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) | |
2932 | snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE, | |
2933 | AMP_OUT_UNMUTE); | |
5204a05d | 2934 | snd_hda_jack_detect_enable(codec, pin, per_pin->dev_id); |
4f0110ce TI |
2935 | return 0; |
2936 | } | |
2937 | ||
3aaf8980 SW |
2938 | static void simple_playback_free(struct hda_codec *codec) |
2939 | { | |
2940 | struct hdmi_spec *spec = codec->spec; | |
2941 | ||
bce0d2a8 | 2942 | hdmi_array_free(spec); |
3aaf8980 SW |
2943 | kfree(spec); |
2944 | } | |
2945 | ||
84eb01be TI |
2946 | /* |
2947 | * Nvidia specific implementations | |
2948 | */ | |
2949 | ||
2950 | #define Nv_VERB_SET_Channel_Allocation 0xF79 | |
2951 | #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A | |
2952 | #define Nv_VERB_SET_Audio_Protection_On 0xF98 | |
2953 | #define Nv_VERB_SET_Audio_Protection_Off 0xF99 | |
2954 | ||
2955 | #define nvhdmi_master_con_nid_7x 0x04 | |
2956 | #define nvhdmi_master_pin_nid_7x 0x05 | |
2957 | ||
fb79e1e0 | 2958 | static const hda_nid_t nvhdmi_con_nids_7x[4] = { |
84eb01be TI |
2959 | /*front, rear, clfe, rear_surr */ |
2960 | 0x6, 0x8, 0xa, 0xc, | |
2961 | }; | |
2962 | ||
ceaa86ba TI |
2963 | static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = { |
2964 | /* set audio protect on */ | |
2965 | { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, | |
2966 | /* enable digital output on pin widget */ | |
2967 | { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, | |
2968 | {} /* terminator */ | |
2969 | }; | |
2970 | ||
2971 | static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = { | |
84eb01be TI |
2972 | /* set audio protect on */ |
2973 | { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, | |
2974 | /* enable digital output on pin widget */ | |
2975 | { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, | |
2976 | { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, | |
2977 | { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, | |
2978 | { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, | |
2979 | { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, | |
2980 | {} /* terminator */ | |
2981 | }; | |
2982 | ||
2983 | #ifdef LIMITED_RATE_FMT_SUPPORT | |
2984 | /* support only the safe format and rate */ | |
2985 | #define SUPPORTED_RATES SNDRV_PCM_RATE_48000 | |
2986 | #define SUPPORTED_MAXBPS 16 | |
2987 | #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE | |
2988 | #else | |
2989 | /* support all rates and formats */ | |
2990 | #define SUPPORTED_RATES \ | |
2991 | (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\ | |
2992 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\ | |
2993 | SNDRV_PCM_RATE_192000) | |
2994 | #define SUPPORTED_MAXBPS 24 | |
2995 | #define SUPPORTED_FORMATS \ | |
2996 | (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) | |
2997 | #endif | |
2998 | ||
ceaa86ba TI |
2999 | static int nvhdmi_7x_init_2ch(struct hda_codec *codec) |
3000 | { | |
3001 | snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch); | |
3002 | return 0; | |
3003 | } | |
3004 | ||
3005 | static int nvhdmi_7x_init_8ch(struct hda_codec *codec) | |
84eb01be | 3006 | { |
ceaa86ba | 3007 | snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch); |
84eb01be TI |
3008 | return 0; |
3009 | } | |
3010 | ||
50c697ad | 3011 | static const unsigned int channels_2_6_8[] = { |
393004b2 ND |
3012 | 2, 6, 8 |
3013 | }; | |
3014 | ||
50c697ad | 3015 | static const unsigned int channels_2_8[] = { |
393004b2 ND |
3016 | 2, 8 |
3017 | }; | |
3018 | ||
50c697ad | 3019 | static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = { |
393004b2 ND |
3020 | .count = ARRAY_SIZE(channels_2_6_8), |
3021 | .list = channels_2_6_8, | |
3022 | .mask = 0, | |
3023 | }; | |
3024 | ||
50c697ad | 3025 | static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = { |
393004b2 ND |
3026 | .count = ARRAY_SIZE(channels_2_8), |
3027 | .list = channels_2_8, | |
3028 | .mask = 0, | |
3029 | }; | |
3030 | ||
84eb01be TI |
3031 | static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo, |
3032 | struct hda_codec *codec, | |
3033 | struct snd_pcm_substream *substream) | |
3034 | { | |
3035 | struct hdmi_spec *spec = codec->spec; | |
50c697ad | 3036 | const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL; |
393004b2 | 3037 | |
b9a94a9c | 3038 | switch (codec->preset->vendor_id) { |
393004b2 ND |
3039 | case 0x10de0002: |
3040 | case 0x10de0003: | |
3041 | case 0x10de0005: | |
3042 | case 0x10de0006: | |
3043 | hw_constraints_channels = &hw_constraints_2_8_channels; | |
3044 | break; | |
3045 | case 0x10de0007: | |
3046 | hw_constraints_channels = &hw_constraints_2_6_8_channels; | |
3047 | break; | |
3048 | default: | |
3049 | break; | |
3050 | } | |
3051 | ||
3052 | if (hw_constraints_channels != NULL) { | |
3053 | snd_pcm_hw_constraint_list(substream->runtime, 0, | |
3054 | SNDRV_PCM_HW_PARAM_CHANNELS, | |
3055 | hw_constraints_channels); | |
ad09fc9d TI |
3056 | } else { |
3057 | snd_pcm_hw_constraint_step(substream->runtime, 0, | |
3058 | SNDRV_PCM_HW_PARAM_CHANNELS, 2); | |
393004b2 ND |
3059 | } |
3060 | ||
84eb01be TI |
3061 | return snd_hda_multi_out_dig_open(codec, &spec->multiout); |
3062 | } | |
3063 | ||
3064 | static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo, | |
3065 | struct hda_codec *codec, | |
3066 | struct snd_pcm_substream *substream) | |
3067 | { | |
3068 | struct hdmi_spec *spec = codec->spec; | |
3069 | return snd_hda_multi_out_dig_close(codec, &spec->multiout); | |
3070 | } | |
3071 | ||
3072 | static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo, | |
3073 | struct hda_codec *codec, | |
3074 | unsigned int stream_tag, | |
3075 | unsigned int format, | |
3076 | struct snd_pcm_substream *substream) | |
3077 | { | |
3078 | struct hdmi_spec *spec = codec->spec; | |
3079 | return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, | |
3080 | stream_tag, format, substream); | |
3081 | } | |
3082 | ||
d0b1252d TI |
3083 | static const struct hda_pcm_stream simple_pcm_playback = { |
3084 | .substreams = 1, | |
3085 | .channels_min = 2, | |
3086 | .channels_max = 2, | |
3087 | .ops = { | |
3088 | .open = simple_playback_pcm_open, | |
3089 | .close = simple_playback_pcm_close, | |
3090 | .prepare = simple_playback_pcm_prepare | |
3091 | }, | |
3092 | }; | |
3093 | ||
3094 | static const struct hda_codec_ops simple_hdmi_patch_ops = { | |
3095 | .build_controls = simple_playback_build_controls, | |
3096 | .build_pcms = simple_playback_build_pcms, | |
3097 | .init = simple_playback_init, | |
3098 | .free = simple_playback_free, | |
250e41ac | 3099 | .unsol_event = simple_hdmi_unsol_event, |
d0b1252d TI |
3100 | }; |
3101 | ||
3102 | static int patch_simple_hdmi(struct hda_codec *codec, | |
3103 | hda_nid_t cvt_nid, hda_nid_t pin_nid) | |
3104 | { | |
3105 | struct hdmi_spec *spec; | |
bce0d2a8 TI |
3106 | struct hdmi_spec_per_cvt *per_cvt; |
3107 | struct hdmi_spec_per_pin *per_pin; | |
d0b1252d TI |
3108 | |
3109 | spec = kzalloc(sizeof(*spec), GFP_KERNEL); | |
3110 | if (!spec) | |
3111 | return -ENOMEM; | |
3112 | ||
ade49db3 | 3113 | spec->codec = codec; |
d0b1252d | 3114 | codec->spec = spec; |
bce0d2a8 | 3115 | hdmi_array_init(spec, 1); |
d0b1252d TI |
3116 | |
3117 | spec->multiout.num_dacs = 0; /* no analog */ | |
3118 | spec->multiout.max_channels = 2; | |
3119 | spec->multiout.dig_out_nid = cvt_nid; | |
3120 | spec->num_cvts = 1; | |
3121 | spec->num_pins = 1; | |
bce0d2a8 TI |
3122 | per_pin = snd_array_new(&spec->pins); |
3123 | per_cvt = snd_array_new(&spec->cvts); | |
3124 | if (!per_pin || !per_cvt) { | |
3125 | simple_playback_free(codec); | |
3126 | return -ENOMEM; | |
3127 | } | |
3128 | per_cvt->cvt_nid = cvt_nid; | |
3129 | per_pin->pin_nid = pin_nid; | |
d0b1252d TI |
3130 | spec->pcm_playback = simple_pcm_playback; |
3131 | ||
3132 | codec->patch_ops = simple_hdmi_patch_ops; | |
3133 | ||
3134 | return 0; | |
3135 | } | |
3136 | ||
1f348522 AP |
3137 | static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec, |
3138 | int channels) | |
3139 | { | |
3140 | unsigned int chanmask; | |
3141 | int chan = channels ? (channels - 1) : 1; | |
3142 | ||
3143 | switch (channels) { | |
3144 | default: | |
3145 | case 0: | |
3146 | case 2: | |
3147 | chanmask = 0x00; | |
3148 | break; | |
3149 | case 4: | |
3150 | chanmask = 0x08; | |
3151 | break; | |
3152 | case 6: | |
3153 | chanmask = 0x0b; | |
3154 | break; | |
3155 | case 8: | |
3156 | chanmask = 0x13; | |
3157 | break; | |
3158 | } | |
3159 | ||
3160 | /* Set the audio infoframe channel allocation and checksum fields. The | |
3161 | * channel count is computed implicitly by the hardware. */ | |
3162 | snd_hda_codec_write(codec, 0x1, 0, | |
3163 | Nv_VERB_SET_Channel_Allocation, chanmask); | |
3164 | ||
3165 | snd_hda_codec_write(codec, 0x1, 0, | |
3166 | Nv_VERB_SET_Info_Frame_Checksum, | |
3167 | (0x71 - chan - chanmask)); | |
3168 | } | |
3169 | ||
84eb01be TI |
3170 | static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo, |
3171 | struct hda_codec *codec, | |
3172 | struct snd_pcm_substream *substream) | |
3173 | { | |
3174 | struct hdmi_spec *spec = codec->spec; | |
3175 | int i; | |
3176 | ||
3177 | snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, | |
3178 | 0, AC_VERB_SET_CHANNEL_STREAMID, 0); | |
3179 | for (i = 0; i < 4; i++) { | |
3180 | /* set the stream id */ | |
3181 | snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, | |
3182 | AC_VERB_SET_CHANNEL_STREAMID, 0); | |
3183 | /* set the stream format */ | |
3184 | snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, | |
3185 | AC_VERB_SET_STREAM_FORMAT, 0); | |
3186 | } | |
3187 | ||
1f348522 AP |
3188 | /* The audio hardware sends a channel count of 0x7 (8ch) when all the |
3189 | * streams are disabled. */ | |
3190 | nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); | |
3191 | ||
84eb01be TI |
3192 | return snd_hda_multi_out_dig_close(codec, &spec->multiout); |
3193 | } | |
3194 | ||
3195 | static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo, | |
3196 | struct hda_codec *codec, | |
3197 | unsigned int stream_tag, | |
3198 | unsigned int format, | |
3199 | struct snd_pcm_substream *substream) | |
3200 | { | |
3201 | int chs; | |
112daa7a | 3202 | unsigned int dataDCC2, channel_id; |
84eb01be | 3203 | int i; |
7c935976 | 3204 | struct hdmi_spec *spec = codec->spec; |
e3245cdd | 3205 | struct hda_spdif_out *spdif; |
bce0d2a8 | 3206 | struct hdmi_spec_per_cvt *per_cvt; |
84eb01be TI |
3207 | |
3208 | mutex_lock(&codec->spdif_mutex); | |
bce0d2a8 TI |
3209 | per_cvt = get_cvt(spec, 0); |
3210 | spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid); | |
84eb01be TI |
3211 | |
3212 | chs = substream->runtime->channels; | |
84eb01be | 3213 | |
84eb01be TI |
3214 | dataDCC2 = 0x2; |
3215 | ||
84eb01be | 3216 | /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */ |
7c935976 | 3217 | if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) |
84eb01be TI |
3218 | snd_hda_codec_write(codec, |
3219 | nvhdmi_master_con_nid_7x, | |
3220 | 0, | |
3221 | AC_VERB_SET_DIGI_CONVERT_1, | |
7c935976 | 3222 | spdif->ctls & ~AC_DIG1_ENABLE & 0xff); |
84eb01be TI |
3223 | |
3224 | /* set the stream id */ | |
3225 | snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, | |
3226 | AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0); | |
3227 | ||
3228 | /* set the stream format */ | |
3229 | snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, | |
3230 | AC_VERB_SET_STREAM_FORMAT, format); | |
3231 | ||
3232 | /* turn on again (if needed) */ | |
3233 | /* enable and set the channel status audio/data flag */ | |
7c935976 | 3234 | if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) { |
84eb01be TI |
3235 | snd_hda_codec_write(codec, |
3236 | nvhdmi_master_con_nid_7x, | |
3237 | 0, | |
3238 | AC_VERB_SET_DIGI_CONVERT_1, | |
7c935976 | 3239 | spdif->ctls & 0xff); |
84eb01be TI |
3240 | snd_hda_codec_write(codec, |
3241 | nvhdmi_master_con_nid_7x, | |
3242 | 0, | |
3243 | AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); | |
3244 | } | |
3245 | ||
3246 | for (i = 0; i < 4; i++) { | |
3247 | if (chs == 2) | |
3248 | channel_id = 0; | |
3249 | else | |
3250 | channel_id = i * 2; | |
3251 | ||
3252 | /* turn off SPDIF once; | |
3253 | *otherwise the IEC958 bits won't be updated | |
3254 | */ | |
3255 | if (codec->spdif_status_reset && | |
7c935976 | 3256 | (spdif->ctls & AC_DIG1_ENABLE)) |
84eb01be TI |
3257 | snd_hda_codec_write(codec, |
3258 | nvhdmi_con_nids_7x[i], | |
3259 | 0, | |
3260 | AC_VERB_SET_DIGI_CONVERT_1, | |
7c935976 | 3261 | spdif->ctls & ~AC_DIG1_ENABLE & 0xff); |
84eb01be TI |
3262 | /* set the stream id */ |
3263 | snd_hda_codec_write(codec, | |
3264 | nvhdmi_con_nids_7x[i], | |
3265 | 0, | |
3266 | AC_VERB_SET_CHANNEL_STREAMID, | |
3267 | (stream_tag << 4) | channel_id); | |
3268 | /* set the stream format */ | |
3269 | snd_hda_codec_write(codec, | |
3270 | nvhdmi_con_nids_7x[i], | |
3271 | 0, | |
3272 | AC_VERB_SET_STREAM_FORMAT, | |
3273 | format); | |
3274 | /* turn on again (if needed) */ | |
3275 | /* enable and set the channel status audio/data flag */ | |
3276 | if (codec->spdif_status_reset && | |
7c935976 | 3277 | (spdif->ctls & AC_DIG1_ENABLE)) { |
84eb01be TI |
3278 | snd_hda_codec_write(codec, |
3279 | nvhdmi_con_nids_7x[i], | |
3280 | 0, | |
3281 | AC_VERB_SET_DIGI_CONVERT_1, | |
7c935976 | 3282 | spdif->ctls & 0xff); |
84eb01be TI |
3283 | snd_hda_codec_write(codec, |
3284 | nvhdmi_con_nids_7x[i], | |
3285 | 0, | |
3286 | AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); | |
3287 | } | |
3288 | } | |
3289 | ||
1f348522 | 3290 | nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs); |
84eb01be TI |
3291 | |
3292 | mutex_unlock(&codec->spdif_mutex); | |
3293 | return 0; | |
3294 | } | |
3295 | ||
fb79e1e0 | 3296 | static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = { |
84eb01be TI |
3297 | .substreams = 1, |
3298 | .channels_min = 2, | |
3299 | .channels_max = 8, | |
3300 | .nid = nvhdmi_master_con_nid_7x, | |
3301 | .rates = SUPPORTED_RATES, | |
3302 | .maxbps = SUPPORTED_MAXBPS, | |
3303 | .formats = SUPPORTED_FORMATS, | |
3304 | .ops = { | |
3305 | .open = simple_playback_pcm_open, | |
3306 | .close = nvhdmi_8ch_7x_pcm_close, | |
3307 | .prepare = nvhdmi_8ch_7x_pcm_prepare | |
3308 | }, | |
3309 | }; | |
3310 | ||
84eb01be TI |
3311 | static int patch_nvhdmi_2ch(struct hda_codec *codec) |
3312 | { | |
3313 | struct hdmi_spec *spec; | |
d0b1252d TI |
3314 | int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x, |
3315 | nvhdmi_master_pin_nid_7x); | |
3316 | if (err < 0) | |
3317 | return err; | |
84eb01be | 3318 | |
ceaa86ba | 3319 | codec->patch_ops.init = nvhdmi_7x_init_2ch; |
d0b1252d TI |
3320 | /* override the PCM rates, etc, as the codec doesn't give full list */ |
3321 | spec = codec->spec; | |
3322 | spec->pcm_playback.rates = SUPPORTED_RATES; | |
3323 | spec->pcm_playback.maxbps = SUPPORTED_MAXBPS; | |
3324 | spec->pcm_playback.formats = SUPPORTED_FORMATS; | |
84eb01be TI |
3325 | return 0; |
3326 | } | |
3327 | ||
53775b0d TI |
3328 | static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec) |
3329 | { | |
3330 | struct hdmi_spec *spec = codec->spec; | |
3331 | int err = simple_playback_build_pcms(codec); | |
bce0d2a8 TI |
3332 | if (!err) { |
3333 | struct hda_pcm *info = get_pcm_rec(spec, 0); | |
3334 | info->own_chmap = true; | |
3335 | } | |
53775b0d TI |
3336 | return err; |
3337 | } | |
3338 | ||
3339 | static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec) | |
3340 | { | |
3341 | struct hdmi_spec *spec = codec->spec; | |
bce0d2a8 | 3342 | struct hda_pcm *info; |
53775b0d TI |
3343 | struct snd_pcm_chmap *chmap; |
3344 | int err; | |
3345 | ||
3346 | err = simple_playback_build_controls(codec); | |
3347 | if (err < 0) | |
3348 | return err; | |
3349 | ||
3350 | /* add channel maps */ | |
bce0d2a8 TI |
3351 | info = get_pcm_rec(spec, 0); |
3352 | err = snd_pcm_add_chmap_ctls(info->pcm, | |
53775b0d TI |
3353 | SNDRV_PCM_STREAM_PLAYBACK, |
3354 | snd_pcm_alt_chmaps, 8, 0, &chmap); | |
3355 | if (err < 0) | |
3356 | return err; | |
b9a94a9c | 3357 | switch (codec->preset->vendor_id) { |
53775b0d TI |
3358 | case 0x10de0002: |
3359 | case 0x10de0003: | |
3360 | case 0x10de0005: | |
3361 | case 0x10de0006: | |
3362 | chmap->channel_mask = (1U << 2) | (1U << 8); | |
3363 | break; | |
3364 | case 0x10de0007: | |
3365 | chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8); | |
3366 | } | |
3367 | return 0; | |
3368 | } | |
3369 | ||
84eb01be TI |
3370 | static int patch_nvhdmi_8ch_7x(struct hda_codec *codec) |
3371 | { | |
3372 | struct hdmi_spec *spec; | |
3373 | int err = patch_nvhdmi_2ch(codec); | |
84eb01be TI |
3374 | if (err < 0) |
3375 | return err; | |
3376 | spec = codec->spec; | |
3377 | spec->multiout.max_channels = 8; | |
d0b1252d | 3378 | spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x; |
ceaa86ba | 3379 | codec->patch_ops.init = nvhdmi_7x_init_8ch; |
53775b0d TI |
3380 | codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms; |
3381 | codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls; | |
1f348522 AP |
3382 | |
3383 | /* Initialize the audio infoframe channel mask and checksum to something | |
3384 | * valid */ | |
3385 | nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); | |
3386 | ||
84eb01be TI |
3387 | return 0; |
3388 | } | |
3389 | ||
611885bc AH |
3390 | /* |
3391 | * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on: | |
3392 | * - 0x10de0015 | |
3393 | * - 0x10de0040 | |
3394 | */ | |
67b90cb8 | 3395 | static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap, |
f302240d | 3396 | struct hdac_cea_channel_speaker_allocation *cap, int channels) |
611885bc AH |
3397 | { |
3398 | if (cap->ca_index == 0x00 && channels == 2) | |
3399 | return SNDRV_CTL_TLVT_CHMAP_FIXED; | |
3400 | ||
028cb68e SP |
3401 | /* If the speaker allocation matches the channel count, it is OK. */ |
3402 | if (cap->channels != channels) | |
3403 | return -1; | |
3404 | ||
3405 | /* all channels are remappable freely */ | |
3406 | return SNDRV_CTL_TLVT_CHMAP_VAR; | |
611885bc AH |
3407 | } |
3408 | ||
828cb4ed SP |
3409 | static int nvhdmi_chmap_validate(struct hdac_chmap *chmap, |
3410 | int ca, int chs, unsigned char *map) | |
611885bc AH |
3411 | { |
3412 | if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR)) | |
3413 | return -EINVAL; | |
3414 | ||
3415 | return 0; | |
3416 | } | |
3417 | ||
ade49db3 TI |
3418 | /* map from pin NID to port; port is 0-based */ |
3419 | /* for Nvidia: assume widget NID starting from 4, with step 1 (4, 5, 6, ...) */ | |
3420 | static int nvhdmi_pin2port(void *audio_ptr, int pin_nid) | |
3421 | { | |
3422 | return pin_nid - 4; | |
3423 | } | |
3424 | ||
3425 | /* reverse-map from port to pin NID: see above */ | |
3426 | static int nvhdmi_port2pin(struct hda_codec *codec, int port) | |
3427 | { | |
3428 | return port + 4; | |
3429 | } | |
3430 | ||
3431 | static const struct drm_audio_component_audio_ops nvhdmi_audio_ops = { | |
3432 | .pin2port = nvhdmi_pin2port, | |
3433 | .pin_eld_notify = generic_acomp_pin_eld_notify, | |
3434 | .master_bind = generic_acomp_master_bind, | |
3435 | .master_unbind = generic_acomp_master_unbind, | |
3436 | }; | |
3437 | ||
611885bc AH |
3438 | static int patch_nvhdmi(struct hda_codec *codec) |
3439 | { | |
3440 | struct hdmi_spec *spec; | |
3441 | int err; | |
3442 | ||
5398e94f NM |
3443 | err = alloc_generic_hdmi(codec); |
3444 | if (err < 0) | |
3445 | return err; | |
3446 | codec->dp_mst = true; | |
3447 | ||
3448 | spec = codec->spec; | |
3449 | spec->dyn_pcm_assign = true; | |
3450 | ||
3451 | err = hdmi_parse_codec(codec); | |
3452 | if (err < 0) { | |
3453 | generic_spec_free(codec); | |
3454 | return err; | |
3455 | } | |
3456 | ||
3457 | generic_hdmi_init_per_pins(codec); | |
3458 | ||
3459 | spec->dyn_pin_out = true; | |
3460 | ||
3461 | spec->chmap.ops.chmap_cea_alloc_validate_get_type = | |
3462 | nvhdmi_chmap_cea_alloc_validate_get_type; | |
3463 | spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; | |
3464 | ||
3465 | codec->link_down_at_suspend = 1; | |
3466 | ||
3467 | generic_acomp_init(codec, &nvhdmi_audio_ops, nvhdmi_port2pin); | |
3468 | ||
3469 | return 0; | |
3470 | } | |
3471 | ||
3472 | static int patch_nvhdmi_legacy(struct hda_codec *codec) | |
3473 | { | |
3474 | struct hdmi_spec *spec; | |
3475 | int err; | |
3476 | ||
611885bc AH |
3477 | err = patch_generic_hdmi(codec); |
3478 | if (err) | |
3479 | return err; | |
3480 | ||
3481 | spec = codec->spec; | |
75fae117 | 3482 | spec->dyn_pin_out = true; |
611885bc | 3483 | |
67b90cb8 | 3484 | spec->chmap.ops.chmap_cea_alloc_validate_get_type = |
611885bc | 3485 | nvhdmi_chmap_cea_alloc_validate_get_type; |
67b90cb8 | 3486 | spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; |
611885bc | 3487 | |
94989e31 LW |
3488 | codec->link_down_at_suspend = 1; |
3489 | ||
611885bc AH |
3490 | return 0; |
3491 | } | |
3492 | ||
26e9a960 TR |
3493 | /* |
3494 | * The HDA codec on NVIDIA Tegra contains two scratch registers that are | |
3495 | * accessed using vendor-defined verbs. These registers can be used for | |
3496 | * interoperability between the HDA and HDMI drivers. | |
3497 | */ | |
3498 | ||
3499 | /* Audio Function Group node */ | |
3500 | #define NVIDIA_AFG_NID 0x01 | |
3501 | ||
3502 | /* | |
3503 | * The SCRATCH0 register is used to notify the HDMI codec of changes in audio | |
3504 | * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to | |
3505 | * be raised in the HDMI codec. The remainder of the bits is arbitrary. This | |
3506 | * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an | |
3507 | * additional bit (at position 30) to signal the validity of the format. | |
3508 | * | |
3509 | * | 31 | 30 | 29 16 | 15 0 | | |
3510 | * +---------+-------+--------+--------+ | |
3511 | * | TRIGGER | VALID | UNUSED | FORMAT | | |
3512 | * +-----------------------------------| | |
3513 | * | |
3514 | * Note that for the trigger bit to take effect it needs to change value | |
3515 | * (i.e. it needs to be toggled). | |
3516 | */ | |
3517 | #define NVIDIA_GET_SCRATCH0 0xfa6 | |
3518 | #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7 | |
3519 | #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8 | |
3520 | #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9 | |
3521 | #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa | |
3522 | #define NVIDIA_SCRATCH_TRIGGER (1 << 7) | |
3523 | #define NVIDIA_SCRATCH_VALID (1 << 6) | |
3524 | ||
3525 | #define NVIDIA_GET_SCRATCH1 0xfab | |
3526 | #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac | |
3527 | #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad | |
3528 | #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae | |
3529 | #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf | |
3530 | ||
3531 | /* | |
3532 | * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0, | |
3533 | * the format is invalidated so that the HDMI codec can be disabled. | |
3534 | */ | |
3535 | static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format) | |
3536 | { | |
3537 | unsigned int value; | |
3538 | ||
3539 | /* bits [31:30] contain the trigger and valid bits */ | |
3540 | value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0, | |
3541 | NVIDIA_GET_SCRATCH0, 0); | |
3542 | value = (value >> 24) & 0xff; | |
3543 | ||
3544 | /* bits [15:0] are used to store the HDA format */ | |
3545 | snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, | |
3546 | NVIDIA_SET_SCRATCH0_BYTE0, | |
3547 | (format >> 0) & 0xff); | |
3548 | snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, | |
3549 | NVIDIA_SET_SCRATCH0_BYTE1, | |
3550 | (format >> 8) & 0xff); | |
3551 | ||
3552 | /* bits [16:24] are unused */ | |
3553 | snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, | |
3554 | NVIDIA_SET_SCRATCH0_BYTE2, 0); | |
3555 | ||
3556 | /* | |
3557 | * Bit 30 signals that the data is valid and hence that HDMI audio can | |
3558 | * be enabled. | |
3559 | */ | |
3560 | if (format == 0) | |
3561 | value &= ~NVIDIA_SCRATCH_VALID; | |
3562 | else | |
3563 | value |= NVIDIA_SCRATCH_VALID; | |
3564 | ||
3565 | /* | |
3566 | * Whenever the trigger bit is toggled, an interrupt is raised in the | |
3567 | * HDMI codec. The HDMI driver will use that as trigger to update its | |
3568 | * configuration. | |
3569 | */ | |
3570 | value ^= NVIDIA_SCRATCH_TRIGGER; | |
3571 | ||
3572 | snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, | |
3573 | NVIDIA_SET_SCRATCH0_BYTE3, value); | |
3574 | } | |
3575 | ||
3576 | static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo, | |
3577 | struct hda_codec *codec, | |
3578 | unsigned int stream_tag, | |
3579 | unsigned int format, | |
3580 | struct snd_pcm_substream *substream) | |
3581 | { | |
3582 | int err; | |
3583 | ||
3584 | err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag, | |
3585 | format, substream); | |
3586 | if (err < 0) | |
3587 | return err; | |
3588 | ||
3589 | /* notify the HDMI codec of the format change */ | |
3590 | tegra_hdmi_set_format(codec, format); | |
3591 | ||
3592 | return 0; | |
3593 | } | |
3594 | ||
3595 | static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo, | |
3596 | struct hda_codec *codec, | |
3597 | struct snd_pcm_substream *substream) | |
3598 | { | |
3599 | /* invalidate the format in the HDMI codec */ | |
3600 | tegra_hdmi_set_format(codec, 0); | |
3601 | ||
3602 | return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream); | |
3603 | } | |
3604 | ||
3605 | static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type) | |
3606 | { | |
3607 | struct hdmi_spec *spec = codec->spec; | |
3608 | unsigned int i; | |
3609 | ||
3610 | for (i = 0; i < spec->num_pins; i++) { | |
3611 | struct hda_pcm *pcm = get_pcm_rec(spec, i); | |
3612 | ||
3613 | if (pcm->pcm_type == type) | |
3614 | return pcm; | |
3615 | } | |
3616 | ||
3617 | return NULL; | |
3618 | } | |
3619 | ||
3620 | static int tegra_hdmi_build_pcms(struct hda_codec *codec) | |
3621 | { | |
3622 | struct hda_pcm_stream *stream; | |
3623 | struct hda_pcm *pcm; | |
3624 | int err; | |
3625 | ||
3626 | err = generic_hdmi_build_pcms(codec); | |
3627 | if (err < 0) | |
3628 | return err; | |
3629 | ||
3630 | pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI); | |
3631 | if (!pcm) | |
3632 | return -ENODEV; | |
3633 | ||
3634 | /* | |
3635 | * Override ->prepare() and ->cleanup() operations to notify the HDMI | |
3636 | * codec about format changes. | |
3637 | */ | |
3638 | stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; | |
3639 | stream->ops.prepare = tegra_hdmi_pcm_prepare; | |
3640 | stream->ops.cleanup = tegra_hdmi_pcm_cleanup; | |
3641 | ||
3642 | return 0; | |
3643 | } | |
3644 | ||
3645 | static int patch_tegra_hdmi(struct hda_codec *codec) | |
3646 | { | |
3647 | int err; | |
3648 | ||
3649 | err = patch_generic_hdmi(codec); | |
3650 | if (err) | |
3651 | return err; | |
3652 | ||
3653 | codec->patch_ops.build_pcms = tegra_hdmi_build_pcms; | |
3654 | ||
3655 | return 0; | |
3656 | } | |
3657 | ||
84eb01be | 3658 | /* |
5a613584 | 3659 | * ATI/AMD-specific implementations |
84eb01be TI |
3660 | */ |
3661 | ||
5a613584 | 3662 | #define is_amdhdmi_rev3_or_later(codec) \ |
7639a06c TI |
3663 | ((codec)->core.vendor_id == 0x1002aa01 && \ |
3664 | ((codec)->core.revision_id & 0xff00) >= 0x0300) | |
5a613584 AH |
3665 | #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec) |
3666 | ||
3667 | /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */ | |
3668 | #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771 | |
3669 | #define ATI_VERB_SET_DOWNMIX_INFO 0x772 | |
3670 | #define ATI_VERB_SET_MULTICHANNEL_01 0x777 | |
3671 | #define ATI_VERB_SET_MULTICHANNEL_23 0x778 | |
3672 | #define ATI_VERB_SET_MULTICHANNEL_45 0x779 | |
3673 | #define ATI_VERB_SET_MULTICHANNEL_67 0x77a | |
461cf6b3 | 3674 | #define ATI_VERB_SET_HBR_CONTROL 0x77c |
5a613584 AH |
3675 | #define ATI_VERB_SET_MULTICHANNEL_1 0x785 |
3676 | #define ATI_VERB_SET_MULTICHANNEL_3 0x786 | |
3677 | #define ATI_VERB_SET_MULTICHANNEL_5 0x787 | |
3678 | #define ATI_VERB_SET_MULTICHANNEL_7 0x788 | |
3679 | #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789 | |
3680 | #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71 | |
3681 | #define ATI_VERB_GET_DOWNMIX_INFO 0xf72 | |
3682 | #define ATI_VERB_GET_MULTICHANNEL_01 0xf77 | |
3683 | #define ATI_VERB_GET_MULTICHANNEL_23 0xf78 | |
3684 | #define ATI_VERB_GET_MULTICHANNEL_45 0xf79 | |
3685 | #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a | |
461cf6b3 | 3686 | #define ATI_VERB_GET_HBR_CONTROL 0xf7c |
5a613584 AH |
3687 | #define ATI_VERB_GET_MULTICHANNEL_1 0xf85 |
3688 | #define ATI_VERB_GET_MULTICHANNEL_3 0xf86 | |
3689 | #define ATI_VERB_GET_MULTICHANNEL_5 0xf87 | |
3690 | #define ATI_VERB_GET_MULTICHANNEL_7 0xf88 | |
3691 | #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89 | |
3692 | ||
84d69e79 AH |
3693 | /* AMD specific HDA cvt verbs */ |
3694 | #define ATI_VERB_SET_RAMP_RATE 0x770 | |
3695 | #define ATI_VERB_GET_RAMP_RATE 0xf70 | |
3696 | ||
5a613584 AH |
3697 | #define ATI_OUT_ENABLE 0x1 |
3698 | ||
3699 | #define ATI_MULTICHANNEL_MODE_PAIRED 0 | |
3700 | #define ATI_MULTICHANNEL_MODE_SINGLE 1 | |
3701 | ||
461cf6b3 AH |
3702 | #define ATI_HBR_CAPABLE 0x01 |
3703 | #define ATI_HBR_ENABLE 0x10 | |
3704 | ||
89250f84 | 3705 | static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, |
9c32fea8 | 3706 | int dev_id, unsigned char *buf, int *eld_size) |
89250f84 | 3707 | { |
9c32fea8 | 3708 | WARN_ON(dev_id != 0); |
89250f84 AH |
3709 | /* call hda_eld.c ATI/AMD-specific function */ |
3710 | return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size, | |
3711 | is_amdhdmi_rev3_or_later(codec)); | |
3712 | } | |
3713 | ||
9c32fea8 NM |
3714 | static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, |
3715 | hda_nid_t pin_nid, int dev_id, int ca, | |
5a613584 AH |
3716 | int active_channels, int conn_type) |
3717 | { | |
9c32fea8 | 3718 | WARN_ON(dev_id != 0); |
5a613584 AH |
3719 | snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca); |
3720 | } | |
3721 | ||
3722 | static int atihdmi_paired_swap_fc_lfe(int pos) | |
3723 | { | |
3724 | /* | |
3725 | * ATI/AMD have automatic FC/LFE swap built-in | |
3726 | * when in pairwise mapping mode. | |
3727 | */ | |
3728 | ||
3729 | switch (pos) { | |
3730 | /* see channel_allocations[].speakers[] */ | |
3731 | case 2: return 3; | |
3732 | case 3: return 2; | |
3733 | default: break; | |
3734 | } | |
3735 | ||
3736 | return pos; | |
3737 | } | |
3738 | ||
828cb4ed SP |
3739 | static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap, |
3740 | int ca, int chs, unsigned char *map) | |
5a613584 | 3741 | { |
f302240d | 3742 | struct hdac_cea_channel_speaker_allocation *cap; |
5a613584 AH |
3743 | int i, j; |
3744 | ||
3745 | /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */ | |
3746 | ||
bb63f726 | 3747 | cap = snd_hdac_get_ch_alloc_from_ca(ca); |
5a613584 | 3748 | for (i = 0; i < chs; ++i) { |
bb63f726 | 3749 | int mask = snd_hdac_chmap_to_spk_mask(map[i]); |
5a613584 AH |
3750 | bool ok = false; |
3751 | bool companion_ok = false; | |
3752 | ||
3753 | if (!mask) | |
3754 | continue; | |
3755 | ||
3756 | for (j = 0 + i % 2; j < 8; j += 2) { | |
3757 | int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j); | |
3758 | if (cap->speakers[chan_idx] == mask) { | |
3759 | /* channel is in a supported position */ | |
3760 | ok = true; | |
3761 | ||
3762 | if (i % 2 == 0 && i + 1 < chs) { | |
3763 | /* even channel, check the odd companion */ | |
3764 | int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1); | |
bb63f726 | 3765 | int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]); |
5a613584 AH |
3766 | int comp_mask_act = cap->speakers[comp_chan_idx]; |
3767 | ||
3768 | if (comp_mask_req == comp_mask_act) | |
3769 | companion_ok = true; | |
3770 | else | |
3771 | return -EINVAL; | |
3772 | } | |
3773 | break; | |
3774 | } | |
3775 | } | |
3776 | ||
3777 | if (!ok) | |
3778 | return -EINVAL; | |
3779 | ||
3780 | if (companion_ok) | |
3781 | i++; /* companion channel already checked */ | |
3782 | } | |
3783 | ||
3784 | return 0; | |
3785 | } | |
3786 | ||
739ffee9 SP |
3787 | static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac, |
3788 | hda_nid_t pin_nid, int hdmi_slot, int stream_channel) | |
5a613584 | 3789 | { |
739ffee9 | 3790 | struct hda_codec *codec = container_of(hdac, struct hda_codec, core); |
5a613584 AH |
3791 | int verb; |
3792 | int ati_channel_setup = 0; | |
3793 | ||
3794 | if (hdmi_slot > 7) | |
3795 | return -EINVAL; | |
3796 | ||
3797 | if (!has_amd_full_remap_support(codec)) { | |
3798 | hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot); | |
3799 | ||
3800 | /* In case this is an odd slot but without stream channel, do not | |
3801 | * disable the slot since the corresponding even slot could have a | |
3802 | * channel. In case neither have a channel, the slot pair will be | |
3803 | * disabled when this function is called for the even slot. */ | |
3804 | if (hdmi_slot % 2 != 0 && stream_channel == 0xf) | |
3805 | return 0; | |
3806 | ||
3807 | hdmi_slot -= hdmi_slot % 2; | |
3808 | ||
3809 | if (stream_channel != 0xf) | |
3810 | stream_channel -= stream_channel % 2; | |
3811 | } | |
3812 | ||
3813 | verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e; | |
3814 | ||
3815 | /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */ | |
3816 | ||
3817 | if (stream_channel != 0xf) | |
3818 | ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE; | |
3819 | ||
3820 | return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup); | |
3821 | } | |
3822 | ||
739ffee9 SP |
3823 | static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac, |
3824 | hda_nid_t pin_nid, int asp_slot) | |
5a613584 | 3825 | { |
739ffee9 | 3826 | struct hda_codec *codec = container_of(hdac, struct hda_codec, core); |
5a613584 AH |
3827 | bool was_odd = false; |
3828 | int ati_asp_slot = asp_slot; | |
3829 | int verb; | |
3830 | int ati_channel_setup; | |
3831 | ||
3832 | if (asp_slot > 7) | |
3833 | return -EINVAL; | |
3834 | ||
3835 | if (!has_amd_full_remap_support(codec)) { | |
3836 | ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot); | |
3837 | if (ati_asp_slot % 2 != 0) { | |
3838 | ati_asp_slot -= 1; | |
3839 | was_odd = true; | |
3840 | } | |
3841 | } | |
3842 | ||
3843 | verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e; | |
3844 | ||
3845 | ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0); | |
3846 | ||
3847 | if (!(ati_channel_setup & ATI_OUT_ENABLE)) | |
3848 | return 0xf; | |
3849 | ||
3850 | return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd; | |
3851 | } | |
84eb01be | 3852 | |
67b90cb8 SP |
3853 | static int atihdmi_paired_chmap_cea_alloc_validate_get_type( |
3854 | struct hdac_chmap *chmap, | |
f302240d | 3855 | struct hdac_cea_channel_speaker_allocation *cap, |
67b90cb8 | 3856 | int channels) |
5a613584 AH |
3857 | { |
3858 | int c; | |
3859 | ||
3860 | /* | |
3861 | * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so | |
3862 | * we need to take that into account (a single channel may take 2 | |
3863 | * channel slots if we need to carry a silent channel next to it). | |
3864 | * On Rev3+ AMD codecs this function is not used. | |
3865 | */ | |
3866 | int chanpairs = 0; | |
3867 | ||
3868 | /* We only produce even-numbered channel count TLVs */ | |
3869 | if ((channels % 2) != 0) | |
3870 | return -1; | |
3871 | ||
3872 | for (c = 0; c < 7; c += 2) { | |
3873 | if (cap->speakers[c] || cap->speakers[c+1]) | |
3874 | chanpairs++; | |
3875 | } | |
3876 | ||
3877 | if (chanpairs * 2 != channels) | |
3878 | return -1; | |
3879 | ||
3880 | return SNDRV_CTL_TLVT_CHMAP_PAIRED; | |
3881 | } | |
3882 | ||
828cb4ed | 3883 | static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap, |
f302240d SP |
3884 | struct hdac_cea_channel_speaker_allocation *cap, |
3885 | unsigned int *chmap, int channels) | |
5a613584 AH |
3886 | { |
3887 | /* produce paired maps for pre-rev3 ATI/AMD codecs */ | |
3888 | int count = 0; | |
3889 | int c; | |
3890 | ||
3891 | for (c = 7; c >= 0; c--) { | |
3892 | int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c); | |
3893 | int spk = cap->speakers[chan]; | |
3894 | if (!spk) { | |
3895 | /* add N/A channel if the companion channel is occupied */ | |
3896 | if (cap->speakers[chan + (chan % 2 ? -1 : 1)]) | |
3897 | chmap[count++] = SNDRV_CHMAP_NA; | |
3898 | ||
3899 | continue; | |
3900 | } | |
3901 | ||
bb63f726 | 3902 | chmap[count++] = snd_hdac_spk_to_chmap(spk); |
5a613584 AH |
3903 | } |
3904 | ||
3905 | WARN_ON(count != channels); | |
3906 | } | |
3907 | ||
461cf6b3 | 3908 | static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, |
9c32fea8 | 3909 | int dev_id, bool hbr) |
461cf6b3 AH |
3910 | { |
3911 | int hbr_ctl, hbr_ctl_new; | |
3912 | ||
9c32fea8 NM |
3913 | WARN_ON(dev_id != 0); |
3914 | ||
461cf6b3 | 3915 | hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0); |
13122e6e | 3916 | if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) { |
461cf6b3 AH |
3917 | if (hbr) |
3918 | hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE; | |
3919 | else | |
3920 | hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE; | |
3921 | ||
4e76a883 TI |
3922 | codec_dbg(codec, |
3923 | "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n", | |
461cf6b3 AH |
3924 | pin_nid, |
3925 | hbr_ctl == hbr_ctl_new ? "" : "new-", | |
3926 | hbr_ctl_new); | |
3927 | ||
3928 | if (hbr_ctl != hbr_ctl_new) | |
3929 | snd_hda_codec_write(codec, pin_nid, 0, | |
3930 | ATI_VERB_SET_HBR_CONTROL, | |
3931 | hbr_ctl_new); | |
3932 | ||
3933 | } else if (hbr) | |
3934 | return -EINVAL; | |
3935 | ||
3936 | return 0; | |
3937 | } | |
3938 | ||
84d69e79 | 3939 | static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, |
9c32fea8 NM |
3940 | hda_nid_t pin_nid, int dev_id, |
3941 | u32 stream_tag, int format) | |
84d69e79 | 3942 | { |
84d69e79 AH |
3943 | if (is_amdhdmi_rev3_or_later(codec)) { |
3944 | int ramp_rate = 180; /* default as per AMD spec */ | |
3945 | /* disable ramp-up/down for non-pcm as per AMD spec */ | |
3946 | if (format & AC_FMT_TYPE_NON_PCM) | |
3947 | ramp_rate = 0; | |
3948 | ||
3949 | snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate); | |
3950 | } | |
3951 | ||
9c32fea8 NM |
3952 | return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id, |
3953 | stream_tag, format); | |
84d69e79 AH |
3954 | } |
3955 | ||
3956 | ||
5a613584 | 3957 | static int atihdmi_init(struct hda_codec *codec) |
84eb01be TI |
3958 | { |
3959 | struct hdmi_spec *spec = codec->spec; | |
5a613584 | 3960 | int pin_idx, err; |
84eb01be | 3961 | |
5a613584 AH |
3962 | err = generic_hdmi_init(codec); |
3963 | ||
3964 | if (err) | |
84eb01be | 3965 | return err; |
5a613584 AH |
3966 | |
3967 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { | |
3968 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); | |
3969 | ||
3970 | /* make sure downmix information in infoframe is zero */ | |
3971 | snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0); | |
3972 | ||
3973 | /* enable channel-wise remap mode if supported */ | |
3974 | if (has_amd_full_remap_support(codec)) | |
3975 | snd_hda_codec_write(codec, per_pin->pin_nid, 0, | |
3976 | ATI_VERB_SET_MULTICHANNEL_MODE, | |
3977 | ATI_MULTICHANNEL_MODE_SINGLE); | |
84eb01be | 3978 | } |
8218df93 | 3979 | codec->auto_runtime_pm = 1; |
5a613584 | 3980 | |
84eb01be TI |
3981 | return 0; |
3982 | } | |
3983 | ||
ade49db3 TI |
3984 | /* map from pin NID to port; port is 0-based */ |
3985 | /* for AMD: assume widget NID starting from 3, with step 2 (3, 5, 7, ...) */ | |
3986 | static int atihdmi_pin2port(void *audio_ptr, int pin_nid) | |
3987 | { | |
3988 | return pin_nid / 2 - 1; | |
3989 | } | |
3990 | ||
3991 | /* reverse-map from port to pin NID: see above */ | |
3992 | static int atihdmi_port2pin(struct hda_codec *codec, int port) | |
3993 | { | |
3994 | return port * 2 + 3; | |
3995 | } | |
3996 | ||
3997 | static const struct drm_audio_component_audio_ops atihdmi_audio_ops = { | |
3998 | .pin2port = atihdmi_pin2port, | |
3999 | .pin_eld_notify = generic_acomp_pin_eld_notify, | |
4000 | .master_bind = generic_acomp_master_bind, | |
4001 | .master_unbind = generic_acomp_master_unbind, | |
4002 | }; | |
4003 | ||
84eb01be TI |
4004 | static int patch_atihdmi(struct hda_codec *codec) |
4005 | { | |
4006 | struct hdmi_spec *spec; | |
5a613584 AH |
4007 | struct hdmi_spec_per_cvt *per_cvt; |
4008 | int err, cvt_idx; | |
4009 | ||
4010 | err = patch_generic_hdmi(codec); | |
4011 | ||
4012 | if (err) | |
d0b1252d | 4013 | return err; |
5a613584 AH |
4014 | |
4015 | codec->patch_ops.init = atihdmi_init; | |
4016 | ||
d0b1252d | 4017 | spec = codec->spec; |
5a613584 | 4018 | |
89250f84 | 4019 | spec->ops.pin_get_eld = atihdmi_pin_get_eld; |
5a613584 | 4020 | spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe; |
461cf6b3 | 4021 | spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup; |
84d69e79 | 4022 | spec->ops.setup_stream = atihdmi_setup_stream; |
5a613584 | 4023 | |
39669225 TI |
4024 | spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel; |
4025 | spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel; | |
4026 | ||
5a613584 AH |
4027 | if (!has_amd_full_remap_support(codec)) { |
4028 | /* override to ATI/AMD-specific versions with pairwise mapping */ | |
67b90cb8 | 4029 | spec->chmap.ops.chmap_cea_alloc_validate_get_type = |
5a613584 | 4030 | atihdmi_paired_chmap_cea_alloc_validate_get_type; |
67b90cb8 SP |
4031 | spec->chmap.ops.cea_alloc_to_tlv_chmap = |
4032 | atihdmi_paired_cea_alloc_to_tlv_chmap; | |
4033 | spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate; | |
5a613584 AH |
4034 | } |
4035 | ||
4036 | /* ATI/AMD converters do not advertise all of their capabilities */ | |
4037 | for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { | |
4038 | per_cvt = get_cvt(spec, cvt_idx); | |
4039 | per_cvt->channels_max = max(per_cvt->channels_max, 8u); | |
4040 | per_cvt->rates |= SUPPORTED_RATES; | |
4041 | per_cvt->formats |= SUPPORTED_FORMATS; | |
4042 | per_cvt->maxbps = max(per_cvt->maxbps, 24u); | |
4043 | } | |
4044 | ||
67b90cb8 | 4045 | spec->chmap.channels_max = max(spec->chmap.channels_max, 8u); |
5a613584 | 4046 | |
57cb54e5 TI |
4047 | /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing |
4048 | * the link-down as is. Tell the core to allow it. | |
4049 | */ | |
4050 | codec->link_down_at_suspend = 1; | |
4051 | ||
ade49db3 TI |
4052 | generic_acomp_init(codec, &atihdmi_audio_ops, atihdmi_port2pin); |
4053 | ||
84eb01be TI |
4054 | return 0; |
4055 | } | |
4056 | ||
3de5ff88 AL |
4057 | /* VIA HDMI Implementation */ |
4058 | #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */ | |
4059 | #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */ | |
4060 | ||
3de5ff88 AL |
4061 | static int patch_via_hdmi(struct hda_codec *codec) |
4062 | { | |
250e41ac | 4063 | return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID); |
3de5ff88 | 4064 | } |
84eb01be TI |
4065 | |
4066 | /* | |
4067 | * patch entries | |
4068 | */ | |
b9a94a9c TI |
4069 | static const struct hda_device_id snd_hda_id_hdmi[] = { |
4070 | HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi), | |
4071 | HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi), | |
4072 | HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi), | |
4073 | HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi), | |
4074 | HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi), | |
4075 | HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi), | |
4076 | HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi), | |
74ec1181 | 4077 | HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch), |
b9a94a9c TI |
4078 | HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), |
4079 | HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), | |
74ec1181 | 4080 | HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x), |
b9a94a9c TI |
4081 | HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), |
4082 | HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), | |
4083 | HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x), | |
5398e94f NM |
4084 | HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi_legacy), |
4085 | HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi_legacy), | |
4086 | HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi_legacy), | |
4087 | HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi_legacy), | |
4088 | HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi_legacy), | |
4089 | HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi_legacy), | |
4090 | HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi_legacy), | |
4091 | HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi_legacy), | |
4092 | HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi_legacy), | |
4093 | HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi_legacy), | |
4094 | HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi_legacy), | |
4095 | HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi_legacy), | |
4096 | HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi_legacy), | |
c8900a0f | 4097 | /* 17 is known to be absent */ |
5398e94f NM |
4098 | HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi_legacy), |
4099 | HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi_legacy), | |
4100 | HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi_legacy), | |
4101 | HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi_legacy), | |
4102 | HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi_legacy), | |
b9a94a9c TI |
4103 | HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi), |
4104 | HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi), | |
4105 | HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi), | |
4106 | HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi), | |
917bb90c TR |
4107 | HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi), |
4108 | HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi), | |
4109 | HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi), | |
4110 | HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi), | |
b9a94a9c TI |
4111 | HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi), |
4112 | HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi), | |
4113 | HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi), | |
4114 | HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi), | |
4115 | HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi), | |
74ec1181 DD |
4116 | HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi), |
4117 | HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi), | |
b9a94a9c | 4118 | HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi), |
74ec1181 | 4119 | HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi), |
b9a94a9c | 4120 | HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi), |
74ec1181 DD |
4121 | HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi), |
4122 | HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi), | |
b9a94a9c TI |
4123 | HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch), |
4124 | HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi), | |
4125 | HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi), | |
4126 | HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi), | |
74ec1181 DD |
4127 | HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi), |
4128 | HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi), | |
4129 | HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi), | |
4130 | HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi), | |
4131 | HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi), | |
b9a94a9c | 4132 | HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi), |
74ec1181 | 4133 | HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi), |
af677166 | 4134 | HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi), |
74ec1181 | 4135 | HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi), |
2d369c74 | 4136 | HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi), |
3ec622f4 | 4137 | HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi), |
74ec1181 DD |
4138 | HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi), |
4139 | HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi), | |
4140 | HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi), | |
4141 | HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi), | |
4142 | HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi), | |
4143 | HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi), | |
4144 | HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi), | |
4145 | HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi), | |
4146 | HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi), | |
4147 | HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi), | |
b9a94a9c | 4148 | HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch), |
74ec1181 | 4149 | HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch), |
b9a94a9c TI |
4150 | HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi), |
4151 | HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi), | |
4152 | HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi), | |
4153 | HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi), | |
7ff652ff | 4154 | HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi), |
b0d8bc50 | 4155 | HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi), |
b9a94a9c TI |
4156 | HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi), |
4157 | HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi), | |
4158 | HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi), | |
7ff652ff | 4159 | HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi), |
e85015a3 TI |
4160 | HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi), |
4161 | HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi), | |
a686632f TI |
4162 | HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi), |
4163 | HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi), | |
4164 | HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi), | |
4165 | HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi), | |
4166 | HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi), | |
2b4584d0 | 4167 | HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi), |
a87a4d23 | 4168 | HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi), |
b0d8bc50 | 4169 | HDA_CODEC_ENTRY(0x8086280f, "Icelake HDMI", patch_i915_icl_hdmi), |
9a11ba73 | 4170 | HDA_CODEC_ENTRY(0x80862812, "Tigerlake HDMI", patch_i915_tgl_hdmi), |
78be2228 | 4171 | HDA_CODEC_ENTRY(0x8086281a, "Jasperlake HDMI", patch_i915_icl_hdmi), |
b9a94a9c | 4172 | HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi), |
a686632f TI |
4173 | HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi), |
4174 | HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi), | |
b9a94a9c | 4175 | HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi), |
d8a766a1 | 4176 | /* special ID for generic HDMI */ |
b9a94a9c | 4177 | HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi), |
84eb01be TI |
4178 | {} /* terminator */ |
4179 | }; | |
b9a94a9c | 4180 | MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi); |
84eb01be TI |
4181 | |
4182 | MODULE_LICENSE("GPL"); | |
4183 | MODULE_DESCRIPTION("HDMI HD-audio codec"); | |
4184 | MODULE_ALIAS("snd-hda-codec-intelhdmi"); | |
4185 | MODULE_ALIAS("snd-hda-codec-nvhdmi"); | |
4186 | MODULE_ALIAS("snd-hda-codec-atihdmi"); | |
4187 | ||
d8a766a1 | 4188 | static struct hda_codec_driver hdmi_driver = { |
b9a94a9c | 4189 | .id = snd_hda_id_hdmi, |
84eb01be TI |
4190 | }; |
4191 | ||
d8a766a1 | 4192 | module_hda_codec_driver(hdmi_driver); |