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ALSA: hda - hdmi: Add ELD emulation for ATI/AMD codecs
[people/ms/linux.git] / sound / pci / hda / patch_hdmi.c
CommitLineData
079d88cc
WF		 1/*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
84eb01be
TI		 6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
5a613584 9 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
079d88cc
WF		 10 *
11 * Authors:
12 * Wu Fengguang <wfg@linux.intel.com>
13 *
14 * Maintained by:
15 * Wu Fengguang <wfg@linux.intel.com>
16 *
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the Free
19 * Software Foundation; either version 2 of the License, or (at your option)
20 * any later version.
21 *
22 * This program is distributed in the hope that it will be useful, but
23 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
24 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 * for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software Foundation,
29 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
84eb01be
TI		 32#include <linux/init.h>
33#include <linux/delay.h>
34#include <linux/slab.h>
65a77217 35#include <linux/module.h>
84eb01be 36#include <sound/core.h>
07acecc1 37#include <sound/jack.h>
433968da 38#include <sound/asoundef.h>
d45e6889 39#include <sound/tlv.h>
84eb01be
TI		 40#include "hda_codec.h"
41#include "hda_local.h"
1835a0f9 42#include "hda_jack.h"
84eb01be 43
0ebaa24c
TI		 44static bool static_hdmi_pcm;
45module_param(static_hdmi_pcm, bool, 0644);
46MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
47
fb87fa3a
ML		 48#define is_haswell(codec) ((codec)->vendor_id == 0x80862807)
49
384a48d7
SW		 50struct hdmi_spec_per_cvt {
51 hda_nid_t cvt_nid;
52 int assigned;
53 unsigned int channels_min;
54 unsigned int channels_max;
55 u32 rates;
56 u64 formats;
57 unsigned int maxbps;
58};
079d88cc 59
4eea3091
TI		 60/* max. connections to a widget */
61#define HDA_MAX_CONNECTIONS 32
62
384a48d7
SW		 63struct hdmi_spec_per_pin {
64 hda_nid_t pin_nid;
65 int num_mux_nids;
66 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
1df5a06a 67 hda_nid_t cvt_nid;
744626da
WF		 68
69 struct hda_codec *codec;
384a48d7 70 struct hdmi_eld sink_eld;
a4e9a38b 71 struct mutex lock;
744626da 72 struct delayed_work work;
92c69e79 73 struct snd_kcontrol *eld_ctl;
c6e8453e 74 int repoll_count;
b054087d
TI		 75 bool setup; /* the stream has been set up by prepare callback */
76 int channels; /* current number of channels */
1a6003b5 77 bool non_pcm;
d45e6889
TI		 78 bool chmap_set; /* channel-map override by ALSA API? */
79 unsigned char chmap[8]; /* ALSA API channel-map */
bce0d2a8 80 char pcm_name[8]; /* filled in build_pcm callbacks */
a4e9a38b
TI		 81#ifdef CONFIG_PROC_FS
82 struct snd_info_entry *proc_entry;
83#endif
384a48d7 84};
079d88cc 85
307229d2
AH		 86struct cea_channel_speaker_allocation;
87
88/* operations used by generic code that can be overridden by patches */
89struct hdmi_ops {
90 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
91 unsigned char *buf, int *eld_size);
92
93 /* get and set channel assigned to each HDMI ASP (audio sample packet) slot */
94 int (*pin_get_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
95 int asp_slot);
96 int (*pin_set_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
97 int asp_slot, int channel);
98
99 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
100 int ca, int active_channels, int conn_type);
101
102 /* enable/disable HBR (HD passthrough) */
103 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
104
105 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
106 hda_nid_t pin_nid, u32 stream_tag, int format);
107
108 /* Helpers for producing the channel map TLVs. These can be overridden
109 * for devices that have non-standard mapping requirements. */
110 int (*chmap_cea_alloc_validate_get_type)(struct cea_channel_speaker_allocation *cap,
111 int channels);
112 void (*cea_alloc_to_tlv_chmap)(struct cea_channel_speaker_allocation *cap,
113 unsigned int *chmap, int channels);
114
115 /* check that the user-given chmap is supported */
116 int (*chmap_validate)(int ca, int channels, unsigned char *chmap);
117};
118
384a48d7
SW		 119struct hdmi_spec {
120 int num_cvts;
bce0d2a8
TI		 121 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
122 hda_nid_t cvt_nids[4]; /* only for haswell fix */
079d88cc 123
384a48d7 124 int num_pins;
bce0d2a8
TI		 125 struct snd_array pins; /* struct hdmi_spec_per_pin */
126 struct snd_array pcm_rec; /* struct hda_pcm */
d45e6889 127 unsigned int channels_max; /* max over all cvts */
079d88cc 128
4bd038f9 129 struct hdmi_eld temp_eld;
307229d2 130 struct hdmi_ops ops;
079d88cc 131 /*
5a613584 132 * Non-generic VIA/NVIDIA specific
079d88cc
WF		 133 */
134 struct hda_multi_out multiout;
d0b1252d 135 struct hda_pcm_stream pcm_playback;
079d88cc
WF		 136};
137
138
139struct hdmi_audio_infoframe {
140 u8 type; /* 0x84 */
141 u8 ver; /* 0x01 */
142 u8 len; /* 0x0a */
143
53d7d69d
WF		 144 u8 checksum;
145
079d88cc
WF		 146 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
147 u8 SS01_SF24;
148 u8 CXT04;
149 u8 CA;
150 u8 LFEPBL01_LSV36_DM_INH7;
53d7d69d
WF		 151};
152
153struct dp_audio_infoframe {
154 u8 type; /* 0x84 */
155 u8 len; /* 0x1b */
156 u8 ver; /* 0x11 << 2 */
157
158 u8 CC02_CT47; /* match with HDMI infoframe from this on */
159 u8 SS01_SF24;
160 u8 CXT04;
161 u8 CA;
162 u8 LFEPBL01_LSV36_DM_INH7;
079d88cc
WF		 163};
164
2b203dbb
TI		 165union audio_infoframe {
166 struct hdmi_audio_infoframe hdmi;
167 struct dp_audio_infoframe dp;
168 u8 bytes[0];
169};
170
079d88cc
WF		 171/*
172 * CEA speaker placement:
173 *
174 * FLH FCH FRH
175 * FLW FL FLC FC FRC FR FRW
176 *
177 * LFE
178 * TC
179 *
180 * RL RLC RC RRC RR
181 *
182 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
183 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
184 */
185enum cea_speaker_placement {
186 FL = (1 << 0), /* Front Left */
187 FC = (1 << 1), /* Front Center */
188 FR = (1 << 2), /* Front Right */
189 FLC = (1 << 3), /* Front Left Center */
190 FRC = (1 << 4), /* Front Right Center */
191 RL = (1 << 5), /* Rear Left */
192 RC = (1 << 6), /* Rear Center */
193 RR = (1 << 7), /* Rear Right */
194 RLC = (1 << 8), /* Rear Left Center */
195 RRC = (1 << 9), /* Rear Right Center */
196 LFE = (1 << 10), /* Low Frequency Effect */
197 FLW = (1 << 11), /* Front Left Wide */
198 FRW = (1 << 12), /* Front Right Wide */
199 FLH = (1 << 13), /* Front Left High */
200 FCH = (1 << 14), /* Front Center High */
201 FRH = (1 << 15), /* Front Right High */
202 TC = (1 << 16), /* Top Center */
203};
204
205/*
206 * ELD SA bits in the CEA Speaker Allocation data block
207 */
208static int eld_speaker_allocation_bits[] = {
209 [0] = FL | FR,
210 [1] = LFE,
211 [2] = FC,
212 [3] = RL | RR,
213 [4] = RC,
214 [5] = FLC | FRC,
215 [6] = RLC | RRC,
216 /* the following are not defined in ELD yet */
217 [7] = FLW | FRW,
218 [8] = FLH | FRH,
219 [9] = TC,
220 [10] = FCH,
221};
222
223struct cea_channel_speaker_allocation {
224 int ca_index;
225 int speakers[8];
226
227 /* derived values, just for convenience */
228 int channels;
229 int spk_mask;
230};
231
232/*
233 * ALSA sequence is:
234 *
235 * surround40 surround41 surround50 surround51 surround71
236 * ch0 front left = = = =
237 * ch1 front right = = = =
238 * ch2 rear left = = = =
239 * ch3 rear right = = = =
240 * ch4 LFE center center center
241 * ch5 LFE LFE
242 * ch6 side left
243 * ch7 side right
244 *
245 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
246 */
247static int hdmi_channel_mapping[0x32][8] = {
248 /* stereo */
249 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
250 /* 2.1 */
251 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
252 /* Dolby Surround */
253 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
254 /* surround40 */
255 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
256 /* 4ch */
257 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
258 /* surround41 */
9396d317 259 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
079d88cc
WF		 260 /* surround50 */
261 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
262 /* surround51 */
263 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
264 /* 7.1 */
265 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
266};
267
268/*
269 * This is an ordered list!
270 *
271 * The preceding ones have better chances to be selected by
53d7d69d 272 * hdmi_channel_allocation().
079d88cc
WF		 273 */
274static struct cea_channel_speaker_allocation channel_allocations[] = {
275/* channel: 7 6 5 4 3 2 1 0 */
276{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
277 /* 2.1 */
278{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
279 /* Dolby Surround */
280{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
281 /* surround40 */
282{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
283 /* surround41 */
284{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
285 /* surround50 */
286{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
287 /* surround51 */
288{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
289 /* 6.1 */
290{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
291 /* surround71 */
292{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
293
294{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
295{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
296{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
297{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
298{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
299{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
300{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
301{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
302{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
303{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
304{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
305{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
306{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
307{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
308{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
309{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
310{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
311{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
312{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
313{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
314{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
315{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
316{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
317{ .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
318{ .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
319{ .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
320{ .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
321{ .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
322{ .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
323{ .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
324{ .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
325{ .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
326{ .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
327{ .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
328{ .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
329{ .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
330{ .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
331{ .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
332{ .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
333{ .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
334{ .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
335};
336
337
338/*
339 * HDMI routines
340 */
341
bce0d2a8
TI		 342#define get_pin(spec, idx) \
343 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
344#define get_cvt(spec, idx) \
345 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
346#define get_pcm_rec(spec, idx) \
347 ((struct hda_pcm *)snd_array_elem(&spec->pcm_rec, idx))
348
384a48d7 349static int pin_nid_to_pin_index(struct hdmi_spec *spec, hda_nid_t pin_nid)
079d88cc 350{
384a48d7 351 int pin_idx;
079d88cc 352
384a48d7 353 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
bce0d2a8 354 if (get_pin(spec, pin_idx)->pin_nid == pin_nid)
384a48d7 355 return pin_idx;
079d88cc 356
384a48d7
SW		 357 snd_printk(KERN_WARNING "HDMI: pin nid %d not registered\n", pin_nid);
358 return -EINVAL;
359}
360
361static int hinfo_to_pin_index(struct hdmi_spec *spec,
362 struct hda_pcm_stream *hinfo)
363{
364 int pin_idx;
365
366 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
bce0d2a8 367 if (get_pcm_rec(spec, pin_idx)->stream == hinfo)
384a48d7
SW		 368 return pin_idx;
369
370 snd_printk(KERN_WARNING "HDMI: hinfo %p not registered\n", hinfo);
371 return -EINVAL;
372}
373
374static int cvt_nid_to_cvt_index(struct hdmi_spec *spec, hda_nid_t cvt_nid)
375{
376 int cvt_idx;
377
378 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
bce0d2a8 379 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
384a48d7
SW		 380 return cvt_idx;
381
382 snd_printk(KERN_WARNING "HDMI: cvt nid %d not registered\n", cvt_nid);
079d88cc
WF		 383 return -EINVAL;
384}
385
14bc52b8
PLB		 386static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
387 struct snd_ctl_elem_info *uinfo)
388{
389 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9 390 struct hdmi_spec *spec = codec->spec;
a4e9a38b 391 struct hdmi_spec_per_pin *per_pin;
68e03de9 392 struct hdmi_eld *eld;
14bc52b8
PLB		 393 int pin_idx;
394
14bc52b8
PLB		 395 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
396
397 pin_idx = kcontrol->private_value;
a4e9a38b
TI		 398 per_pin = get_pin(spec, pin_idx);
399 eld = &per_pin->sink_eld;
68e03de9 400
a4e9a38b 401 mutex_lock(&per_pin->lock);
68e03de9 402 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
a4e9a38b 403 mutex_unlock(&per_pin->lock);
14bc52b8
PLB		 404
405 return 0;
406}
407
408static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
409 struct snd_ctl_elem_value *ucontrol)
410{
411 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9 412 struct hdmi_spec *spec = codec->spec;
a4e9a38b 413 struct hdmi_spec_per_pin *per_pin;
68e03de9 414 struct hdmi_eld *eld;
14bc52b8
PLB		 415 int pin_idx;
416
14bc52b8 417 pin_idx = kcontrol->private_value;
a4e9a38b
TI		 418 per_pin = get_pin(spec, pin_idx);
419 eld = &per_pin->sink_eld;
68e03de9 420
a4e9a38b 421 mutex_lock(&per_pin->lock);
68e03de9 422 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data)) {
a4e9a38b 423 mutex_unlock(&per_pin->lock);
68e03de9
DH		 424 snd_BUG();
425 return -EINVAL;
426 }
427
428 memset(ucontrol->value.bytes.data, 0,
429 ARRAY_SIZE(ucontrol->value.bytes.data));
430 if (eld->eld_valid)
431 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
432 eld->eld_size);
a4e9a38b 433 mutex_unlock(&per_pin->lock);
14bc52b8
PLB		 434
435 return 0;
436}
437
438static struct snd_kcontrol_new eld_bytes_ctl = {
439 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
440 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
441 .name = "ELD",
442 .info = hdmi_eld_ctl_info,
443 .get = hdmi_eld_ctl_get,
444};
445
446static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
447 int device)
448{
449 struct snd_kcontrol *kctl;
450 struct hdmi_spec *spec = codec->spec;
451 int err;
452
453 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
454 if (!kctl)
455 return -ENOMEM;
456 kctl->private_value = pin_idx;
457 kctl->id.device = device;
458
bce0d2a8 459 err = snd_hda_ctl_add(codec, get_pin(spec, pin_idx)->pin_nid, kctl);
14bc52b8
PLB		 460 if (err < 0)
461 return err;
462
bce0d2a8 463 get_pin(spec, pin_idx)->eld_ctl = kctl;
14bc52b8
PLB		 464 return 0;
465}
466
079d88cc
WF		 467#ifdef BE_PARANOID
468static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
469 int *packet_index, int *byte_index)
470{
471 int val;
472
473 val = snd_hda_codec_read(codec, pin_nid, 0,
474 AC_VERB_GET_HDMI_DIP_INDEX, 0);
475
476 *packet_index = val >> 5;
477 *byte_index = val & 0x1f;
478}
479#endif
480
481static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
482 int packet_index, int byte_index)
483{
484 int val;
485
486 val = (packet_index << 5) | (byte_index & 0x1f);
487
488 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
489}
490
491static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
492 unsigned char val)
493{
494 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
495}
496
384a48d7 497static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
079d88cc
WF		 498{
499 /* Unmute */
500 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
501 snd_hda_codec_write(codec, pin_nid, 0,
502 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
6169b673
TI		 503 /* Enable pin out: some machines with GM965 gets broken output when
504 * the pin is disabled or changed while using with HDMI
505 */
079d88cc 506 snd_hda_codec_write(codec, pin_nid, 0,
6169b673 507 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
079d88cc
WF		 508}
509
384a48d7 510static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc 511{
384a48d7 512 return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
079d88cc
WF		 513 AC_VERB_GET_CVT_CHAN_COUNT, 0);
514}
515
516static void hdmi_set_channel_count(struct hda_codec *codec,
384a48d7 517 hda_nid_t cvt_nid, int chs)
079d88cc 518{
384a48d7
SW		 519 if (chs != hdmi_get_channel_count(codec, cvt_nid))
520 snd_hda_codec_write(codec, cvt_nid, 0,
079d88cc
WF		 521 AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
522}
523
a4e9a38b
TI		 524/*
525 * ELD proc files
526 */
527
528#ifdef CONFIG_PROC_FS
529static void print_eld_info(struct snd_info_entry *entry,
530 struct snd_info_buffer *buffer)
531{
532 struct hdmi_spec_per_pin *per_pin = entry->private_data;
533
534 mutex_lock(&per_pin->lock);
535 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
536 mutex_unlock(&per_pin->lock);
537}
538
539static void write_eld_info(struct snd_info_entry *entry,
540 struct snd_info_buffer *buffer)
541{
542 struct hdmi_spec_per_pin *per_pin = entry->private_data;
543
544 mutex_lock(&per_pin->lock);
545 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
546 mutex_unlock(&per_pin->lock);
547}
548
549static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
550{
551 char name[32];
552 struct hda_codec *codec = per_pin->codec;
553 struct snd_info_entry *entry;
554 int err;
555
556 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
557 err = snd_card_proc_new(codec->bus->card, name, &entry);
558 if (err < 0)
559 return err;
560
561 snd_info_set_text_ops(entry, per_pin, print_eld_info);
562 entry->c.text.write = write_eld_info;
563 entry->mode |= S_IWUSR;
564 per_pin->proc_entry = entry;
565
566 return 0;
567}
568
569static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
570{
571 if (!per_pin->codec->bus->shutdown && per_pin->proc_entry) {
572 snd_device_free(per_pin->codec->bus->card, per_pin->proc_entry);
573 per_pin->proc_entry = NULL;
574 }
575}
576#else
b55447a7
TI		 577static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
578 int index)
a4e9a38b
TI		 579{
580 return 0;
581}
b55447a7 582static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
a4e9a38b
TI		 583{
584}
585#endif
079d88cc
WF		 586
587/*
588 * Channel mapping routines
589 */
590
591/*
592 * Compute derived values in channel_allocations[].
593 */
594static void init_channel_allocations(void)
595{
596 int i, j;
597 struct cea_channel_speaker_allocation *p;
598
599 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
600 p = channel_allocations + i;
601 p->channels = 0;
602 p->spk_mask = 0;
603 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
604 if (p->speakers[j]) {
605 p->channels++;
606 p->spk_mask |= p->speakers[j];
607 }
608 }
609}
610
72357c78
WX		 611static int get_channel_allocation_order(int ca)
612{
613 int i;
614
615 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
616 if (channel_allocations[i].ca_index == ca)
617 break;
618 }
619 return i;
620}
621
079d88cc
WF		 622/*
623 * The transformation takes two steps:
624 *
625 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
626 * spk_mask => (channel_allocations[]) => ai->CA
627 *
628 * TODO: it could select the wrong CA from multiple candidates.
629*/
384a48d7 630static int hdmi_channel_allocation(struct hdmi_eld *eld, int channels)
079d88cc 631{
079d88cc 632 int i;
53d7d69d 633 int ca = 0;
079d88cc 634 int spk_mask = 0;
079d88cc
WF		 635 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
636
637 /*
638 * CA defaults to 0 for basic stereo audio
639 */
640 if (channels <= 2)
641 return 0;
642
079d88cc
WF		 643 /*
644 * expand ELD's speaker allocation mask
645 *
646 * ELD tells the speaker mask in a compact(paired) form,
647 * expand ELD's notions to match the ones used by Audio InfoFrame.
648 */
649 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
1613d6b4 650 if (eld->info.spk_alloc & (1 << i))
079d88cc
WF		 651 spk_mask |= eld_speaker_allocation_bits[i];
652 }
653
654 /* search for the first working match in the CA table */
655 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
656 if (channels == channel_allocations[i].channels &&
657 (spk_mask & channel_allocations[i].spk_mask) ==
658 channel_allocations[i].spk_mask) {
53d7d69d 659 ca = channel_allocations[i].ca_index;
079d88cc
WF		 660 break;
661 }
662 }
663
18e39186
AH		 664 if (!ca) {
665 /* if there was no match, select the regular ALSA channel
666 * allocation with the matching number of channels */
667 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
668 if (channels == channel_allocations[i].channels) {
669 ca = channel_allocations[i].ca_index;
670 break;
671 }
672 }
673 }
674
1613d6b4 675 snd_print_channel_allocation(eld->info.spk_alloc, buf, sizeof(buf));
2abbf439 676 snd_printdd("HDMI: select CA 0x%x for %d-channel allocation: %s\n",
53d7d69d 677 ca, channels, buf);
079d88cc 678
53d7d69d 679 return ca;
079d88cc
WF		 680}
681
682static void hdmi_debug_channel_mapping(struct hda_codec *codec,
683 hda_nid_t pin_nid)
684{
685#ifdef CONFIG_SND_DEBUG_VERBOSE
307229d2 686 struct hdmi_spec *spec = codec->spec;
079d88cc 687 int i;
307229d2 688 int channel;
079d88cc
WF		 689
690 for (i = 0; i < 8; i++) {
307229d2 691 channel = spec->ops.pin_get_slot_channel(codec, pin_nid, i);
079d88cc 692 printk(KERN_DEBUG "HDMI: ASP channel %d => slot %d\n",
307229d2 693 channel, i);
079d88cc
WF		 694 }
695#endif
696}
697
d45e6889 698static void hdmi_std_setup_channel_mapping(struct hda_codec *codec,
079d88cc 699 hda_nid_t pin_nid,
433968da 700 bool non_pcm,
53d7d69d 701 int ca)
079d88cc 702{
307229d2 703 struct hdmi_spec *spec = codec->spec;
90f28002 704 struct cea_channel_speaker_allocation *ch_alloc;
079d88cc 705 int i;
079d88cc 706 int err;
72357c78 707 int order;
433968da 708 int non_pcm_mapping[8];
079d88cc 709
72357c78 710 order = get_channel_allocation_order(ca);
90f28002 711 ch_alloc = &channel_allocations[order];
433968da 712
079d88cc 713 if (hdmi_channel_mapping[ca][1] == 0) {
90f28002
AH		 714 int hdmi_slot = 0;
715 /* fill actual channel mappings in ALSA channel (i) order */
716 for (i = 0; i < ch_alloc->channels; i++) {
717 while (!ch_alloc->speakers[7 - hdmi_slot] && !WARN_ON(hdmi_slot >= 8))
718 hdmi_slot++; /* skip zero slots */
719
720 hdmi_channel_mapping[ca][i] = (i << 4) | hdmi_slot++;
721 }
722 /* fill the rest of the slots with ALSA channel 0xf */
723 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++)
724 if (!ch_alloc->speakers[7 - hdmi_slot])
725 hdmi_channel_mapping[ca][i++] = (0xf << 4) | hdmi_slot;
079d88cc
WF		 726 }
727
433968da 728 if (non_pcm) {
90f28002 729 for (i = 0; i < ch_alloc->channels; i++)
11f7c52d 730 non_pcm_mapping[i] = (i << 4) | i;
433968da 731 for (; i < 8; i++)
11f7c52d 732 non_pcm_mapping[i] = (0xf << 4) | i;
433968da
WX		 733 }
734
079d88cc 735 for (i = 0; i < 8; i++) {
307229d2
AH		 736 int slotsetup = non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i];
737 int hdmi_slot = slotsetup & 0x0f;
738 int channel = (slotsetup & 0xf0) >> 4;
739 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot, channel);
079d88cc 740 if (err) {
2abbf439
WF		 741 snd_printdd(KERN_NOTICE
742 "HDMI: channel mapping failed\n");
079d88cc
WF		 743 break;
744 }
745 }
079d88cc
WF		 746}
747
d45e6889
TI		 748struct channel_map_table {
749 unsigned char map; /* ALSA API channel map position */
d45e6889
TI		 750 int spk_mask; /* speaker position bit mask */
751};
752
753static struct channel_map_table map_tables[] = {
a5b7d510
AH		 754 { SNDRV_CHMAP_FL, FL },
755 { SNDRV_CHMAP_FR, FR },
756 { SNDRV_CHMAP_RL, RL },
757 { SNDRV_CHMAP_RR, RR },
758 { SNDRV_CHMAP_LFE, LFE },
759 { SNDRV_CHMAP_FC, FC },
760 { SNDRV_CHMAP_RLC, RLC },
761 { SNDRV_CHMAP_RRC, RRC },
762 { SNDRV_CHMAP_RC, RC },
763 { SNDRV_CHMAP_FLC, FLC },
764 { SNDRV_CHMAP_FRC, FRC },
765 { SNDRV_CHMAP_FLH, FLH },
766 { SNDRV_CHMAP_FRH, FRH },
767 { SNDRV_CHMAP_FLW, FLW },
768 { SNDRV_CHMAP_FRW, FRW },
769 { SNDRV_CHMAP_TC, TC },
770 { SNDRV_CHMAP_FCH, FCH },
d45e6889
TI		 771 {} /* terminator */
772};
773
774/* from ALSA API channel position to speaker bit mask */
775static int to_spk_mask(unsigned char c)
776{
777 struct channel_map_table *t = map_tables;
778 for (; t->map; t++) {
779 if (t->map == c)
780 return t->spk_mask;
781 }
782 return 0;
783}
784
785/* from ALSA API channel position to CEA slot */
a5b7d510 786static int to_cea_slot(int ordered_ca, unsigned char pos)
d45e6889 787{
a5b7d510
AH		 788 int mask = to_spk_mask(pos);
789 int i;
d45e6889 790
a5b7d510
AH		 791 if (mask) {
792 for (i = 0; i < 8; i++) {
793 if (channel_allocations[ordered_ca].speakers[7 - i] == mask)
794 return i;
795 }
d45e6889 796 }
a5b7d510
AH		 797
798 return -1;
d45e6889
TI		 799}
800
801/* from speaker bit mask to ALSA API channel position */
802static int spk_to_chmap(int spk)
803{
804 struct channel_map_table *t = map_tables;
805 for (; t->map; t++) {
806 if (t->spk_mask == spk)
807 return t->map;
808 }
809 return 0;
810}
811
a5b7d510
AH		 812/* from CEA slot to ALSA API channel position */
813static int from_cea_slot(int ordered_ca, unsigned char slot)
814{
815 int mask = channel_allocations[ordered_ca].speakers[7 - slot];
816
817 return spk_to_chmap(mask);
818}
819
d45e6889
TI		 820/* get the CA index corresponding to the given ALSA API channel map */
821static int hdmi_manual_channel_allocation(int chs, unsigned char *map)
822{
823 int i, spks = 0, spk_mask = 0;
824
825 for (i = 0; i < chs; i++) {
826 int mask = to_spk_mask(map[i]);
827 if (mask) {
828 spk_mask |= mask;
829 spks++;
830 }
831 }
832
833 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
834 if ((chs == channel_allocations[i].channels ||
835 spks == channel_allocations[i].channels) &&
836 (spk_mask & channel_allocations[i].spk_mask) ==
837 channel_allocations[i].spk_mask)
838 return channel_allocations[i].ca_index;
839 }
840 return -1;
841}
842
843/* set up the channel slots for the given ALSA API channel map */
844static int hdmi_manual_setup_channel_mapping(struct hda_codec *codec,
845 hda_nid_t pin_nid,
a5b7d510
AH		 846 int chs, unsigned char *map,
847 int ca)
d45e6889 848{
307229d2 849 struct hdmi_spec *spec = codec->spec;
a5b7d510 850 int ordered_ca = get_channel_allocation_order(ca);
11f7c52d
AH		 851 int alsa_pos, hdmi_slot;
852 int assignments[8] = {[0 ... 7] = 0xf};
853
854 for (alsa_pos = 0; alsa_pos < chs; alsa_pos++) {
855
a5b7d510 856 hdmi_slot = to_cea_slot(ordered_ca, map[alsa_pos]);
11f7c52d
AH		 857
858 if (hdmi_slot < 0)
859 continue; /* unassigned channel */
860
861 assignments[hdmi_slot] = alsa_pos;
862 }
863
864 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++) {
307229d2 865 int err;
11f7c52d 866
307229d2
AH		 867 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot,
868 assignments[hdmi_slot]);
d45e6889
TI		 869 if (err)
870 return -EINVAL;
871 }
872 return 0;
873}
874
875/* store ALSA API channel map from the current default map */
876static void hdmi_setup_fake_chmap(unsigned char *map, int ca)
877{
878 int i;
56cac413 879 int ordered_ca = get_channel_allocation_order(ca);
d45e6889 880 for (i = 0; i < 8; i++) {
56cac413 881 if (i < channel_allocations[ordered_ca].channels)
a5b7d510 882 map[i] = from_cea_slot(ordered_ca, hdmi_channel_mapping[ca][i] & 0x0f);
d45e6889
TI		 883 else
884 map[i] = 0;
885 }
886}
887
888static void hdmi_setup_channel_mapping(struct hda_codec *codec,
889 hda_nid_t pin_nid, bool non_pcm, int ca,
20608731
AH		 890 int channels, unsigned char *map,
891 bool chmap_set)
d45e6889 892{
20608731 893 if (!non_pcm && chmap_set) {
d45e6889 894 hdmi_manual_setup_channel_mapping(codec, pin_nid,
a5b7d510 895 channels, map, ca);
d45e6889
TI		 896 } else {
897 hdmi_std_setup_channel_mapping(codec, pin_nid, non_pcm, ca);
898 hdmi_setup_fake_chmap(map, ca);
899 }
980b2495
AH		 900
901 hdmi_debug_channel_mapping(codec, pin_nid);
d45e6889 902}
079d88cc 903
307229d2
AH		 904static int hdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
905 int asp_slot, int channel)
906{
907 return snd_hda_codec_write(codec, pin_nid, 0,
908 AC_VERB_SET_HDMI_CHAN_SLOT,
909 (channel << 4) | asp_slot);
910}
911
912static int hdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
913 int asp_slot)
914{
915 return (snd_hda_codec_read(codec, pin_nid, 0,
916 AC_VERB_GET_HDMI_CHAN_SLOT,
917 asp_slot) & 0xf0) >> 4;
918}
919
079d88cc
WF		 920/*
921 * Audio InfoFrame routines
922 */
923
924/*
925 * Enable Audio InfoFrame Transmission
926 */
927static void hdmi_start_infoframe_trans(struct hda_codec *codec,
928 hda_nid_t pin_nid)
929{
930 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
931 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
932 AC_DIPXMIT_BEST);
933}
934
935/*
936 * Disable Audio InfoFrame Transmission
937 */
938static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
939 hda_nid_t pin_nid)
940{
941 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
942 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
943 AC_DIPXMIT_DISABLE);
944}
945
946static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
947{
948#ifdef CONFIG_SND_DEBUG_VERBOSE
949 int i;
950 int size;
951
952 size = snd_hdmi_get_eld_size(codec, pin_nid);
953 printk(KERN_DEBUG "HDMI: ELD buf size is %d\n", size);
954
955 for (i = 0; i < 8; i++) {
956 size = snd_hda_codec_read(codec, pin_nid, 0,
957 AC_VERB_GET_HDMI_DIP_SIZE, i);
958 printk(KERN_DEBUG "HDMI: DIP GP[%d] buf size is %d\n", i, size);
959 }
960#endif
961}
962
963static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
964{
965#ifdef BE_PARANOID
966 int i, j;
967 int size;
968 int pi, bi;
969 for (i = 0; i < 8; i++) {
970 size = snd_hda_codec_read(codec, pin_nid, 0,
971 AC_VERB_GET_HDMI_DIP_SIZE, i);
972 if (size == 0)
973 continue;
974
975 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
976 for (j = 1; j < 1000; j++) {
977 hdmi_write_dip_byte(codec, pin_nid, 0x0);
978 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
979 if (pi != i)
980 snd_printd(KERN_INFO "dip index %d: %d != %d\n",
981 bi, pi, i);
982 if (bi == 0) /* byte index wrapped around */
983 break;
984 }
985 snd_printd(KERN_INFO
986 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
987 i, size, j);
988 }
989#endif
990}
991
53d7d69d 992static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
079d88cc 993{
53d7d69d 994 u8 *bytes = (u8 *)hdmi_ai;
079d88cc
WF		 995 u8 sum = 0;
996 int i;
997
53d7d69d 998 hdmi_ai->checksum = 0;
079d88cc 999
53d7d69d 1000 for (i = 0; i < sizeof(*hdmi_ai); i++)
079d88cc
WF		 1001 sum += bytes[i];
1002
53d7d69d 1003 hdmi_ai->checksum = -sum;
079d88cc
WF		 1004}
1005
1006static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
1007 hda_nid_t pin_nid,
53d7d69d 1008 u8 *dip, int size)
079d88cc 1009{
079d88cc
WF		 1010 int i;
1011
1012 hdmi_debug_dip_size(codec, pin_nid);
1013 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
1014
079d88cc 1015 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d
WF		 1016 for (i = 0; i < size; i++)
1017 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
079d88cc
WF		 1018}
1019
1020static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
53d7d69d 1021 u8 *dip, int size)
079d88cc 1022{
079d88cc
WF		 1023 u8 val;
1024 int i;
1025
1026 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
1027 != AC_DIPXMIT_BEST)
1028 return false;
1029
1030 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d 1031 for (i = 0; i < size; i++) {
079d88cc
WF		 1032 val = snd_hda_codec_read(codec, pin_nid, 0,
1033 AC_VERB_GET_HDMI_DIP_DATA, 0);
53d7d69d 1034 if (val != dip[i])
079d88cc
WF		 1035 return false;
1036 }
1037
1038 return true;
1039}
1040
307229d2
AH		 1041static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
1042 hda_nid_t pin_nid,
1043 int ca, int active_channels,
1044 int conn_type)
1045{
1046 union audio_infoframe ai;
1047
1048 if (conn_type == 0) { /* HDMI */
1049 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
1050
1051 hdmi_ai->type = 0x84;
1052 hdmi_ai->ver = 0x01;
1053 hdmi_ai->len = 0x0a;
1054 hdmi_ai->CC02_CT47 = active_channels - 1;
1055 hdmi_ai->CA = ca;
1056 hdmi_checksum_audio_infoframe(hdmi_ai);
1057 } else if (conn_type == 1) { /* DisplayPort */
1058 struct dp_audio_infoframe *dp_ai = &ai.dp;
1059
1060 dp_ai->type = 0x84;
1061 dp_ai->len = 0x1b;
1062 dp_ai->ver = 0x11 << 2;
1063 dp_ai->CC02_CT47 = active_channels - 1;
1064 dp_ai->CA = ca;
1065 } else {
1066 snd_printd("HDMI: unknown connection type at pin %d\n",
1067 pin_nid);
1068 return;
1069 }
1070
1071 /*
1072 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
1073 * sizeof(*dp_ai) to avoid partial match/update problems when
1074 * the user switches between HDMI/DP monitors.
1075 */
1076 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
1077 sizeof(ai))) {
1078 snd_printdd("hdmi_pin_setup_infoframe: "
1079 "pin=%d channels=%d ca=0x%02x\n",
1080 pin_nid,
1081 active_channels, ca);
1082 hdmi_stop_infoframe_trans(codec, pin_nid);
1083 hdmi_fill_audio_infoframe(codec, pin_nid,
1084 ai.bytes, sizeof(ai));
1085 hdmi_start_infoframe_trans(codec, pin_nid);
1086 }
1087}
1088
b054087d
TI		 1089static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
1090 struct hdmi_spec_per_pin *per_pin,
1091 bool non_pcm)
079d88cc 1092{
307229d2 1093 struct hdmi_spec *spec = codec->spec;
384a48d7 1094 hda_nid_t pin_nid = per_pin->pin_nid;
b054087d 1095 int channels = per_pin->channels;
1df5a06a 1096 int active_channels;
384a48d7 1097 struct hdmi_eld *eld;
1df5a06a 1098 int ca, ordered_ca;
079d88cc 1099
b054087d
TI		 1100 if (!channels)
1101 return;
1102
58f7d28d
ML		 1103 if (is_haswell(codec))
1104 snd_hda_codec_write(codec, pin_nid, 0,
1105 AC_VERB_SET_AMP_GAIN_MUTE,
1106 AMP_OUT_UNMUTE);
1107
bce0d2a8 1108 eld = &per_pin->sink_eld;
384a48d7
SW		 1109 if (!eld->monitor_present)
1110 return;
079d88cc 1111
d45e6889
TI		 1112 if (!non_pcm && per_pin->chmap_set)
1113 ca = hdmi_manual_channel_allocation(channels, per_pin->chmap);
1114 else
1115 ca = hdmi_channel_allocation(eld, channels);
1116 if (ca < 0)
1117 ca = 0;
384a48d7 1118
1df5a06a
AH		 1119 ordered_ca = get_channel_allocation_order(ca);
1120 active_channels = channel_allocations[ordered_ca].channels;
1121
1122 hdmi_set_channel_count(codec, per_pin->cvt_nid, active_channels);
1123
39edac70
AH		 1124 /*
1125 * always configure channel mapping, it may have been changed by the
1126 * user in the meantime
1127 */
1128 hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
1129 channels, per_pin->chmap,
1130 per_pin->chmap_set);
1131
307229d2
AH		 1132 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
1133 eld->info.conn_type);
433968da 1134
1a6003b5 1135 per_pin->non_pcm = non_pcm;
079d88cc
WF		 1136}
1137
079d88cc
WF		 1138/*
1139 * Unsolicited events
1140 */
1141
c6e8453e 1142static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
38faddb1 1143
079d88cc
WF		 1144static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
1145{
1146 struct hdmi_spec *spec = codec->spec;
3a93897e
TI		 1147 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1148 int pin_nid;
384a48d7 1149 int pin_idx;
3a93897e 1150 struct hda_jack_tbl *jack;
2e59e5ab 1151 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
3a93897e
TI		 1152
1153 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
1154 if (!jack)
1155 return;
1156 pin_nid = jack->nid;
1157 jack->jack_dirty = 1;
079d88cc 1158
fae3d88a 1159 _snd_printd(SND_PR_VERBOSE,
2e59e5ab
ML		 1160 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
1161 codec->addr, pin_nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
fae3d88a 1162 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
079d88cc 1163
384a48d7
SW		 1164 pin_idx = pin_nid_to_pin_index(spec, pin_nid);
1165 if (pin_idx < 0)
079d88cc
WF		 1166 return;
1167
bce0d2a8 1168 hdmi_present_sense(get_pin(spec, pin_idx), 1);
01a61e12 1169 snd_hda_jack_report_sync(codec);
079d88cc
WF		 1170}
1171
1172static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
1173{
1174 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1175 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1176 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
1177 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
1178
1179 printk(KERN_INFO
e9ea8e8f 1180 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
384a48d7 1181 codec->addr,
079d88cc
WF		 1182 tag,
1183 subtag,
1184 cp_state,
1185 cp_ready);
1186
1187 /* TODO */
1188 if (cp_state)
1189 ;
1190 if (cp_ready)
1191 ;
1192}
1193
1194
1195static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
1196{
079d88cc
WF		 1197 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1198 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1199
3a93897e 1200 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
079d88cc
WF		 1201 snd_printd(KERN_INFO "Unexpected HDMI event tag 0x%x\n", tag);
1202 return;
1203 }
1204
1205 if (subtag == 0)
1206 hdmi_intrinsic_event(codec, res);
1207 else
1208 hdmi_non_intrinsic_event(codec, res);
1209}
1210
58f7d28d 1211static void haswell_verify_D0(struct hda_codec *codec,
53b434f0 1212 hda_nid_t cvt_nid, hda_nid_t nid)
83f26ad2 1213{
58f7d28d 1214 int pwr;
83f26ad2 1215
53b434f0
WX		 1216 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
1217 * thus pins could only choose converter 0 for use. Make sure the
1218 * converters are in correct power state */
fd678cac 1219 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
53b434f0
WX		 1220 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
1221
fd678cac 1222 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
83f26ad2
DH		 1223 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
1224 AC_PWRST_D0);
1225 msleep(40);
1226 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
1227 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
1228 snd_printd("Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
1229 }
83f26ad2
DH		 1230}
1231
079d88cc
WF		 1232/*
1233 * Callbacks
1234 */
1235
92f10b3f
TI		 1236/* HBR should be Non-PCM, 8 channels */
1237#define is_hbr_format(format) \
1238 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
1239
307229d2
AH		 1240static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
1241 bool hbr)
079d88cc 1242{
307229d2 1243 int pinctl, new_pinctl;
83f26ad2 1244
384a48d7
SW		 1245 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
1246 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
ea87d1c4
AH		 1247 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1248
1249 new_pinctl = pinctl & ~AC_PINCTL_EPT;
307229d2 1250 if (hbr)
ea87d1c4
AH		 1251 new_pinctl |= AC_PINCTL_EPT_HBR;
1252 else
1253 new_pinctl |= AC_PINCTL_EPT_NATIVE;
1254
307229d2 1255 snd_printdd("hdmi_pin_hbr_setup: "
ea87d1c4 1256 "NID=0x%x, %spinctl=0x%x\n",
384a48d7 1257 pin_nid,
ea87d1c4
AH		 1258 pinctl == new_pinctl ? "" : "new-",
1259 new_pinctl);
1260
1261 if (pinctl != new_pinctl)
384a48d7 1262 snd_hda_codec_write(codec, pin_nid, 0,
ea87d1c4
AH		 1263 AC_VERB_SET_PIN_WIDGET_CONTROL,
1264 new_pinctl);
307229d2
AH		 1265 } else if (hbr)
1266 return -EINVAL;
ea87d1c4 1267
307229d2
AH		 1268 return 0;
1269}
1270
1271static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
1272 hda_nid_t pin_nid, u32 stream_tag, int format)
1273{
1274 struct hdmi_spec *spec = codec->spec;
1275 int err;
1276
1277 if (is_haswell(codec))
1278 haswell_verify_D0(codec, cvt_nid, pin_nid);
1279
1280 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
1281
1282 if (err) {
ea87d1c4 1283 snd_printdd("hdmi_setup_stream: HBR is not supported\n");
307229d2 1284 return err;
ea87d1c4 1285 }
079d88cc 1286
384a48d7 1287 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
ea87d1c4 1288 return 0;
079d88cc
WF		 1289}
1290
7ef166b8
WX		 1291static int hdmi_choose_cvt(struct hda_codec *codec,
1292 int pin_idx, int *cvt_id, int *mux_id)
bbbe3390
TI		 1293{
1294 struct hdmi_spec *spec = codec->spec;
384a48d7 1295 struct hdmi_spec_per_pin *per_pin;
384a48d7 1296 struct hdmi_spec_per_cvt *per_cvt = NULL;
7ef166b8 1297 int cvt_idx, mux_idx = 0;
bbbe3390 1298
bce0d2a8 1299 per_pin = get_pin(spec, pin_idx);
384a48d7
SW		 1300
1301 /* Dynamically assign converter to stream */
1302 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
bce0d2a8 1303 per_cvt = get_cvt(spec, cvt_idx);
bbbe3390 1304
384a48d7
SW		 1305 /* Must not already be assigned */
1306 if (per_cvt->assigned)
1307 continue;
1308 /* Must be in pin's mux's list of converters */
1309 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1310 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
1311 break;
1312 /* Not in mux list */
1313 if (mux_idx == per_pin->num_mux_nids)
1314 continue;
1315 break;
1316 }
7ef166b8 1317
384a48d7
SW		 1318 /* No free converters */
1319 if (cvt_idx == spec->num_cvts)
1320 return -ENODEV;
1321
7ef166b8
WX		 1322 if (cvt_id)
1323 *cvt_id = cvt_idx;
1324 if (mux_id)
1325 *mux_id = mux_idx;
1326
1327 return 0;
1328}
1329
1330static void haswell_config_cvts(struct hda_codec *codec,
f82d7d16 1331 hda_nid_t pin_nid, int mux_idx)
7ef166b8
WX		 1332{
1333 struct hdmi_spec *spec = codec->spec;
f82d7d16
ML		 1334 hda_nid_t nid, end_nid;
1335 int cvt_idx, curr;
1336 struct hdmi_spec_per_cvt *per_cvt;
7ef166b8 1337
f82d7d16
ML		 1338 /* configure all pins, including "no physical connection" ones */
1339 end_nid = codec->start_nid + codec->num_nodes;
1340 for (nid = codec->start_nid; nid < end_nid; nid++) {
1341 unsigned int wid_caps = get_wcaps(codec, nid);
1342 unsigned int wid_type = get_wcaps_type(wid_caps);
1343
1344 if (wid_type != AC_WID_PIN)
1345 continue;
7ef166b8 1346
f82d7d16 1347 if (nid == pin_nid)
7ef166b8
WX		 1348 continue;
1349
f82d7d16 1350 curr = snd_hda_codec_read(codec, nid, 0,
7ef166b8 1351 AC_VERB_GET_CONNECT_SEL, 0);
f82d7d16
ML		 1352 if (curr != mux_idx)
1353 continue;
7ef166b8 1354
f82d7d16
ML		 1355 /* choose an unassigned converter. The conveters in the
1356 * connection list are in the same order as in the codec.
1357 */
1358 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1359 per_cvt = get_cvt(spec, cvt_idx);
1360 if (!per_cvt->assigned) {
1361 snd_printdd("choose cvt %d for pin nid %d\n",
1362 cvt_idx, nid);
1363 snd_hda_codec_write_cache(codec, nid, 0,
7ef166b8 1364 AC_VERB_SET_CONNECT_SEL,
f82d7d16
ML		 1365 cvt_idx);
1366 break;
1367 }
7ef166b8
WX		 1368 }
1369 }
1370}
1371
1372/*
1373 * HDA PCM callbacks
1374 */
1375static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1376 struct hda_codec *codec,
1377 struct snd_pcm_substream *substream)
1378{
1379 struct hdmi_spec *spec = codec->spec;
1380 struct snd_pcm_runtime *runtime = substream->runtime;
1381 int pin_idx, cvt_idx, mux_idx = 0;
1382 struct hdmi_spec_per_pin *per_pin;
1383 struct hdmi_eld *eld;
1384 struct hdmi_spec_per_cvt *per_cvt = NULL;
1385 int err;
1386
1387 /* Validate hinfo */
1388 pin_idx = hinfo_to_pin_index(spec, hinfo);
1389 if (snd_BUG_ON(pin_idx < 0))
1390 return -EINVAL;
1391 per_pin = get_pin(spec, pin_idx);
1392 eld = &per_pin->sink_eld;
1393
1394 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, &mux_idx);
1395 if (err < 0)
1396 return err;
1397
1398 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1399 /* Claim converter */
1400 per_cvt->assigned = 1;
1df5a06a 1401 per_pin->cvt_nid = per_cvt->cvt_nid;
384a48d7
SW		 1402 hinfo->nid = per_cvt->cvt_nid;
1403
bddee96b 1404 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
384a48d7
SW		 1405 AC_VERB_SET_CONNECT_SEL,
1406 mux_idx);
7ef166b8
WX		 1407
1408 /* configure unused pins to choose other converters */
fb87fa3a 1409 if (is_haswell(codec))
f82d7d16 1410 haswell_config_cvts(codec, per_pin->pin_nid, mux_idx);
7ef166b8 1411
384a48d7 1412 snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
bbbe3390 1413
2def8172 1414 /* Initially set the converter's capabilities */
384a48d7
SW		 1415 hinfo->channels_min = per_cvt->channels_min;
1416 hinfo->channels_max = per_cvt->channels_max;
1417 hinfo->rates = per_cvt->rates;
1418 hinfo->formats = per_cvt->formats;
1419 hinfo->maxbps = per_cvt->maxbps;
2def8172 1420
384a48d7 1421 /* Restrict capabilities by ELD if this isn't disabled */
c3d52105 1422 if (!static_hdmi_pcm && eld->eld_valid) {
1613d6b4 1423 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
bbbe3390 1424 if (hinfo->channels_min > hinfo->channels_max ||
2ad779b7
TI		 1425 !hinfo->rates || !hinfo->formats) {
1426 per_cvt->assigned = 0;
1427 hinfo->nid = 0;
1428 snd_hda_spdif_ctls_unassign(codec, pin_idx);
bbbe3390 1429 return -ENODEV;
2ad779b7 1430 }
bbbe3390 1431 }
2def8172
SW		 1432
1433 /* Store the updated parameters */
639cef0e
TI		 1434 runtime->hw.channels_min = hinfo->channels_min;
1435 runtime->hw.channels_max = hinfo->channels_max;
1436 runtime->hw.formats = hinfo->formats;
1437 runtime->hw.rates = hinfo->rates;
4fe2ca14
TI		 1438
1439 snd_pcm_hw_constraint_step(substream->runtime, 0,
1440 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
bbbe3390
TI		 1441 return 0;
1442}
1443
079d88cc
WF		 1444/*
1445 * HDA/HDMI auto parsing
1446 */
384a48d7 1447static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
079d88cc
WF		 1448{
1449 struct hdmi_spec *spec = codec->spec;
bce0d2a8 1450 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
384a48d7 1451 hda_nid_t pin_nid = per_pin->pin_nid;
079d88cc
WF		 1452
1453 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1454 snd_printk(KERN_WARNING
1455 "HDMI: pin %d wcaps %#x "
1456 "does not support connection list\n",
1457 pin_nid, get_wcaps(codec, pin_nid));
1458 return -EINVAL;
1459 }
1460
384a48d7
SW		 1461 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1462 per_pin->mux_nids,
1463 HDA_MAX_CONNECTIONS);
079d88cc
WF		 1464
1465 return 0;
1466}
1467
c6e8453e 1468static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
079d88cc 1469{
744626da 1470 struct hda_codec *codec = per_pin->codec;
4bd038f9
DH		 1471 struct hdmi_spec *spec = codec->spec;
1472 struct hdmi_eld *eld = &spec->temp_eld;
1473 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
744626da 1474 hda_nid_t pin_nid = per_pin->pin_nid;
5d44f927
SW		 1475 /*
1476 * Always execute a GetPinSense verb here, even when called from
1477 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1478 * response's PD bit is not the real PD value, but indicates that
1479 * the real PD value changed. An older version of the HD-audio
1480 * specification worked this way. Hence, we just ignore the data in
1481 * the unsolicited response to avoid custom WARs.
1482 */
079d88cc 1483 int present = snd_hda_pin_sense(codec, pin_nid);
4bd038f9
DH		 1484 bool update_eld = false;
1485 bool eld_changed = false;
079d88cc 1486
a4e9a38b 1487 mutex_lock(&per_pin->lock);
4bd038f9
DH		 1488 pin_eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1489 if (pin_eld->monitor_present)
1490 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1491 else
1492 eld->eld_valid = false;
079d88cc 1493
fae3d88a 1494 _snd_printd(SND_PR_VERBOSE,
384a48d7 1495 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
10250911 1496 codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid);
5d44f927 1497
4bd038f9 1498 if (eld->eld_valid) {
307229d2 1499 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1613d6b4 1500 &eld->eld_size) < 0)
4bd038f9 1501 eld->eld_valid = false;
1613d6b4
DH		 1502 else {
1503 memset(&eld->info, 0, sizeof(struct parsed_hdmi_eld));
1504 if (snd_hdmi_parse_eld(&eld->info, eld->eld_buffer,
1505 eld->eld_size) < 0)
4bd038f9 1506 eld->eld_valid = false;
1613d6b4
DH		 1507 }
1508
4bd038f9 1509 if (eld->eld_valid) {
1613d6b4 1510 snd_hdmi_show_eld(&eld->info);
4bd038f9 1511 update_eld = true;
1613d6b4 1512 }
c6e8453e 1513 else if (repoll) {
744626da
WF		 1514 queue_delayed_work(codec->bus->workq,
1515 &per_pin->work,
1516 msecs_to_jiffies(300));
cbbaa603 1517 goto unlock;
744626da
WF		 1518 }
1519 }
4bd038f9 1520
92c69e79 1521 if (pin_eld->eld_valid && !eld->eld_valid) {
4bd038f9 1522 update_eld = true;
92c69e79
DH		 1523 eld_changed = true;
1524 }
4bd038f9 1525 if (update_eld) {
b054087d 1526 bool old_eld_valid = pin_eld->eld_valid;
4bd038f9 1527 pin_eld->eld_valid = eld->eld_valid;
92c69e79
DH		 1528 eld_changed = pin_eld->eld_size != eld->eld_size ||
1529 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
4bd038f9
DH		 1530 eld->eld_size) != 0;
1531 if (eld_changed)
1532 memcpy(pin_eld->eld_buffer, eld->eld_buffer,
1533 eld->eld_size);
1534 pin_eld->eld_size = eld->eld_size;
1535 pin_eld->info = eld->info;
b054087d
TI		 1536
1537 /* Haswell-specific workaround: re-setup when the transcoder is
1538 * changed during the stream playback
1539 */
fb87fa3a 1540 if (is_haswell(codec) &&
58f7d28d 1541 eld->eld_valid && !old_eld_valid && per_pin->setup)
b054087d
TI		 1542 hdmi_setup_audio_infoframe(codec, per_pin,
1543 per_pin->non_pcm);
4bd038f9 1544 }
92c69e79
DH		 1545
1546 if (eld_changed)
1547 snd_ctl_notify(codec->bus->card,
1548 SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO,
1549 &per_pin->eld_ctl->id);
cbbaa603 1550 unlock:
a4e9a38b 1551 mutex_unlock(&per_pin->lock);
079d88cc
WF		 1552}
1553
744626da
WF		 1554static void hdmi_repoll_eld(struct work_struct *work)
1555{
1556 struct hdmi_spec_per_pin *per_pin =
1557 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1558
c6e8453e
WF		 1559 if (per_pin->repoll_count++ > 6)
1560 per_pin->repoll_count = 0;
1561
1562 hdmi_present_sense(per_pin, per_pin->repoll_count);
744626da
WF		 1563}
1564
c88d4e84
TI		 1565static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1566 hda_nid_t nid);
1567
079d88cc
WF		 1568static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1569{
1570 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1571 unsigned int caps, config;
1572 int pin_idx;
1573 struct hdmi_spec_per_pin *per_pin;
07acecc1 1574 int err;
079d88cc 1575
efc2f8de 1576 caps = snd_hda_query_pin_caps(codec, pin_nid);
384a48d7
SW		 1577 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1578 return 0;
1579
efc2f8de 1580 config = snd_hda_codec_get_pincfg(codec, pin_nid);
384a48d7
SW		 1581 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1582 return 0;
1583
fb87fa3a 1584 if (is_haswell(codec))
c88d4e84
TI		 1585 intel_haswell_fixup_connect_list(codec, pin_nid);
1586
384a48d7 1587 pin_idx = spec->num_pins;
bce0d2a8
TI		 1588 per_pin = snd_array_new(&spec->pins);
1589 if (!per_pin)
1590 return -ENOMEM;
384a48d7
SW		 1591
1592 per_pin->pin_nid = pin_nid;
1a6003b5 1593 per_pin->non_pcm = false;
079d88cc 1594
384a48d7
SW		 1595 err = hdmi_read_pin_conn(codec, pin_idx);
1596 if (err < 0)
1597 return err;
079d88cc 1598
079d88cc
WF		 1599 spec->num_pins++;
1600
384a48d7 1601 return 0;
079d88cc
WF		 1602}
1603
384a48d7 1604static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc
WF		 1605{
1606 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1607 struct hdmi_spec_per_cvt *per_cvt;
1608 unsigned int chans;
1609 int err;
079d88cc 1610
384a48d7
SW		 1611 chans = get_wcaps(codec, cvt_nid);
1612 chans = get_wcaps_channels(chans);
1613
bce0d2a8
TI		 1614 per_cvt = snd_array_new(&spec->cvts);
1615 if (!per_cvt)
1616 return -ENOMEM;
384a48d7
SW		 1617
1618 per_cvt->cvt_nid = cvt_nid;
1619 per_cvt->channels_min = 2;
d45e6889 1620 if (chans <= 16) {
384a48d7 1621 per_cvt->channels_max = chans;
d45e6889
TI		 1622 if (chans > spec->channels_max)
1623 spec->channels_max = chans;
1624 }
384a48d7
SW		 1625
1626 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1627 &per_cvt->rates,
1628 &per_cvt->formats,
1629 &per_cvt->maxbps);
1630 if (err < 0)
1631 return err;
1632
bce0d2a8
TI		 1633 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1634 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1635 spec->num_cvts++;
079d88cc
WF		 1636
1637 return 0;
1638}
1639
1640static int hdmi_parse_codec(struct hda_codec *codec)
1641{
1642 hda_nid_t nid;
1643 int i, nodes;
1644
1645 nodes = snd_hda_get_sub_nodes(codec, codec->afg, &nid);
1646 if (!nid || nodes < 0) {
1647 snd_printk(KERN_WARNING "HDMI: failed to get afg sub nodes\n");
1648 return -EINVAL;
1649 }
1650
1651 for (i = 0; i < nodes; i++, nid++) {
1652 unsigned int caps;
1653 unsigned int type;
1654
efc2f8de 1655 caps = get_wcaps(codec, nid);
079d88cc
WF		 1656 type = get_wcaps_type(caps);
1657
1658 if (!(caps & AC_WCAP_DIGITAL))
1659 continue;
1660
1661 switch (type) {
1662 case AC_WID_AUD_OUT:
384a48d7 1663 hdmi_add_cvt(codec, nid);
079d88cc
WF		 1664 break;
1665 case AC_WID_PIN:
3eaead57 1666 hdmi_add_pin(codec, nid);
079d88cc
WF		 1667 break;
1668 }
1669 }
1670
c9adeefd
DH		 1671#ifdef CONFIG_PM
1672 /* We're seeing some problems with unsolicited hot plug events on
1673 * PantherPoint after S3, if this is not enabled */
1674 if (codec->vendor_id == 0x80862806)
1675 codec->bus->power_keep_link_on = 1;
079d88cc
WF		 1676 /*
1677 * G45/IbexPeak don't support EPSS: the unsolicited pin hot plug event
1678 * can be lost and presence sense verb will become inaccurate if the
1679 * HDA link is powered off at hot plug or hw initialization time.
1680 */
c9adeefd 1681 else if (!(snd_hda_param_read(codec, codec->afg, AC_PAR_POWER_STATE) &
079d88cc
WF		 1682 AC_PWRST_EPSS))
1683 codec->bus->power_keep_link_on = 1;
1684#endif
1685
1686 return 0;
1687}
1688
84eb01be
TI		 1689/*
1690 */
1a6003b5
TI		 1691static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1692{
1693 struct hda_spdif_out *spdif;
1694 bool non_pcm;
1695
1696 mutex_lock(&codec->spdif_mutex);
1697 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1698 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1699 mutex_unlock(&codec->spdif_mutex);
1700 return non_pcm;
1701}
1702
1703
84eb01be
TI		 1704/*
1705 * HDMI callbacks
1706 */
1707
1708static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1709 struct hda_codec *codec,
1710 unsigned int stream_tag,
1711 unsigned int format,
1712 struct snd_pcm_substream *substream)
1713{
384a48d7
SW		 1714 hda_nid_t cvt_nid = hinfo->nid;
1715 struct hdmi_spec *spec = codec->spec;
1716 int pin_idx = hinfo_to_pin_index(spec, hinfo);
b054087d
TI		 1717 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1718 hda_nid_t pin_nid = per_pin->pin_nid;
1a6003b5
TI		 1719 bool non_pcm;
1720
1721 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
a4e9a38b 1722 mutex_lock(&per_pin->lock);
b054087d
TI		 1723 per_pin->channels = substream->runtime->channels;
1724 per_pin->setup = true;
384a48d7 1725
b054087d 1726 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
a4e9a38b 1727 mutex_unlock(&per_pin->lock);
84eb01be 1728
307229d2 1729 return spec->ops.setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
84eb01be
TI		 1730}
1731
8dfaa573
TI		 1732static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1733 struct hda_codec *codec,
1734 struct snd_pcm_substream *substream)
1735{
1736 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1737 return 0;
1738}
1739
f2ad24fa
TI		 1740static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1741 struct hda_codec *codec,
1742 struct snd_pcm_substream *substream)
384a48d7
SW		 1743{
1744 struct hdmi_spec *spec = codec->spec;
1745 int cvt_idx, pin_idx;
1746 struct hdmi_spec_per_cvt *per_cvt;
1747 struct hdmi_spec_per_pin *per_pin;
384a48d7 1748
384a48d7
SW		 1749 if (hinfo->nid) {
1750 cvt_idx = cvt_nid_to_cvt_index(spec, hinfo->nid);
1751 if (snd_BUG_ON(cvt_idx < 0))
1752 return -EINVAL;
bce0d2a8 1753 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1754
1755 snd_BUG_ON(!per_cvt->assigned);
1756 per_cvt->assigned = 0;
1757 hinfo->nid = 0;
1758
1759 pin_idx = hinfo_to_pin_index(spec, hinfo);
1760 if (snd_BUG_ON(pin_idx < 0))
1761 return -EINVAL;
bce0d2a8 1762 per_pin = get_pin(spec, pin_idx);
384a48d7 1763
384a48d7 1764 snd_hda_spdif_ctls_unassign(codec, pin_idx);
cbbaa603 1765
a4e9a38b 1766 mutex_lock(&per_pin->lock);
d45e6889
TI		 1767 per_pin->chmap_set = false;
1768 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
b054087d
TI		 1769
1770 per_pin->setup = false;
1771 per_pin->channels = 0;
a4e9a38b 1772 mutex_unlock(&per_pin->lock);
384a48d7 1773 }
d45e6889 1774
384a48d7
SW		 1775 return 0;
1776}
1777
1778static const struct hda_pcm_ops generic_ops = {
1779 .open = hdmi_pcm_open,
f2ad24fa 1780 .close = hdmi_pcm_close,
384a48d7 1781 .prepare = generic_hdmi_playback_pcm_prepare,
8dfaa573 1782 .cleanup = generic_hdmi_playback_pcm_cleanup,
84eb01be
TI		 1783};
1784
d45e6889
TI		 1785/*
1786 * ALSA API channel-map control callbacks
1787 */
1788static int hdmi_chmap_ctl_info(struct snd_kcontrol *kcontrol,
1789 struct snd_ctl_elem_info *uinfo)
1790{
1791 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1792 struct hda_codec *codec = info->private_data;
1793 struct hdmi_spec *spec = codec->spec;
1794 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1795 uinfo->count = spec->channels_max;
1796 uinfo->value.integer.min = 0;
1797 uinfo->value.integer.max = SNDRV_CHMAP_LAST;
1798 return 0;
1799}
1800
307229d2
AH		 1801static int hdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
1802 int channels)
1803{
1804 /* If the speaker allocation matches the channel count, it is OK.*/
1805 if (cap->channels != channels)
1806 return -1;
1807
1808 /* all channels are remappable freely */
1809 return SNDRV_CTL_TLVT_CHMAP_VAR;
1810}
1811
1812static void hdmi_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
1813 unsigned int *chmap, int channels)
1814{
1815 int count = 0;
1816 int c;
1817
1818 for (c = 7; c >= 0; c--) {
1819 int spk = cap->speakers[c];
1820 if (!spk)
1821 continue;
1822
1823 chmap[count++] = spk_to_chmap(spk);
1824 }
1825
1826 WARN_ON(count != channels);
1827}
1828
d45e6889
TI		 1829static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
1830 unsigned int size, unsigned int __user *tlv)
1831{
1832 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1833 struct hda_codec *codec = info->private_data;
1834 struct hdmi_spec *spec = codec->spec;
d45e6889
TI		 1835 unsigned int __user *dst;
1836 int chs, count = 0;
1837
1838 if (size < 8)
1839 return -ENOMEM;
1840 if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
1841 return -EFAULT;
1842 size -= 8;
1843 dst = tlv + 2;
498dab3a 1844 for (chs = 2; chs <= spec->channels_max; chs++) {
307229d2 1845 int i;
d45e6889
TI		 1846 struct cea_channel_speaker_allocation *cap;
1847 cap = channel_allocations;
1848 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++, cap++) {
1849 int chs_bytes = chs * 4;
307229d2
AH		 1850 int type = spec->ops.chmap_cea_alloc_validate_get_type(cap, chs);
1851 unsigned int tlv_chmap[8];
1852
1853 if (type < 0)
d45e6889 1854 continue;
d45e6889
TI		 1855 if (size < 8)
1856 return -ENOMEM;
307229d2 1857 if (put_user(type, dst) ||
d45e6889
TI		 1858 put_user(chs_bytes, dst + 1))
1859 return -EFAULT;
1860 dst += 2;
1861 size -= 8;
1862 count += 8;
1863 if (size < chs_bytes)
1864 return -ENOMEM;
1865 size -= chs_bytes;
1866 count += chs_bytes;
307229d2
AH		 1867 spec->ops.cea_alloc_to_tlv_chmap(cap, tlv_chmap, chs);
1868 if (copy_to_user(dst, tlv_chmap, chs_bytes))
1869 return -EFAULT;
1870 dst += chs;
d45e6889
TI		 1871 }
1872 }
1873 if (put_user(count, tlv + 1))
1874 return -EFAULT;
1875 return 0;
1876}
1877
1878static int hdmi_chmap_ctl_get(struct snd_kcontrol *kcontrol,
1879 struct snd_ctl_elem_value *ucontrol)
1880{
1881 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1882 struct hda_codec *codec = info->private_data;
1883 struct hdmi_spec *spec = codec->spec;
1884 int pin_idx = kcontrol->private_value;
bce0d2a8 1885 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
d45e6889
TI		 1886 int i;
1887
1888 for (i = 0; i < ARRAY_SIZE(per_pin->chmap); i++)
1889 ucontrol->value.integer.value[i] = per_pin->chmap[i];
1890 return 0;
1891}
1892
1893static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol,
1894 struct snd_ctl_elem_value *ucontrol)
1895{
1896 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1897 struct hda_codec *codec = info->private_data;
1898 struct hdmi_spec *spec = codec->spec;
1899 int pin_idx = kcontrol->private_value;
bce0d2a8 1900 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
d45e6889
TI		 1901 unsigned int ctl_idx;
1902 struct snd_pcm_substream *substream;
1903 unsigned char chmap[8];
307229d2 1904 int i, err, ca, prepared = 0;
d45e6889
TI		 1905
1906 ctl_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
1907 substream = snd_pcm_chmap_substream(info, ctl_idx);
1908 if (!substream || !substream->runtime)
6f54c361 1909 return 0; /* just for avoiding error from alsactl restore */
d45e6889
TI		 1910 switch (substream->runtime->status->state) {
1911 case SNDRV_PCM_STATE_OPEN:
1912 case SNDRV_PCM_STATE_SETUP:
1913 break;
1914 case SNDRV_PCM_STATE_PREPARED:
1915 prepared = 1;
1916 break;
1917 default:
1918 return -EBUSY;
1919 }
1920 memset(chmap, 0, sizeof(chmap));
1921 for (i = 0; i < ARRAY_SIZE(chmap); i++)
1922 chmap[i] = ucontrol->value.integer.value[i];
1923 if (!memcmp(chmap, per_pin->chmap, sizeof(chmap)))
1924 return 0;
1925 ca = hdmi_manual_channel_allocation(ARRAY_SIZE(chmap), chmap);
1926 if (ca < 0)
1927 return -EINVAL;
307229d2
AH		 1928 if (spec->ops.chmap_validate) {
1929 err = spec->ops.chmap_validate(ca, ARRAY_SIZE(chmap), chmap);
1930 if (err)
1931 return err;
1932 }
a4e9a38b 1933 mutex_lock(&per_pin->lock);
d45e6889
TI		 1934 per_pin->chmap_set = true;
1935 memcpy(per_pin->chmap, chmap, sizeof(chmap));
1936 if (prepared)
b054087d 1937 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
a4e9a38b 1938 mutex_unlock(&per_pin->lock);
d45e6889
TI		 1939
1940 return 0;
1941}
1942
84eb01be
TI		 1943static int generic_hdmi_build_pcms(struct hda_codec *codec)
1944{
1945 struct hdmi_spec *spec = codec->spec;
384a48d7 1946 int pin_idx;
84eb01be 1947
384a48d7
SW		 1948 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1949 struct hda_pcm *info;
84eb01be 1950 struct hda_pcm_stream *pstr;
bce0d2a8
TI		 1951 struct hdmi_spec_per_pin *per_pin;
1952
1953 per_pin = get_pin(spec, pin_idx);
1954 sprintf(per_pin->pcm_name, "HDMI %d", pin_idx);
1955 info = snd_array_new(&spec->pcm_rec);
1956 if (!info)
1957 return -ENOMEM;
1958 info->name = per_pin->pcm_name;
84eb01be 1959 info->pcm_type = HDA_PCM_TYPE_HDMI;
d45e6889 1960 info->own_chmap = true;
384a48d7 1961
84eb01be 1962 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
384a48d7
SW		 1963 pstr->substreams = 1;
1964 pstr->ops = generic_ops;
1965 /* other pstr fields are set in open */
84eb01be
TI		 1966 }
1967
384a48d7 1968 codec->num_pcms = spec->num_pins;
bce0d2a8 1969 codec->pcm_info = spec->pcm_rec.list;
384a48d7 1970
84eb01be
TI		 1971 return 0;
1972}
1973
0b6c49b5
DH		 1974static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
1975{
31ef2257 1976 char hdmi_str[32] = "HDMI/DP";
0b6c49b5 1977 struct hdmi_spec *spec = codec->spec;
bce0d2a8
TI		 1978 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1979 int pcmdev = get_pcm_rec(spec, pin_idx)->device;
0b6c49b5 1980
31ef2257
TI		 1981 if (pcmdev > 0)
1982 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
30efd8de
DH		 1983 if (!is_jack_detectable(codec, per_pin->pin_nid))
1984 strncat(hdmi_str, " Phantom",
1985 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
0b6c49b5 1986
31ef2257 1987 return snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str, 0);
0b6c49b5
DH		 1988}
1989
84eb01be
TI		 1990static int generic_hdmi_build_controls(struct hda_codec *codec)
1991{
1992 struct hdmi_spec *spec = codec->spec;
1993 int err;
384a48d7 1994 int pin_idx;
84eb01be 1995
384a48d7 1996 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 1997 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
0b6c49b5
DH		 1998
1999 err = generic_hdmi_build_jack(codec, pin_idx);
2000 if (err < 0)
2001 return err;
2002
dcda5806
TI		 2003 err = snd_hda_create_dig_out_ctls(codec,
2004 per_pin->pin_nid,
2005 per_pin->mux_nids[0],
2006 HDA_PCM_TYPE_HDMI);
84eb01be
TI		 2007 if (err < 0)
2008 return err;
384a48d7 2009 snd_hda_spdif_ctls_unassign(codec, pin_idx);
14bc52b8
PLB		 2010
2011 /* add control for ELD Bytes */
bce0d2a8
TI		 2012 err = hdmi_create_eld_ctl(codec, pin_idx,
2013 get_pcm_rec(spec, pin_idx)->device);
14bc52b8
PLB		 2014
2015 if (err < 0)
2016 return err;
31ef2257 2017
82b1d73f 2018 hdmi_present_sense(per_pin, 0);
84eb01be
TI		 2019 }
2020
d45e6889
TI		 2021 /* add channel maps */
2022 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2023 struct snd_pcm_chmap *chmap;
2024 struct snd_kcontrol *kctl;
2025 int i;
2ca320e2
TI		 2026
2027 if (!codec->pcm_info[pin_idx].pcm)
2028 break;
d45e6889
TI		 2029 err = snd_pcm_add_chmap_ctls(codec->pcm_info[pin_idx].pcm,
2030 SNDRV_PCM_STREAM_PLAYBACK,
2031 NULL, 0, pin_idx, &chmap);
2032 if (err < 0)
2033 return err;
2034 /* override handlers */
2035 chmap->private_data = codec;
2036 kctl = chmap->kctl;
2037 for (i = 0; i < kctl->count; i++)
2038 kctl->vd[i].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
2039 kctl->info = hdmi_chmap_ctl_info;
2040 kctl->get = hdmi_chmap_ctl_get;
2041 kctl->put = hdmi_chmap_ctl_put;
2042 kctl->tlv.c = hdmi_chmap_ctl_tlv;
2043 }
2044
84eb01be
TI		 2045 return 0;
2046}
2047
8b8d654b 2048static int generic_hdmi_init_per_pins(struct hda_codec *codec)
84eb01be
TI		 2049{
2050 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 2051 int pin_idx;
2052
2053 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2054 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
84eb01be 2055
744626da 2056 per_pin->codec = codec;
a4e9a38b 2057 mutex_init(&per_pin->lock);
744626da 2058 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
a4e9a38b 2059 eld_proc_new(per_pin, pin_idx);
84eb01be 2060 }
8b8d654b
TI		 2061 return 0;
2062}
2063
2064static int generic_hdmi_init(struct hda_codec *codec)
2065{
2066 struct hdmi_spec *spec = codec->spec;
2067 int pin_idx;
2068
2069 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2070 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
8b8d654b
TI		 2071 hda_nid_t pin_nid = per_pin->pin_nid;
2072
2073 hdmi_init_pin(codec, pin_nid);
2074 snd_hda_jack_detect_enable(codec, pin_nid, pin_nid);
2075 }
84eb01be
TI		 2076 return 0;
2077}
2078
bce0d2a8
TI		 2079static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2080{
2081 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2082 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2083 snd_array_init(&spec->pcm_rec, sizeof(struct hda_pcm), nums);
2084}
2085
2086static void hdmi_array_free(struct hdmi_spec *spec)
2087{
2088 snd_array_free(&spec->pins);
2089 snd_array_free(&spec->cvts);
2090 snd_array_free(&spec->pcm_rec);
2091}
2092
84eb01be
TI		 2093static void generic_hdmi_free(struct hda_codec *codec)
2094{
2095 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 2096 int pin_idx;
2097
2098 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2099 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
84eb01be 2100
744626da 2101 cancel_delayed_work(&per_pin->work);
a4e9a38b 2102 eld_proc_free(per_pin);
384a48d7 2103 }
84eb01be 2104
744626da 2105 flush_workqueue(codec->bus->workq);
bce0d2a8 2106 hdmi_array_free(spec);
84eb01be
TI		 2107 kfree(spec);
2108}
2109
28cb72e5
WX		 2110#ifdef CONFIG_PM
2111static int generic_hdmi_resume(struct hda_codec *codec)
2112{
2113 struct hdmi_spec *spec = codec->spec;
2114 int pin_idx;
2115
2116 generic_hdmi_init(codec);
2117 snd_hda_codec_resume_amp(codec);
2118 snd_hda_codec_resume_cache(codec);
2119
2120 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2121 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2122 hdmi_present_sense(per_pin, 1);
2123 }
2124 return 0;
2125}
2126#endif
2127
fb79e1e0 2128static const struct hda_codec_ops generic_hdmi_patch_ops = {
84eb01be
TI		 2129 .init = generic_hdmi_init,
2130 .free = generic_hdmi_free,
2131 .build_pcms = generic_hdmi_build_pcms,
2132 .build_controls = generic_hdmi_build_controls,
2133 .unsol_event = hdmi_unsol_event,
28cb72e5
WX		 2134#ifdef CONFIG_PM
2135 .resume = generic_hdmi_resume,
2136#endif
84eb01be
TI		 2137};
2138
307229d2
AH		 2139static const struct hdmi_ops generic_standard_hdmi_ops = {
2140 .pin_get_eld = snd_hdmi_get_eld,
2141 .pin_get_slot_channel = hdmi_pin_get_slot_channel,
2142 .pin_set_slot_channel = hdmi_pin_set_slot_channel,
2143 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2144 .pin_hbr_setup = hdmi_pin_hbr_setup,
2145 .setup_stream = hdmi_setup_stream,
2146 .chmap_cea_alloc_validate_get_type = hdmi_chmap_cea_alloc_validate_get_type,
2147 .cea_alloc_to_tlv_chmap = hdmi_cea_alloc_to_tlv_chmap,
2148};
2149
6ffe168f 2150
c88d4e84
TI		 2151static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2152 hda_nid_t nid)
2153{
2154 struct hdmi_spec *spec = codec->spec;
2155 hda_nid_t conns[4];
2156 int nconns;
6ffe168f 2157
c88d4e84
TI		 2158 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2159 if (nconns == spec->num_cvts &&
2160 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
6ffe168f
ML		 2161 return;
2162
c88d4e84
TI		 2163 /* override pins connection list */
2164 snd_printdd("hdmi: haswell: override pin connection 0x%x\n", nid);
2165 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
6ffe168f
ML		 2166}
2167
1611a9c9
ML		 2168#define INTEL_VENDOR_NID 0x08
2169#define INTEL_GET_VENDOR_VERB 0xf81
2170#define INTEL_SET_VENDOR_VERB 0x781
2171#define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2172#define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2173
2174static void intel_haswell_enable_all_pins(struct hda_codec *codec,
17df3f55 2175 bool update_tree)
1611a9c9
ML		 2176{
2177 unsigned int vendor_param;
2178
1611a9c9
ML		 2179 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2180 INTEL_GET_VENDOR_VERB, 0);
2181 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2182 return;
2183
2184 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2185 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2186 INTEL_SET_VENDOR_VERB, vendor_param);
2187 if (vendor_param == -1)
2188 return;
2189
17df3f55
TI		 2190 if (update_tree)
2191 snd_hda_codec_update_widgets(codec);
1611a9c9
ML		 2192}
2193
c88d4e84
TI		 2194static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2195{
2196 unsigned int vendor_param;
2197
2198 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2199 INTEL_GET_VENDOR_VERB, 0);
2200 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2201 return;
2202
2203 /* enable DP1.2 mode */
2204 vendor_param |= INTEL_EN_DP12;
2205 snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
2206 INTEL_SET_VENDOR_VERB, vendor_param);
2207}
2208
17df3f55
TI		 2209/* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2210 * Otherwise you may get severe h/w communication errors.
2211 */
2212static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2213 unsigned int power_state)
2214{
2215 if (power_state == AC_PWRST_D0) {
2216 intel_haswell_enable_all_pins(codec, false);
2217 intel_haswell_fixup_enable_dp12(codec);
2218 }
c88d4e84 2219
17df3f55
TI		 2220 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2221 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2222}
6ffe168f 2223
84eb01be
TI		 2224static int patch_generic_hdmi(struct hda_codec *codec)
2225{
2226 struct hdmi_spec *spec;
84eb01be
TI		 2227
2228 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2229 if (spec == NULL)
2230 return -ENOMEM;
2231
307229d2 2232 spec->ops = generic_standard_hdmi_ops;
84eb01be 2233 codec->spec = spec;
bce0d2a8 2234 hdmi_array_init(spec, 4);
6ffe168f 2235
fb87fa3a 2236 if (is_haswell(codec)) {
17df3f55 2237 intel_haswell_enable_all_pins(codec, true);
c88d4e84 2238 intel_haswell_fixup_enable_dp12(codec);
17df3f55 2239 }
6ffe168f 2240
84eb01be
TI		 2241 if (hdmi_parse_codec(codec) < 0) {
2242 codec->spec = NULL;
2243 kfree(spec);
2244 return -EINVAL;
2245 }
2246 codec->patch_ops = generic_hdmi_patch_ops;
fb87fa3a 2247 if (is_haswell(codec)) {
17df3f55 2248 codec->patch_ops.set_power_state = haswell_set_power_state;
5dc989bd
ML		 2249 codec->dp_mst = true;
2250 }
17df3f55 2251
8b8d654b 2252 generic_hdmi_init_per_pins(codec);
84eb01be 2253
84eb01be
TI		 2254 init_channel_allocations();
2255
2256 return 0;
2257}
2258
3aaf8980
SW		 2259/*
2260 * Shared non-generic implementations
2261 */
2262
2263static int simple_playback_build_pcms(struct hda_codec *codec)
2264{
2265 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2266 struct hda_pcm *info;
8ceb332d
TI		 2267 unsigned int chans;
2268 struct hda_pcm_stream *pstr;
bce0d2a8 2269 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2270
bce0d2a8
TI		 2271 per_cvt = get_cvt(spec, 0);
2272 chans = get_wcaps(codec, per_cvt->cvt_nid);
8ceb332d 2273 chans = get_wcaps_channels(chans);
3aaf8980 2274
bce0d2a8
TI		 2275 info = snd_array_new(&spec->pcm_rec);
2276 if (!info)
2277 return -ENOMEM;
2278 info->name = get_pin(spec, 0)->pcm_name;
2279 sprintf(info->name, "HDMI 0");
8ceb332d
TI		 2280 info->pcm_type = HDA_PCM_TYPE_HDMI;
2281 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2282 *pstr = spec->pcm_playback;
bce0d2a8 2283 pstr->nid = per_cvt->cvt_nid;
8ceb332d
TI		 2284 if (pstr->channels_max <= 2 && chans && chans <= 16)
2285 pstr->channels_max = chans;
3aaf8980 2286
bce0d2a8
TI		 2287 codec->num_pcms = 1;
2288 codec->pcm_info = info;
2289
3aaf8980
SW		 2290 return 0;
2291}
2292
4b6ace9e
TI		 2293/* unsolicited event for jack sensing */
2294static void simple_hdmi_unsol_event(struct hda_codec *codec,
2295 unsigned int res)
2296{
9dd8cf12 2297 snd_hda_jack_set_dirty_all(codec);
4b6ace9e
TI		 2298 snd_hda_jack_report_sync(codec);
2299}
2300
2301/* generic_hdmi_build_jack can be used for simple_hdmi, too,
2302 * as long as spec->pins[] is set correctly
2303 */
2304#define simple_hdmi_build_jack generic_hdmi_build_jack
2305
3aaf8980
SW		 2306static int simple_playback_build_controls(struct hda_codec *codec)
2307{
2308 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2309 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2310 int err;
3aaf8980 2311
bce0d2a8
TI		 2312 per_cvt = get_cvt(spec, 0);
2313 err = snd_hda_create_spdif_out_ctls(codec, per_cvt->cvt_nid,
2314 per_cvt->cvt_nid);
8ceb332d
TI		 2315 if (err < 0)
2316 return err;
2317 return simple_hdmi_build_jack(codec, 0);
3aaf8980
SW		 2318}
2319
4f0110ce
TI		 2320static int simple_playback_init(struct hda_codec *codec)
2321{
2322 struct hdmi_spec *spec = codec->spec;
bce0d2a8
TI		 2323 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2324 hda_nid_t pin = per_pin->pin_nid;
8ceb332d
TI		 2325
2326 snd_hda_codec_write(codec, pin, 0,
2327 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2328 /* some codecs require to unmute the pin */
2329 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2330 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2331 AMP_OUT_UNMUTE);
2332 snd_hda_jack_detect_enable(codec, pin, pin);
4f0110ce
TI		 2333 return 0;
2334}
2335
3aaf8980
SW		 2336static void simple_playback_free(struct hda_codec *codec)
2337{
2338 struct hdmi_spec *spec = codec->spec;
2339
bce0d2a8 2340 hdmi_array_free(spec);
3aaf8980
SW		 2341 kfree(spec);
2342}
2343
84eb01be
TI		 2344/*
2345 * Nvidia specific implementations
2346 */
2347
2348#define Nv_VERB_SET_Channel_Allocation 0xF79
2349#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2350#define Nv_VERB_SET_Audio_Protection_On 0xF98
2351#define Nv_VERB_SET_Audio_Protection_Off 0xF99
2352
2353#define nvhdmi_master_con_nid_7x 0x04
2354#define nvhdmi_master_pin_nid_7x 0x05
2355
fb79e1e0 2356static const hda_nid_t nvhdmi_con_nids_7x[4] = {
84eb01be
TI		 2357 /*front, rear, clfe, rear_surr */
2358 0x6, 0x8, 0xa, 0xc,
2359};
2360
ceaa86ba
TI		 2361static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2362 /* set audio protect on */
2363 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2364 /* enable digital output on pin widget */
2365 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2366 {} /* terminator */
2367};
2368
2369static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
84eb01be
TI		 2370 /* set audio protect on */
2371 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2372 /* enable digital output on pin widget */
2373 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2374 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2375 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2376 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2377 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2378 {} /* terminator */
2379};
2380
2381#ifdef LIMITED_RATE_FMT_SUPPORT
2382/* support only the safe format and rate */
2383#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2384#define SUPPORTED_MAXBPS 16
2385#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2386#else
2387/* support all rates and formats */
2388#define SUPPORTED_RATES \
2389 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2390 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2391 SNDRV_PCM_RATE_192000)
2392#define SUPPORTED_MAXBPS 24
2393#define SUPPORTED_FORMATS \
2394 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2395#endif
2396
ceaa86ba
TI		 2397static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2398{
2399 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2400 return 0;
2401}
2402
2403static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
84eb01be 2404{
ceaa86ba 2405 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
84eb01be
TI		 2406 return 0;
2407}
2408
393004b2
ND		 2409static unsigned int channels_2_6_8[] = {
2410 2, 6, 8
2411};
2412
2413static unsigned int channels_2_8[] = {
2414 2, 8
2415};
2416
2417static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2418 .count = ARRAY_SIZE(channels_2_6_8),
2419 .list = channels_2_6_8,
2420 .mask = 0,
2421};
2422
2423static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2424 .count = ARRAY_SIZE(channels_2_8),
2425 .list = channels_2_8,
2426 .mask = 0,
2427};
2428
84eb01be
TI		 2429static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2430 struct hda_codec *codec,
2431 struct snd_pcm_substream *substream)
2432{
2433 struct hdmi_spec *spec = codec->spec;
393004b2
ND		 2434 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2435
2436 switch (codec->preset->id) {
2437 case 0x10de0002:
2438 case 0x10de0003:
2439 case 0x10de0005:
2440 case 0x10de0006:
2441 hw_constraints_channels = &hw_constraints_2_8_channels;
2442 break;
2443 case 0x10de0007:
2444 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2445 break;
2446 default:
2447 break;
2448 }
2449
2450 if (hw_constraints_channels != NULL) {
2451 snd_pcm_hw_constraint_list(substream->runtime, 0,
2452 SNDRV_PCM_HW_PARAM_CHANNELS,
2453 hw_constraints_channels);
ad09fc9d
TI		 2454 } else {
2455 snd_pcm_hw_constraint_step(substream->runtime, 0,
2456 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
393004b2
ND		 2457 }
2458
84eb01be
TI		 2459 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2460}
2461
2462static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2463 struct hda_codec *codec,
2464 struct snd_pcm_substream *substream)
2465{
2466 struct hdmi_spec *spec = codec->spec;
2467 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2468}
2469
2470static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2471 struct hda_codec *codec,
2472 unsigned int stream_tag,
2473 unsigned int format,
2474 struct snd_pcm_substream *substream)
2475{
2476 struct hdmi_spec *spec = codec->spec;
2477 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2478 stream_tag, format, substream);
2479}
2480
d0b1252d
TI		 2481static const struct hda_pcm_stream simple_pcm_playback = {
2482 .substreams = 1,
2483 .channels_min = 2,
2484 .channels_max = 2,
2485 .ops = {
2486 .open = simple_playback_pcm_open,
2487 .close = simple_playback_pcm_close,
2488 .prepare = simple_playback_pcm_prepare
2489 },
2490};
2491
2492static const struct hda_codec_ops simple_hdmi_patch_ops = {
2493 .build_controls = simple_playback_build_controls,
2494 .build_pcms = simple_playback_build_pcms,
2495 .init = simple_playback_init,
2496 .free = simple_playback_free,
250e41ac 2497 .unsol_event = simple_hdmi_unsol_event,
d0b1252d
TI		 2498};
2499
2500static int patch_simple_hdmi(struct hda_codec *codec,
2501 hda_nid_t cvt_nid, hda_nid_t pin_nid)
2502{
2503 struct hdmi_spec *spec;
bce0d2a8
TI		 2504 struct hdmi_spec_per_cvt *per_cvt;
2505 struct hdmi_spec_per_pin *per_pin;
d0b1252d
TI		 2506
2507 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2508 if (!spec)
2509 return -ENOMEM;
2510
2511 codec->spec = spec;
bce0d2a8 2512 hdmi_array_init(spec, 1);
d0b1252d
TI		 2513
2514 spec->multiout.num_dacs = 0; /* no analog */
2515 spec->multiout.max_channels = 2;
2516 spec->multiout.dig_out_nid = cvt_nid;
2517 spec->num_cvts = 1;
2518 spec->num_pins = 1;
bce0d2a8
TI		 2519 per_pin = snd_array_new(&spec->pins);
2520 per_cvt = snd_array_new(&spec->cvts);
2521 if (!per_pin || !per_cvt) {
2522 simple_playback_free(codec);
2523 return -ENOMEM;
2524 }
2525 per_cvt->cvt_nid = cvt_nid;
2526 per_pin->pin_nid = pin_nid;
d0b1252d
TI		 2527 spec->pcm_playback = simple_pcm_playback;
2528
2529 codec->patch_ops = simple_hdmi_patch_ops;
2530
2531 return 0;
2532}
2533
1f348522
AP		 2534static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2535 int channels)
2536{
2537 unsigned int chanmask;
2538 int chan = channels ? (channels - 1) : 1;
2539
2540 switch (channels) {
2541 default:
2542 case 0:
2543 case 2:
2544 chanmask = 0x00;
2545 break;
2546 case 4:
2547 chanmask = 0x08;
2548 break;
2549 case 6:
2550 chanmask = 0x0b;
2551 break;
2552 case 8:
2553 chanmask = 0x13;
2554 break;
2555 }
2556
2557 /* Set the audio infoframe channel allocation and checksum fields. The
2558 * channel count is computed implicitly by the hardware. */
2559 snd_hda_codec_write(codec, 0x1, 0,
2560 Nv_VERB_SET_Channel_Allocation, chanmask);
2561
2562 snd_hda_codec_write(codec, 0x1, 0,
2563 Nv_VERB_SET_Info_Frame_Checksum,
2564 (0x71 - chan - chanmask));
2565}
2566
84eb01be
TI		 2567static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2568 struct hda_codec *codec,
2569 struct snd_pcm_substream *substream)
2570{
2571 struct hdmi_spec *spec = codec->spec;
2572 int i;
2573
2574 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2575 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2576 for (i = 0; i < 4; i++) {
2577 /* set the stream id */
2578 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2579 AC_VERB_SET_CHANNEL_STREAMID, 0);
2580 /* set the stream format */
2581 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2582 AC_VERB_SET_STREAM_FORMAT, 0);
2583 }
2584
1f348522
AP		 2585 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2586 * streams are disabled. */
2587 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2588
84eb01be
TI		 2589 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2590}
2591
2592static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2593 struct hda_codec *codec,
2594 unsigned int stream_tag,
2595 unsigned int format,
2596 struct snd_pcm_substream *substream)
2597{
2598 int chs;
112daa7a 2599 unsigned int dataDCC2, channel_id;
84eb01be 2600 int i;
7c935976 2601 struct hdmi_spec *spec = codec->spec;
e3245cdd 2602 struct hda_spdif_out *spdif;
bce0d2a8 2603 struct hdmi_spec_per_cvt *per_cvt;
84eb01be
TI		 2604
2605 mutex_lock(&codec->spdif_mutex);
bce0d2a8
TI		 2606 per_cvt = get_cvt(spec, 0);
2607 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
84eb01be
TI		 2608
2609 chs = substream->runtime->channels;
84eb01be 2610
84eb01be
TI		 2611 dataDCC2 = 0x2;
2612
84eb01be 2613 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
7c935976 2614 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 2615 snd_hda_codec_write(codec,
2616 nvhdmi_master_con_nid_7x,
2617 0,
2618 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2619 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 2620
2621 /* set the stream id */
2622 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2623 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
2624
2625 /* set the stream format */
2626 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2627 AC_VERB_SET_STREAM_FORMAT, format);
2628
2629 /* turn on again (if needed) */
2630 /* enable and set the channel status audio/data flag */
7c935976 2631 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 2632 snd_hda_codec_write(codec,
2633 nvhdmi_master_con_nid_7x,
2634 0,
2635 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2636 spdif->ctls & 0xff);
84eb01be
TI		 2637 snd_hda_codec_write(codec,
2638 nvhdmi_master_con_nid_7x,
2639 0,
2640 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2641 }
2642
2643 for (i = 0; i < 4; i++) {
2644 if (chs == 2)
2645 channel_id = 0;
2646 else
2647 channel_id = i * 2;
2648
2649 /* turn off SPDIF once;
2650 *otherwise the IEC958 bits won't be updated
2651 */
2652 if (codec->spdif_status_reset &&
7c935976 2653 (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 2654 snd_hda_codec_write(codec,
2655 nvhdmi_con_nids_7x[i],
2656 0,
2657 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2658 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 2659 /* set the stream id */
2660 snd_hda_codec_write(codec,
2661 nvhdmi_con_nids_7x[i],
2662 0,
2663 AC_VERB_SET_CHANNEL_STREAMID,
2664 (stream_tag << 4) | channel_id);
2665 /* set the stream format */
2666 snd_hda_codec_write(codec,
2667 nvhdmi_con_nids_7x[i],
2668 0,
2669 AC_VERB_SET_STREAM_FORMAT,
2670 format);
2671 /* turn on again (if needed) */
2672 /* enable and set the channel status audio/data flag */
2673 if (codec->spdif_status_reset &&
7c935976 2674 (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 2675 snd_hda_codec_write(codec,
2676 nvhdmi_con_nids_7x[i],
2677 0,
2678 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2679 spdif->ctls & 0xff);
84eb01be
TI		 2680 snd_hda_codec_write(codec,
2681 nvhdmi_con_nids_7x[i],
2682 0,
2683 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2684 }
2685 }
2686
1f348522 2687 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
84eb01be
TI		 2688
2689 mutex_unlock(&codec->spdif_mutex);
2690 return 0;
2691}
2692
fb79e1e0 2693static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
84eb01be
TI		 2694 .substreams = 1,
2695 .channels_min = 2,
2696 .channels_max = 8,
2697 .nid = nvhdmi_master_con_nid_7x,
2698 .rates = SUPPORTED_RATES,
2699 .maxbps = SUPPORTED_MAXBPS,
2700 .formats = SUPPORTED_FORMATS,
2701 .ops = {
2702 .open = simple_playback_pcm_open,
2703 .close = nvhdmi_8ch_7x_pcm_close,
2704 .prepare = nvhdmi_8ch_7x_pcm_prepare
2705 },
2706};
2707
84eb01be
TI		 2708static int patch_nvhdmi_2ch(struct hda_codec *codec)
2709{
2710 struct hdmi_spec *spec;
d0b1252d
TI		 2711 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
2712 nvhdmi_master_pin_nid_7x);
2713 if (err < 0)
2714 return err;
84eb01be 2715
ceaa86ba 2716 codec->patch_ops.init = nvhdmi_7x_init_2ch;
d0b1252d
TI		 2717 /* override the PCM rates, etc, as the codec doesn't give full list */
2718 spec = codec->spec;
2719 spec->pcm_playback.rates = SUPPORTED_RATES;
2720 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
2721 spec->pcm_playback.formats = SUPPORTED_FORMATS;
84eb01be
TI		 2722 return 0;
2723}
2724
53775b0d
TI		 2725static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
2726{
2727 struct hdmi_spec *spec = codec->spec;
2728 int err = simple_playback_build_pcms(codec);
bce0d2a8
TI		 2729 if (!err) {
2730 struct hda_pcm *info = get_pcm_rec(spec, 0);
2731 info->own_chmap = true;
2732 }
53775b0d
TI		 2733 return err;
2734}
2735
2736static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
2737{
2738 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2739 struct hda_pcm *info;
53775b0d
TI		 2740 struct snd_pcm_chmap *chmap;
2741 int err;
2742
2743 err = simple_playback_build_controls(codec);
2744 if (err < 0)
2745 return err;
2746
2747 /* add channel maps */
bce0d2a8
TI		 2748 info = get_pcm_rec(spec, 0);
2749 err = snd_pcm_add_chmap_ctls(info->pcm,
53775b0d
TI		 2750 SNDRV_PCM_STREAM_PLAYBACK,
2751 snd_pcm_alt_chmaps, 8, 0, &chmap);
2752 if (err < 0)
2753 return err;
2754 switch (codec->preset->id) {
2755 case 0x10de0002:
2756 case 0x10de0003:
2757 case 0x10de0005:
2758 case 0x10de0006:
2759 chmap->channel_mask = (1U << 2) | (1U << 8);
2760 break;
2761 case 0x10de0007:
2762 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
2763 }
2764 return 0;
2765}
2766
84eb01be
TI		 2767static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
2768{
2769 struct hdmi_spec *spec;
2770 int err = patch_nvhdmi_2ch(codec);
84eb01be
TI		 2771 if (err < 0)
2772 return err;
2773 spec = codec->spec;
2774 spec->multiout.max_channels = 8;
d0b1252d 2775 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
ceaa86ba 2776 codec->patch_ops.init = nvhdmi_7x_init_8ch;
53775b0d
TI		 2777 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
2778 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
1f348522
AP		 2779
2780 /* Initialize the audio infoframe channel mask and checksum to something
2781 * valid */
2782 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2783
84eb01be
TI		 2784 return 0;
2785}
2786
2787/*
5a613584 2788 * ATI/AMD-specific implementations
84eb01be
TI		 2789 */
2790
5a613584
AH		 2791#define is_amdhdmi_rev3_or_later(codec) \
2792 ((codec)->vendor_id == 0x1002aa01 && ((codec)->revision_id & 0xff00) >= 0x0300)
2793#define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
2794
2795/* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
2796#define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
2797#define ATI_VERB_SET_DOWNMIX_INFO 0x772
2798#define ATI_VERB_SET_MULTICHANNEL_01 0x777
2799#define ATI_VERB_SET_MULTICHANNEL_23 0x778
2800#define ATI_VERB_SET_MULTICHANNEL_45 0x779
2801#define ATI_VERB_SET_MULTICHANNEL_67 0x77a
2802#define ATI_VERB_SET_MULTICHANNEL_1 0x785
2803#define ATI_VERB_SET_MULTICHANNEL_3 0x786
2804#define ATI_VERB_SET_MULTICHANNEL_5 0x787
2805#define ATI_VERB_SET_MULTICHANNEL_7 0x788
2806#define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
2807#define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
2808#define ATI_VERB_GET_DOWNMIX_INFO 0xf72
2809#define ATI_VERB_GET_MULTICHANNEL_01 0xf77
2810#define ATI_VERB_GET_MULTICHANNEL_23 0xf78
2811#define ATI_VERB_GET_MULTICHANNEL_45 0xf79
2812#define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
2813#define ATI_VERB_GET_MULTICHANNEL_1 0xf85
2814#define ATI_VERB_GET_MULTICHANNEL_3 0xf86
2815#define ATI_VERB_GET_MULTICHANNEL_5 0xf87
2816#define ATI_VERB_GET_MULTICHANNEL_7 0xf88
2817#define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
2818
2819#define ATI_OUT_ENABLE 0x1
2820
2821#define ATI_MULTICHANNEL_MODE_PAIRED 0
2822#define ATI_MULTICHANNEL_MODE_SINGLE 1
2823
89250f84
AH		 2824static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
2825 unsigned char *buf, int *eld_size)
2826{
2827 /* call hda_eld.c ATI/AMD-specific function */
2828 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
2829 is_amdhdmi_rev3_or_later(codec));
2830}
2831
5a613584
AH		 2832static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
2833 int active_channels, int conn_type)
2834{
2835 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
2836}
2837
2838static int atihdmi_paired_swap_fc_lfe(int pos)
2839{
2840 /*
2841 * ATI/AMD have automatic FC/LFE swap built-in
2842 * when in pairwise mapping mode.
2843 */
2844
2845 switch (pos) {
2846 /* see channel_allocations[].speakers[] */
2847 case 2: return 3;
2848 case 3: return 2;
2849 default: break;
2850 }
2851
2852 return pos;
2853}
2854
2855static int atihdmi_paired_chmap_validate(int ca, int chs, unsigned char *map)
2856{
2857 struct cea_channel_speaker_allocation *cap;
2858 int i, j;
2859
2860 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
2861
2862 cap = &channel_allocations[get_channel_allocation_order(ca)];
2863 for (i = 0; i < chs; ++i) {
2864 int mask = to_spk_mask(map[i]);
2865 bool ok = false;
2866 bool companion_ok = false;
2867
2868 if (!mask)
2869 continue;
2870
2871 for (j = 0 + i % 2; j < 8; j += 2) {
2872 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
2873 if (cap->speakers[chan_idx] == mask) {
2874 /* channel is in a supported position */
2875 ok = true;
2876
2877 if (i % 2 == 0 && i + 1 < chs) {
2878 /* even channel, check the odd companion */
2879 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
2880 int comp_mask_req = to_spk_mask(map[i+1]);
2881 int comp_mask_act = cap->speakers[comp_chan_idx];
2882
2883 if (comp_mask_req == comp_mask_act)
2884 companion_ok = true;
2885 else
2886 return -EINVAL;
2887 }
2888 break;
2889 }
2890 }
2891
2892 if (!ok)
2893 return -EINVAL;
2894
2895 if (companion_ok)
2896 i++; /* companion channel already checked */
2897 }
2898
2899 return 0;
2900}
2901
2902static int atihdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
2903 int hdmi_slot, int stream_channel)
2904{
2905 int verb;
2906 int ati_channel_setup = 0;
2907
2908 if (hdmi_slot > 7)
2909 return -EINVAL;
2910
2911 if (!has_amd_full_remap_support(codec)) {
2912 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
2913
2914 /* In case this is an odd slot but without stream channel, do not
2915 * disable the slot since the corresponding even slot could have a
2916 * channel. In case neither have a channel, the slot pair will be
2917 * disabled when this function is called for the even slot. */
2918 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
2919 return 0;
2920
2921 hdmi_slot -= hdmi_slot % 2;
2922
2923 if (stream_channel != 0xf)
2924 stream_channel -= stream_channel % 2;
2925 }
2926
2927 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
2928
2929 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
2930
2931 if (stream_channel != 0xf)
2932 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
2933
2934 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
2935}
2936
2937static int atihdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
2938 int asp_slot)
2939{
2940 bool was_odd = false;
2941 int ati_asp_slot = asp_slot;
2942 int verb;
2943 int ati_channel_setup;
2944
2945 if (asp_slot > 7)
2946 return -EINVAL;
2947
2948 if (!has_amd_full_remap_support(codec)) {
2949 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
2950 if (ati_asp_slot % 2 != 0) {
2951 ati_asp_slot -= 1;
2952 was_odd = true;
2953 }
2954 }
2955
2956 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
2957
2958 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
2959
2960 if (!(ati_channel_setup & ATI_OUT_ENABLE))
2961 return 0xf;
2962
2963 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
2964}
84eb01be 2965
5a613584
AH		 2966static int atihdmi_paired_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
2967 int channels)
2968{
2969 int c;
2970
2971 /*
2972 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
2973 * we need to take that into account (a single channel may take 2
2974 * channel slots if we need to carry a silent channel next to it).
2975 * On Rev3+ AMD codecs this function is not used.
2976 */
2977 int chanpairs = 0;
2978
2979 /* We only produce even-numbered channel count TLVs */
2980 if ((channels % 2) != 0)
2981 return -1;
2982
2983 for (c = 0; c < 7; c += 2) {
2984 if (cap->speakers[c] || cap->speakers[c+1])
2985 chanpairs++;
2986 }
2987
2988 if (chanpairs * 2 != channels)
2989 return -1;
2990
2991 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
2992}
2993
2994static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
2995 unsigned int *chmap, int channels)
2996{
2997 /* produce paired maps for pre-rev3 ATI/AMD codecs */
2998 int count = 0;
2999 int c;
3000
3001 for (c = 7; c >= 0; c--) {
3002 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3003 int spk = cap->speakers[chan];
3004 if (!spk) {
3005 /* add N/A channel if the companion channel is occupied */
3006 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3007 chmap[count++] = SNDRV_CHMAP_NA;
3008
3009 continue;
3010 }
3011
3012 chmap[count++] = spk_to_chmap(spk);
3013 }
3014
3015 WARN_ON(count != channels);
3016}
3017
3018static int atihdmi_init(struct hda_codec *codec)
84eb01be
TI		 3019{
3020 struct hdmi_spec *spec = codec->spec;
5a613584 3021 int pin_idx, err;
84eb01be 3022
5a613584
AH		 3023 err = generic_hdmi_init(codec);
3024
3025 if (err)
84eb01be 3026 return err;
5a613584
AH		 3027
3028 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3029 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3030
3031 /* make sure downmix information in infoframe is zero */
3032 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3033
3034 /* enable channel-wise remap mode if supported */
3035 if (has_amd_full_remap_support(codec))
3036 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3037 ATI_VERB_SET_MULTICHANNEL_MODE,
3038 ATI_MULTICHANNEL_MODE_SINGLE);
84eb01be 3039 }
5a613584 3040
84eb01be
TI		 3041 return 0;
3042}
3043
84eb01be
TI		 3044static int patch_atihdmi(struct hda_codec *codec)
3045{
3046 struct hdmi_spec *spec;
5a613584
AH		 3047 struct hdmi_spec_per_cvt *per_cvt;
3048 int err, cvt_idx;
3049
3050 err = patch_generic_hdmi(codec);
3051
3052 if (err)
d0b1252d 3053 return err;
5a613584
AH		 3054
3055 codec->patch_ops.init = atihdmi_init;
3056
d0b1252d 3057 spec = codec->spec;
5a613584 3058
89250f84 3059 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
5a613584
AH		 3060 spec->ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
3061 spec->ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
3062 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
3063
3064 if (!has_amd_full_remap_support(codec)) {
3065 /* override to ATI/AMD-specific versions with pairwise mapping */
3066 spec->ops.chmap_cea_alloc_validate_get_type =
3067 atihdmi_paired_chmap_cea_alloc_validate_get_type;
3068 spec->ops.cea_alloc_to_tlv_chmap = atihdmi_paired_cea_alloc_to_tlv_chmap;
3069 spec->ops.chmap_validate = atihdmi_paired_chmap_validate;
3070 }
3071
3072 /* ATI/AMD converters do not advertise all of their capabilities */
3073 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
3074 per_cvt = get_cvt(spec, cvt_idx);
3075 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
3076 per_cvt->rates |= SUPPORTED_RATES;
3077 per_cvt->formats |= SUPPORTED_FORMATS;
3078 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
3079 }
3080
3081 spec->channels_max = max(spec->channels_max, 8u);
3082
84eb01be
TI		 3083 return 0;
3084}
3085
3de5ff88
AL		 3086/* VIA HDMI Implementation */
3087#define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
3088#define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
3089
3de5ff88
AL		 3090static int patch_via_hdmi(struct hda_codec *codec)
3091{
250e41ac 3092 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3de5ff88 3093}
84eb01be
TI		 3094
3095/*
3096 * patch entries
3097 */
fb79e1e0 3098static const struct hda_codec_preset snd_hda_preset_hdmi[] = {
84eb01be
TI		 3099{ .id = 0x1002793c, .name = "RS600 HDMI", .patch = patch_atihdmi },
3100{ .id = 0x10027919, .name = "RS600 HDMI", .patch = patch_atihdmi },
3101{ .id = 0x1002791a, .name = "RS690/780 HDMI", .patch = patch_atihdmi },
5a613584 3102{ .id = 0x1002aa01, .name = "R6xx HDMI", .patch = patch_atihdmi },
84eb01be
TI		 3103{ .id = 0x10951390, .name = "SiI1390 HDMI", .patch = patch_generic_hdmi },
3104{ .id = 0x10951392, .name = "SiI1392 HDMI", .patch = patch_generic_hdmi },
3105{ .id = 0x17e80047, .name = "Chrontel HDMI", .patch = patch_generic_hdmi },
3106{ .id = 0x10de0002, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3107{ .id = 0x10de0003, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3108{ .id = 0x10de0005, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3109{ .id = 0x10de0006, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3110{ .id = 0x10de0007, .name = "MCP79/7A HDMI", .patch = patch_nvhdmi_8ch_7x },
5d44f927
SW		 3111{ .id = 0x10de000a, .name = "GPU 0a HDMI/DP", .patch = patch_generic_hdmi },
3112{ .id = 0x10de000b, .name = "GPU 0b HDMI/DP", .patch = patch_generic_hdmi },
3113{ .id = 0x10de000c, .name = "MCP89 HDMI", .patch = patch_generic_hdmi },
3114{ .id = 0x10de000d, .name = "GPU 0d HDMI/DP", .patch = patch_generic_hdmi },
3115{ .id = 0x10de0010, .name = "GPU 10 HDMI/DP", .patch = patch_generic_hdmi },
3116{ .id = 0x10de0011, .name = "GPU 11 HDMI/DP", .patch = patch_generic_hdmi },
3117{ .id = 0x10de0012, .name = "GPU 12 HDMI/DP", .patch = patch_generic_hdmi },
3118{ .id = 0x10de0013, .name = "GPU 13 HDMI/DP", .patch = patch_generic_hdmi },
3119{ .id = 0x10de0014, .name = "GPU 14 HDMI/DP", .patch = patch_generic_hdmi },
3120{ .id = 0x10de0015, .name = "GPU 15 HDMI/DP", .patch = patch_generic_hdmi },
3121{ .id = 0x10de0016, .name = "GPU 16 HDMI/DP", .patch = patch_generic_hdmi },
c8900a0f 3122/* 17 is known to be absent */
5d44f927
SW		 3123{ .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_generic_hdmi },
3124{ .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_generic_hdmi },
3125{ .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_generic_hdmi },
3126{ .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_generic_hdmi },
3127{ .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_generic_hdmi },
3128{ .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_generic_hdmi },
3129{ .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_generic_hdmi },
3130{ .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_generic_hdmi },
3131{ .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_generic_hdmi },
3132{ .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_generic_hdmi },
7ae48b56 3133{ .id = 0x10de0051, .name = "GPU 51 HDMI/DP", .patch = patch_generic_hdmi },
d52392b1 3134{ .id = 0x10de0060, .name = "GPU 60 HDMI/DP", .patch = patch_generic_hdmi },
84eb01be
TI		 3135{ .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch },
3136{ .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch },
3de5ff88
AL		 3137{ .id = 0x11069f80, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
3138{ .id = 0x11069f81, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
3139{ .id = 0x11069f84, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
3140{ .id = 0x11069f85, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
84eb01be
TI		 3141{ .id = 0x80860054, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
3142{ .id = 0x80862801, .name = "Bearlake HDMI", .patch = patch_generic_hdmi },
3143{ .id = 0x80862802, .name = "Cantiga HDMI", .patch = patch_generic_hdmi },
3144{ .id = 0x80862803, .name = "Eaglelake HDMI", .patch = patch_generic_hdmi },
3145{ .id = 0x80862804, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
3146{ .id = 0x80862805, .name = "CougarPoint HDMI", .patch = patch_generic_hdmi },
591e610d 3147{ .id = 0x80862806, .name = "PantherPoint HDMI", .patch = patch_generic_hdmi },
1c76684d 3148{ .id = 0x80862807, .name = "Haswell HDMI", .patch = patch_generic_hdmi },
6edc59e6 3149{ .id = 0x80862880, .name = "CedarTrail HDMI", .patch = patch_generic_hdmi },
cc1a95d9 3150{ .id = 0x80862882, .name = "Valleyview2 HDMI", .patch = patch_generic_hdmi },
84eb01be
TI		 3151{ .id = 0x808629fb, .name = "Crestline HDMI", .patch = patch_generic_hdmi },
3152{} /* terminator */
3153};
3154
3155MODULE_ALIAS("snd-hda-codec-id:1002793c");
3156MODULE_ALIAS("snd-hda-codec-id:10027919");
3157MODULE_ALIAS("snd-hda-codec-id:1002791a");
3158MODULE_ALIAS("snd-hda-codec-id:1002aa01");
3159MODULE_ALIAS("snd-hda-codec-id:10951390");
3160MODULE_ALIAS("snd-hda-codec-id:10951392");
3161MODULE_ALIAS("snd-hda-codec-id:10de0002");
3162MODULE_ALIAS("snd-hda-codec-id:10de0003");
3163MODULE_ALIAS("snd-hda-codec-id:10de0005");
3164MODULE_ALIAS("snd-hda-codec-id:10de0006");
3165MODULE_ALIAS("snd-hda-codec-id:10de0007");
3166MODULE_ALIAS("snd-hda-codec-id:10de000a");
3167MODULE_ALIAS("snd-hda-codec-id:10de000b");
3168MODULE_ALIAS("snd-hda-codec-id:10de000c");
3169MODULE_ALIAS("snd-hda-codec-id:10de000d");
3170MODULE_ALIAS("snd-hda-codec-id:10de0010");
3171MODULE_ALIAS("snd-hda-codec-id:10de0011");
3172MODULE_ALIAS("snd-hda-codec-id:10de0012");
3173MODULE_ALIAS("snd-hda-codec-id:10de0013");
3174MODULE_ALIAS("snd-hda-codec-id:10de0014");
c8900a0f
RS		 3175MODULE_ALIAS("snd-hda-codec-id:10de0015");
3176MODULE_ALIAS("snd-hda-codec-id:10de0016");
84eb01be
TI		 3177MODULE_ALIAS("snd-hda-codec-id:10de0018");
3178MODULE_ALIAS("snd-hda-codec-id:10de0019");
3179MODULE_ALIAS("snd-hda-codec-id:10de001a");
3180MODULE_ALIAS("snd-hda-codec-id:10de001b");
3181MODULE_ALIAS("snd-hda-codec-id:10de001c");
3182MODULE_ALIAS("snd-hda-codec-id:10de0040");
3183MODULE_ALIAS("snd-hda-codec-id:10de0041");
3184MODULE_ALIAS("snd-hda-codec-id:10de0042");
3185MODULE_ALIAS("snd-hda-codec-id:10de0043");
3186MODULE_ALIAS("snd-hda-codec-id:10de0044");
7ae48b56 3187MODULE_ALIAS("snd-hda-codec-id:10de0051");
d52392b1 3188MODULE_ALIAS("snd-hda-codec-id:10de0060");
84eb01be
TI		 3189MODULE_ALIAS("snd-hda-codec-id:10de0067");
3190MODULE_ALIAS("snd-hda-codec-id:10de8001");
3de5ff88
AL		 3191MODULE_ALIAS("snd-hda-codec-id:11069f80");
3192MODULE_ALIAS("snd-hda-codec-id:11069f81");
3193MODULE_ALIAS("snd-hda-codec-id:11069f84");
3194MODULE_ALIAS("snd-hda-codec-id:11069f85");
84eb01be
TI		 3195MODULE_ALIAS("snd-hda-codec-id:17e80047");
3196MODULE_ALIAS("snd-hda-codec-id:80860054");
3197MODULE_ALIAS("snd-hda-codec-id:80862801");
3198MODULE_ALIAS("snd-hda-codec-id:80862802");
3199MODULE_ALIAS("snd-hda-codec-id:80862803");
3200MODULE_ALIAS("snd-hda-codec-id:80862804");
3201MODULE_ALIAS("snd-hda-codec-id:80862805");
591e610d 3202MODULE_ALIAS("snd-hda-codec-id:80862806");
1c76684d 3203MODULE_ALIAS("snd-hda-codec-id:80862807");
6edc59e6 3204MODULE_ALIAS("snd-hda-codec-id:80862880");
cc1a95d9 3205MODULE_ALIAS("snd-hda-codec-id:80862882");
84eb01be
TI		 3206MODULE_ALIAS("snd-hda-codec-id:808629fb");
3207
3208MODULE_LICENSE("GPL");
3209MODULE_DESCRIPTION("HDMI HD-audio codec");
3210MODULE_ALIAS("snd-hda-codec-intelhdmi");
3211MODULE_ALIAS("snd-hda-codec-nvhdmi");
3212MODULE_ALIAS("snd-hda-codec-atihdmi");
3213
3214static struct hda_codec_preset_list intel_list = {
3215 .preset = snd_hda_preset_hdmi,
3216 .owner = THIS_MODULE,
3217};
3218
3219static int __init patch_hdmi_init(void)
3220{
3221 return snd_hda_add_codec_preset(&intel_list);
3222}
3223
3224static void __exit patch_hdmi_exit(void)
3225{
3226 snd_hda_delete_codec_preset(&intel_list);
3227}
3228
3229module_init(patch_hdmi_init)
3230module_exit(patch_hdmi_exit)
Michael's Linux tree.