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Merge tag 'net-6.0-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
[people/ms/linux.git] / sound / soc / codecs / nau8821.c
CommitLineData
aab1ad11
SL		 1// SPDX-License-Identifier: GPL-2.0-only
2//
3// nau8821.c -- Nuvoton NAU88L21 audio codec driver
4//
5// Copyright 2021 Nuvoton Technology Corp.
6// Author: John Hsu <kchsu0@nuvoton.com>
7// Co-author: Seven Lee <wtli@nuvoton.com>
8//
9
10#include <linux/acpi.h>
11#include <linux/clk.h>
12#include <linux/delay.h>
13#include <linux/init.h>
14#include <linux/i2c.h>
15#include <linux/module.h>
16#include <linux/math64.h>
17#include <linux/regmap.h>
18#include <linux/slab.h>
19#include <sound/core.h>
20#include <sound/initval.h>
21#include <sound/jack.h>
22#include <sound/pcm.h>
23#include <sound/pcm_params.h>
24#include <sound/soc.h>
25#include <sound/tlv.h>
26#include "nau8821.h"
27
28#define NAU_FREF_MAX 13500000
29#define NAU_FVCO_MAX 100000000
30#define NAU_FVCO_MIN 90000000
31
2551b6e8
SL		 32#define NAU8821_BUTTON SND_JACK_BTN_0
33
aab1ad11
SL		 34/* the maximum frequency of CLK_ADC and CLK_DAC */
35#define CLK_DA_AD_MAX 6144000
36
37static int nau8821_configure_sysclk(struct nau8821 *nau8821,
38 int clk_id, unsigned int freq);
0cf470c0 39static bool nau8821_is_jack_inserted(struct regmap *regmap);
aab1ad11
SL		 40
41struct nau8821_fll {
42 int mclk_src;
43 int ratio;
44 int fll_frac;
45 int fll_int;
46 int clk_ref_div;
47};
48
49struct nau8821_fll_attr {
50 unsigned int param;
51 unsigned int val;
52};
53
54/* scaling for mclk from sysclk_src output */
55static const struct nau8821_fll_attr mclk_src_scaling[] = {
56 { 1, 0x0 },
57 { 2, 0x2 },
58 { 4, 0x3 },
59 { 8, 0x4 },
60 { 16, 0x5 },
61 { 32, 0x6 },
62 { 3, 0x7 },
63 { 6, 0xa },
64 { 12, 0xb },
65 { 24, 0xc },
66 { 48, 0xd },
67 { 96, 0xe },
68 { 5, 0xf },
69};
70
71/* ratio for input clk freq */
72static const struct nau8821_fll_attr fll_ratio[] = {
73 { 512000, 0x01 },
74 { 256000, 0x02 },
75 { 128000, 0x04 },
76 { 64000, 0x08 },
77 { 32000, 0x10 },
78 { 8000, 0x20 },
79 { 4000, 0x40 },
80};
81
82static const struct nau8821_fll_attr fll_pre_scalar[] = {
83 { 0, 0x0 },
84 { 1, 0x1 },
85 { 2, 0x2 },
86 { 3, 0x3 },
87};
88
89/* over sampling rate */
90struct nau8821_osr_attr {
91 unsigned int osr;
92 unsigned int clk_src;
93};
94
95static const struct nau8821_osr_attr osr_dac_sel[] = {
96 { 64, 2 }, /* OSR 64, SRC 1/4 */
97 { 256, 0 }, /* OSR 256, SRC 1 */
98 { 128, 1 }, /* OSR 128, SRC 1/2 */
99 { 0, 0 },
100 { 32, 3 }, /* OSR 32, SRC 1/8 */
101};
102
103static const struct nau8821_osr_attr osr_adc_sel[] = {
104 { 32, 3 }, /* OSR 32, SRC 1/8 */
105 { 64, 2 }, /* OSR 64, SRC 1/4 */
106 { 128, 1 }, /* OSR 128, SRC 1/2 */
107 { 256, 0 }, /* OSR 256, SRC 1 */
108};
109
110struct nau8821_dmic_speed {
111 unsigned int param;
112 unsigned int val;
113};
114
115static const struct nau8821_dmic_speed dmic_speed_sel[] = {
116 { 0, 0x0 }, /*SPEED 1, SRC 1 */
117 { 1, 0x1 }, /*SPEED 2, SRC 1/2 */
118 { 2, 0x2 }, /*SPEED 4, SRC 1/4 */
119 { 3, 0x3 }, /*SPEED 8, SRC 1/8 */
120};
121
122static const struct reg_default nau8821_reg_defaults[] = {
123 { NAU8821_R01_ENA_CTRL, 0x00ff },
124 { NAU8821_R03_CLK_DIVIDER, 0x0050 },
125 { NAU8821_R04_FLL1, 0x0 },
126 { NAU8821_R05_FLL2, 0x00bc },
127 { NAU8821_R06_FLL3, 0x0008 },
128 { NAU8821_R07_FLL4, 0x0010 },
129 { NAU8821_R08_FLL5, 0x4000 },
130 { NAU8821_R09_FLL6, 0x6900 },
131 { NAU8821_R0A_FLL7, 0x0031 },
132 { NAU8821_R0B_FLL8, 0x26e9 },
133 { NAU8821_R0D_JACK_DET_CTRL, 0x0 },
134 { NAU8821_R0F_INTERRUPT_MASK, 0x0 },
135 { NAU8821_R12_INTERRUPT_DIS_CTRL, 0xffff },
136 { NAU8821_R13_DMIC_CTRL, 0x0 },
137 { NAU8821_R1A_GPIO12_CTRL, 0x0 },
138 { NAU8821_R1B_TDM_CTRL, 0x0 },
139 { NAU8821_R1C_I2S_PCM_CTRL1, 0x000a },
140 { NAU8821_R1D_I2S_PCM_CTRL2, 0x8010 },
141 { NAU8821_R1E_LEFT_TIME_SLOT, 0x0 },
142 { NAU8821_R1F_RIGHT_TIME_SLOT, 0x0 },
143 { NAU8821_R21_BIQ0_COF1, 0x0 },
144 { NAU8821_R22_BIQ0_COF2, 0x0 },
145 { NAU8821_R23_BIQ0_COF3, 0x0 },
146 { NAU8821_R24_BIQ0_COF4, 0x0 },
147 { NAU8821_R25_BIQ0_COF5, 0x0 },
148 { NAU8821_R26_BIQ0_COF6, 0x0 },
149 { NAU8821_R27_BIQ0_COF7, 0x0 },
150 { NAU8821_R28_BIQ0_COF8, 0x0 },
151 { NAU8821_R29_BIQ0_COF9, 0x0 },
152 { NAU8821_R2A_BIQ0_COF10, 0x0 },
153 { NAU8821_R2B_ADC_RATE, 0x0002 },
154 { NAU8821_R2C_DAC_CTRL1, 0x0082 },
155 { NAU8821_R2D_DAC_CTRL2, 0x0 },
156 { NAU8821_R2F_DAC_DGAIN_CTRL, 0x0 },
157 { NAU8821_R30_ADC_DGAIN_CTRL, 0x0 },
158 { NAU8821_R31_MUTE_CTRL, 0x0 },
159 { NAU8821_R32_HSVOL_CTRL, 0x0 },
160 { NAU8821_R34_DACR_CTRL, 0xcfcf },
161 { NAU8821_R35_ADC_DGAIN_CTRL1, 0xcfcf },
162 { NAU8821_R36_ADC_DRC_KNEE_IP12, 0x1486 },
163 { NAU8821_R37_ADC_DRC_KNEE_IP34, 0x0f12 },
164 { NAU8821_R38_ADC_DRC_SLOPES, 0x25ff },
165 { NAU8821_R39_ADC_DRC_ATKDCY, 0x3457 },
166 { NAU8821_R3A_DAC_DRC_KNEE_IP12, 0x1486 },
167 { NAU8821_R3B_DAC_DRC_KNEE_IP34, 0x0f12 },
168 { NAU8821_R3C_DAC_DRC_SLOPES, 0x25f9 },
169 { NAU8821_R3D_DAC_DRC_ATKDCY, 0x3457 },
170 { NAU8821_R41_BIQ1_COF1, 0x0 },
171 { NAU8821_R42_BIQ1_COF2, 0x0 },
172 { NAU8821_R43_BIQ1_COF3, 0x0 },
173 { NAU8821_R44_BIQ1_COF4, 0x0 },
174 { NAU8821_R45_BIQ1_COF5, 0x0 },
175 { NAU8821_R46_BIQ1_COF6, 0x0 },
176 { NAU8821_R47_BIQ1_COF7, 0x0 },
177 { NAU8821_R48_BIQ1_COF8, 0x0 },
178 { NAU8821_R49_BIQ1_COF9, 0x0 },
179 { NAU8821_R4A_BIQ1_COF10, 0x0 },
180 { NAU8821_R4B_CLASSG_CTRL, 0x0 },
181 { NAU8821_R4C_IMM_MODE_CTRL, 0x0 },
182 { NAU8821_R4D_IMM_RMS_L, 0x0 },
183 { NAU8821_R53_OTPDOUT_1, 0xaad8 },
184 { NAU8821_R54_OTPDOUT_2, 0x0002 },
185 { NAU8821_R55_MISC_CTRL, 0x0 },
186 { NAU8821_R66_BIAS_ADJ, 0x0 },
187 { NAU8821_R68_TRIM_SETTINGS, 0x0 },
188 { NAU8821_R69_ANALOG_CONTROL_1, 0x0 },
189 { NAU8821_R6A_ANALOG_CONTROL_2, 0x0 },
190 { NAU8821_R6B_PGA_MUTE, 0x0 },
191 { NAU8821_R71_ANALOG_ADC_1, 0x0011 },
192 { NAU8821_R72_ANALOG_ADC_2, 0x0020 },
193 { NAU8821_R73_RDAC, 0x0008 },
194 { NAU8821_R74_MIC_BIAS, 0x0006 },
195 { NAU8821_R76_BOOST, 0x0 },
196 { NAU8821_R77_FEPGA, 0x0 },
197 { NAU8821_R7E_PGA_GAIN, 0x0 },
198 { NAU8821_R7F_POWER_UP_CONTROL, 0x0 },
199 { NAU8821_R80_CHARGE_PUMP, 0x0 },
200};
201
202static bool nau8821_readable_reg(struct device *dev, unsigned int reg)
203{
204 switch (reg) {
205 case NAU8821_R00_RESET ... NAU8821_R01_ENA_CTRL:
206 case NAU8821_R03_CLK_DIVIDER ... NAU8821_R0B_FLL8:
207 case NAU8821_R0D_JACK_DET_CTRL:
208 case NAU8821_R0F_INTERRUPT_MASK ... NAU8821_R13_DMIC_CTRL:
209 case NAU8821_R1A_GPIO12_CTRL ... NAU8821_R1F_RIGHT_TIME_SLOT:
210 case NAU8821_R21_BIQ0_COF1 ... NAU8821_R2D_DAC_CTRL2:
211 case NAU8821_R2F_DAC_DGAIN_CTRL ... NAU8821_R32_HSVOL_CTRL:
212 case NAU8821_R34_DACR_CTRL ... NAU8821_R3D_DAC_DRC_ATKDCY:
213 case NAU8821_R41_BIQ1_COF1 ... NAU8821_R4F_FUSE_CTRL3:
214 case NAU8821_R51_FUSE_CTRL1:
215 case NAU8821_R53_OTPDOUT_1 ... NAU8821_R55_MISC_CTRL:
216 case NAU8821_R58_I2C_DEVICE_ID ... NAU8821_R5A_SOFTWARE_RST:
217 case NAU8821_R66_BIAS_ADJ:
218 case NAU8821_R68_TRIM_SETTINGS ... NAU8821_R6B_PGA_MUTE:
219 case NAU8821_R71_ANALOG_ADC_1 ... NAU8821_R74_MIC_BIAS:
220 case NAU8821_R76_BOOST ... NAU8821_R77_FEPGA:
221 case NAU8821_R7E_PGA_GAIN ... NAU8821_R82_GENERAL_STATUS:
222 return true;
223 default:
224 return false;
225 }
226}
227
228static bool nau8821_writeable_reg(struct device *dev, unsigned int reg)
229{
230 switch (reg) {
231 case NAU8821_R00_RESET ... NAU8821_R01_ENA_CTRL:
232 case NAU8821_R03_CLK_DIVIDER ... NAU8821_R0B_FLL8:
233 case NAU8821_R0D_JACK_DET_CTRL:
234 case NAU8821_R0F_INTERRUPT_MASK:
235 case NAU8821_R11_INT_CLR_KEY_STATUS ... NAU8821_R13_DMIC_CTRL:
236 case NAU8821_R1A_GPIO12_CTRL ... NAU8821_R1F_RIGHT_TIME_SLOT:
237 case NAU8821_R21_BIQ0_COF1 ... NAU8821_R2D_DAC_CTRL2:
238 case NAU8821_R2F_DAC_DGAIN_CTRL ... NAU8821_R32_HSVOL_CTRL:
239 case NAU8821_R34_DACR_CTRL ... NAU8821_R3D_DAC_DRC_ATKDCY:
240 case NAU8821_R41_BIQ1_COF1 ... NAU8821_R4C_IMM_MODE_CTRL:
241 case NAU8821_R4E_FUSE_CTRL2 ... NAU8821_R4F_FUSE_CTRL3:
242 case NAU8821_R51_FUSE_CTRL1:
243 case NAU8821_R55_MISC_CTRL:
244 case NAU8821_R5A_SOFTWARE_RST:
245 case NAU8821_R66_BIAS_ADJ:
246 case NAU8821_R68_TRIM_SETTINGS ... NAU8821_R6B_PGA_MUTE:
247 case NAU8821_R71_ANALOG_ADC_1 ... NAU8821_R74_MIC_BIAS:
248 case NAU8821_R76_BOOST ... NAU8821_R77_FEPGA:
249 case NAU8821_R7E_PGA_GAIN ... NAU8821_R80_CHARGE_PUMP:
250 return true;
251 default:
252 return false;
253 }
254}
255
256static bool nau8821_volatile_reg(struct device *dev, unsigned int reg)
257{
258 switch (reg) {
259 case NAU8821_R00_RESET:
260 case NAU8821_R10_IRQ_STATUS ... NAU8821_R11_INT_CLR_KEY_STATUS:
261 case NAU8821_R21_BIQ0_COF1 ... NAU8821_R2A_BIQ0_COF10:
262 case NAU8821_R41_BIQ1_COF1 ... NAU8821_R4A_BIQ1_COF10:
263 case NAU8821_R4D_IMM_RMS_L:
264 case NAU8821_R53_OTPDOUT_1 ... NAU8821_R54_OTPDOUT_2:
265 case NAU8821_R58_I2C_DEVICE_ID ... NAU8821_R5A_SOFTWARE_RST:
266 case NAU8821_R81_CHARGE_PUMP_INPUT_READ ... NAU8821_R82_GENERAL_STATUS:
267 return true;
268 default:
269 return false;
270 }
271}
272
273static int nau8821_biq_coeff_get(struct snd_kcontrol *kcontrol,
274 struct snd_ctl_elem_value *ucontrol)
275{
276 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
277 struct soc_bytes_ext *params = (void *)kcontrol->private_value;
278
279 if (!component->regmap)
280 return -EINVAL;
281
282 regmap_raw_read(component->regmap, NAU8821_R21_BIQ0_COF1,
283 ucontrol->value.bytes.data, params->max);
284
285 return 0;
286}
287
288static int nau8821_biq_coeff_put(struct snd_kcontrol *kcontrol,
289 struct snd_ctl_elem_value *ucontrol)
290{
291 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
292 struct soc_bytes_ext *params = (void *)kcontrol->private_value;
293 void *data;
294
295 if (!component->regmap)
296 return -EINVAL;
297
298 data = kmemdup(ucontrol->value.bytes.data,
299 params->max, GFP_KERNEL | GFP_DMA);
300 if (!data)
301 return -ENOMEM;
302
303 regmap_raw_write(component->regmap, NAU8821_R21_BIQ0_COF1,
304 data, params->max);
305
306 kfree(data);
307
308 return 0;
309}
310
311static const char * const nau8821_adc_decimation[] = {
312 "32", "64", "128", "256" };
313
314static const struct soc_enum nau8821_adc_decimation_enum =
315 SOC_ENUM_SINGLE(NAU8821_R2B_ADC_RATE, NAU8821_ADC_SYNC_DOWN_SFT,
316 ARRAY_SIZE(nau8821_adc_decimation), nau8821_adc_decimation);
317
318static const char * const nau8821_dac_oversampl[] = {
319 "64", "256", "128", "", "32" };
320
321static const struct soc_enum nau8821_dac_oversampl_enum =
322 SOC_ENUM_SINGLE(NAU8821_R2C_DAC_CTRL1, NAU8821_DAC_OVERSAMPLE_SFT,
323 ARRAY_SIZE(nau8821_dac_oversampl), nau8821_dac_oversampl);
324
325static const DECLARE_TLV_DB_MINMAX_MUTE(adc_vol_tlv, -6600, 2400);
326static const DECLARE_TLV_DB_MINMAX_MUTE(sidetone_vol_tlv, -4200, 0);
327static const DECLARE_TLV_DB_MINMAX(hp_vol_tlv, -900, 0);
328static const DECLARE_TLV_DB_SCALE(playback_vol_tlv, -6600, 50, 1);
329static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600);
330static const DECLARE_TLV_DB_MINMAX_MUTE(crosstalk_vol_tlv, -7000, 2400);
331
332static const struct snd_kcontrol_new nau8821_controls[] = {
333 SOC_DOUBLE_TLV("Mic Volume", NAU8821_R35_ADC_DGAIN_CTRL1,
334 NAU8821_ADCL_CH_VOL_SFT, NAU8821_ADCR_CH_VOL_SFT,
335 0xff, 0, adc_vol_tlv),
336 SOC_DOUBLE_TLV("Headphone Bypass Volume", NAU8821_R30_ADC_DGAIN_CTRL,
337 12, 8, 0x0f, 0, sidetone_vol_tlv),
338 SOC_DOUBLE_TLV("Headphone Volume", NAU8821_R32_HSVOL_CTRL,
339 NAU8821_HPL_VOL_SFT, NAU8821_HPR_VOL_SFT, 0x3, 1, hp_vol_tlv),
340 SOC_DOUBLE_TLV("Digital Playback Volume", NAU8821_R34_DACR_CTRL,
341 NAU8821_DACL_CH_VOL_SFT, NAU8821_DACR_CH_VOL_SFT,
342 0xcf, 0, playback_vol_tlv),
343 SOC_DOUBLE_TLV("Frontend PGA Volume", NAU8821_R7E_PGA_GAIN,
344 NAU8821_PGA_GAIN_L_SFT, NAU8821_PGA_GAIN_R_SFT,
345 37, 0, fepga_gain_tlv),
346 SOC_DOUBLE_TLV("Headphone Crosstalk Volume",
347 NAU8821_R2F_DAC_DGAIN_CTRL,
348 0, 8, 0xff, 0, crosstalk_vol_tlv),
349
350 SOC_ENUM("ADC Decimation Rate", nau8821_adc_decimation_enum),
351 SOC_ENUM("DAC Oversampling Rate", nau8821_dac_oversampl_enum),
352 SND_SOC_BYTES_EXT("BIQ Coefficients", 20,
353 nau8821_biq_coeff_get, nau8821_biq_coeff_put),
354 SOC_SINGLE("ADC Phase Switch", NAU8821_R1B_TDM_CTRL,
355 NAU8821_ADCPHS_SFT, 1, 0),
356};
357
358static const struct snd_kcontrol_new nau8821_dmic_mode_switch =
359 SOC_DAPM_SINGLE("Switch", NAU8821_R13_DMIC_CTRL,
360 NAU8821_DMIC_EN_SFT, 1, 0);
361
362static int dmic_clock_control(struct snd_soc_dapm_widget *w,
363 struct snd_kcontrol *k, int event)
364{
365 struct snd_soc_component *component =
366 snd_soc_dapm_to_component(w->dapm);
367 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
368 int i, speed_selection = -1, clk_adc_src, clk_adc;
369 unsigned int clk_divider_r03;
370
371 /* The DMIC clock is gotten from adc clock divided by
372 * CLK_DMIC_SRC (1, 2, 4, 8). The clock has to be equal or
373 * less than nau8821->dmic_clk_threshold.
374 */
375 regmap_read(nau8821->regmap, NAU8821_R03_CLK_DIVIDER,
376 &clk_divider_r03);
377 clk_adc_src = (clk_divider_r03 & NAU8821_CLK_ADC_SRC_MASK)
378 >> NAU8821_CLK_ADC_SRC_SFT;
379 clk_adc = (nau8821->fs * 256) >> clk_adc_src;
380
381 for (i = 0 ; i < 4 ; i++)
382 if ((clk_adc >> dmic_speed_sel[i].param) <=
383 nau8821->dmic_clk_threshold) {
384 speed_selection = dmic_speed_sel[i].val;
385 break;
386 }
46ae0b3f 387 if (i == 4)
aab1ad11
SL		 388 return -EINVAL;
389
390 dev_dbg(nau8821->dev,
391 "clk_adc=%d, dmic_clk_threshold = %d, param=%d, val = %d\n",
392 clk_adc, nau8821->dmic_clk_threshold,
393 dmic_speed_sel[i].param, dmic_speed_sel[i].val);
394 regmap_update_bits(nau8821->regmap, NAU8821_R13_DMIC_CTRL,
395 NAU8821_DMIC_SRC_MASK,
396 (speed_selection << NAU8821_DMIC_SRC_SFT));
397
398 return 0;
399}
400
401static int nau8821_left_adc_event(struct snd_soc_dapm_widget *w,
402 struct snd_kcontrol *kcontrol, int event)
403{
404 struct snd_soc_component *component =
405 snd_soc_dapm_to_component(w->dapm);
406 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
407
408 switch (event) {
409 case SND_SOC_DAPM_POST_PMU:
410 msleep(125);
411 regmap_update_bits(nau8821->regmap, NAU8821_R01_ENA_CTRL,
412 NAU8821_EN_ADCL, NAU8821_EN_ADCL);
413 break;
414 case SND_SOC_DAPM_POST_PMD:
415 regmap_update_bits(nau8821->regmap,
416 NAU8821_R01_ENA_CTRL, NAU8821_EN_ADCL, 0);
417 break;
418 default:
419 return -EINVAL;
420 }
421
422 return 0;
423}
424
425static int nau8821_right_adc_event(struct snd_soc_dapm_widget *w,
426 struct snd_kcontrol *kcontrol, int event)
427{
428 struct snd_soc_component *component =
429 snd_soc_dapm_to_component(w->dapm);
430 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
431
432 switch (event) {
433 case SND_SOC_DAPM_POST_PMU:
434 msleep(125);
435 regmap_update_bits(nau8821->regmap, NAU8821_R01_ENA_CTRL,
436 NAU8821_EN_ADCR, NAU8821_EN_ADCR);
437 break;
438 case SND_SOC_DAPM_POST_PMD:
439 regmap_update_bits(nau8821->regmap,
440 NAU8821_R01_ENA_CTRL, NAU8821_EN_ADCR, 0);
441 break;
442 default:
443 return -EINVAL;
444 }
445
446 return 0;
447}
448
449static int nau8821_pump_event(struct snd_soc_dapm_widget *w,
450 struct snd_kcontrol *kcontrol, int event)
451{
452 struct snd_soc_component *component =
453 snd_soc_dapm_to_component(w->dapm);
454 struct nau8821 *nau8821 =
455 snd_soc_component_get_drvdata(component);
456
457 switch (event) {
458 case SND_SOC_DAPM_POST_PMU:
459 /* Prevent startup click by letting charge pump to ramp up */
460 msleep(20);
461 regmap_update_bits(nau8821->regmap, NAU8821_R80_CHARGE_PUMP,
462 NAU8821_JAMNODCLOW, NAU8821_JAMNODCLOW);
463 break;
464 case SND_SOC_DAPM_PRE_PMD:
465 regmap_update_bits(nau8821->regmap, NAU8821_R80_CHARGE_PUMP,
466 NAU8821_JAMNODCLOW, 0);
467 break;
468 default:
469 return -EINVAL;
470 }
471
472 return 0;
473}
474
475static int nau8821_output_dac_event(struct snd_soc_dapm_widget *w,
476 struct snd_kcontrol *kcontrol, int event)
477{
478 struct snd_soc_component *component =
479 snd_soc_dapm_to_component(w->dapm);
480 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
481
482 switch (event) {
483 case SND_SOC_DAPM_PRE_PMU:
484 /* Disables the TESTDAC to let DAC signal pass through. */
485 regmap_update_bits(nau8821->regmap, NAU8821_R66_BIAS_ADJ,
486 NAU8821_BIAS_TESTDAC_EN, 0);
487 break;
488 case SND_SOC_DAPM_POST_PMD:
489 regmap_update_bits(nau8821->regmap, NAU8821_R66_BIAS_ADJ,
490 NAU8821_BIAS_TESTDAC_EN, NAU8821_BIAS_TESTDAC_EN);
491 break;
492 default:
493 return -EINVAL;
494 }
495
496 return 0;
497}
498
0cf470c0
WL		 499static int system_clock_control(struct snd_soc_dapm_widget *w,
500 struct snd_kcontrol *k, int event)
501{
502 struct snd_soc_component *component =
503 snd_soc_dapm_to_component(w->dapm);
504 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
505
506 if (SND_SOC_DAPM_EVENT_OFF(event)) {
507 dev_dbg(nau8821->dev, "system clock control : POWER OFF\n");
508 /* Set clock source to disable or internal clock before the
509 * playback or capture end. Codec needs clock for Jack
510 * detection and button press if jack inserted; otherwise,
511 * the clock should be closed.
512 */
513 if (nau8821_is_jack_inserted(nau8821->regmap)) {
514 nau8821_configure_sysclk(nau8821,
515 NAU8821_CLK_INTERNAL, 0);
516 } else {
517 nau8821_configure_sysclk(nau8821, NAU8821_CLK_DIS, 0);
518 }
519 }
520 return 0;
521}
522
aab1ad11 523static const struct snd_soc_dapm_widget nau8821_dapm_widgets[] = {
0cf470c0
WL		 524 SND_SOC_DAPM_SUPPLY("System Clock", SND_SOC_NOPM, 0, 0,
525 system_clock_control, SND_SOC_DAPM_POST_PMD),
aab1ad11
SL		 526 SND_SOC_DAPM_SUPPLY("MICBIAS", NAU8821_R74_MIC_BIAS,
527 NAU8821_MICBIAS_POWERUP_SFT, 0, NULL, 0),
528 SND_SOC_DAPM_SUPPLY("DMIC Clock", SND_SOC_NOPM, 0, 0,
529 dmic_clock_control, SND_SOC_DAPM_POST_PMU),
530 SND_SOC_DAPM_ADC("ADCL Power", NULL, NAU8821_R72_ANALOG_ADC_2,
531 NAU8821_POWERUP_ADCL_SFT, 0),
532 SND_SOC_DAPM_ADC("ADCR Power", NULL, NAU8821_R72_ANALOG_ADC_2,
533 NAU8821_POWERUP_ADCR_SFT, 0),
534 SND_SOC_DAPM_PGA_S("Frontend PGA L", 1, NAU8821_R7F_POWER_UP_CONTROL,
535 NAU8821_PUP_PGA_L_SFT, 0, NULL, 0),
536 SND_SOC_DAPM_PGA_S("Frontend PGA R", 1, NAU8821_R7F_POWER_UP_CONTROL,
537 NAU8821_PUP_PGA_R_SFT, 0, NULL, 0),
538 SND_SOC_DAPM_PGA_S("ADCL Digital path", 0, NAU8821_R01_ENA_CTRL,
539 NAU8821_EN_ADCL_SFT, 0, nau8821_left_adc_event,
540 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
541 SND_SOC_DAPM_PGA_S("ADCR Digital path", 0, NAU8821_R01_ENA_CTRL,
542 NAU8821_EN_ADCR_SFT, 0, nau8821_right_adc_event,
543 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
544 SND_SOC_DAPM_SWITCH("DMIC Enable", SND_SOC_NOPM,
545 0, 0, &nau8821_dmic_mode_switch),
546 SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, NAU8821_R1D_I2S_PCM_CTRL2,
547 NAU8821_I2S_TRISTATE_SFT, 1),
548 SND_SOC_DAPM_AIF_IN("AIFRX", "Playback", 0, SND_SOC_NOPM, 0, 0),
549
550 SND_SOC_DAPM_PGA_S("ADACL", 2, NAU8821_R73_RDAC,
551 NAU8821_DACL_EN_SFT, 0, NULL, 0),
552 SND_SOC_DAPM_PGA_S("ADACR", 2, NAU8821_R73_RDAC,
553 NAU8821_DACR_EN_SFT, 0, NULL, 0),
554 SND_SOC_DAPM_PGA_S("ADACL Clock", 3, NAU8821_R73_RDAC,
555 NAU8821_DACL_CLK_EN_SFT, 0, NULL, 0),
556 SND_SOC_DAPM_PGA_S("ADACR Clock", 3, NAU8821_R73_RDAC,
557 NAU8821_DACR_CLK_EN_SFT, 0, NULL, 0),
558 SND_SOC_DAPM_DAC("DDACR", NULL, NAU8821_R01_ENA_CTRL,
559 NAU8821_EN_DACR_SFT, 0),
560 SND_SOC_DAPM_DAC("DDACL", NULL, NAU8821_R01_ENA_CTRL,
561 NAU8821_EN_DACL_SFT, 0),
562 SND_SOC_DAPM_PGA_S("HP amp L", 0, NAU8821_R4B_CLASSG_CTRL,
563 NAU8821_CLASSG_LDAC_EN_SFT, 0, NULL, 0),
564 SND_SOC_DAPM_PGA_S("HP amp R", 0, NAU8821_R4B_CLASSG_CTRL,
565 NAU8821_CLASSG_RDAC_EN_SFT, 0, NULL, 0),
566 SND_SOC_DAPM_PGA_S("Charge Pump", 1, NAU8821_R80_CHARGE_PUMP,
567 NAU8821_CHANRGE_PUMP_EN_SFT, 0, nau8821_pump_event,
568 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
569 SND_SOC_DAPM_PGA_S("Output Driver R Stage 1", 4,
570 NAU8821_R7F_POWER_UP_CONTROL,
571 NAU8821_PUP_INTEG_R_SFT, 0, NULL, 0),
572 SND_SOC_DAPM_PGA_S("Output Driver L Stage 1", 4,
573 NAU8821_R7F_POWER_UP_CONTROL,
574 NAU8821_PUP_INTEG_L_SFT, 0, NULL, 0),
575 SND_SOC_DAPM_PGA_S("Output Driver R Stage 2", 5,
576 NAU8821_R7F_POWER_UP_CONTROL,
577 NAU8821_PUP_DRV_INSTG_R_SFT, 0, NULL, 0),
578 SND_SOC_DAPM_PGA_S("Output Driver L Stage 2", 5,
579 NAU8821_R7F_POWER_UP_CONTROL,
580 NAU8821_PUP_DRV_INSTG_L_SFT, 0, NULL, 0),
581 SND_SOC_DAPM_PGA_S("Output Driver R Stage 3", 6,
582 NAU8821_R7F_POWER_UP_CONTROL,
583 NAU8821_PUP_MAIN_DRV_R_SFT, 0, NULL, 0),
584 SND_SOC_DAPM_PGA_S("Output Driver L Stage 3", 6,
585 NAU8821_R7F_POWER_UP_CONTROL,
586 NAU8821_PUP_MAIN_DRV_L_SFT, 0, NULL, 0),
587 SND_SOC_DAPM_PGA_S("Output DACL", 7,
588 NAU8821_R80_CHARGE_PUMP, NAU8821_POWER_DOWN_DACL_SFT,
589 0, nau8821_output_dac_event,
590 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
591 SND_SOC_DAPM_PGA_S("Output DACR", 7,
592 NAU8821_R80_CHARGE_PUMP, NAU8821_POWER_DOWN_DACR_SFT,
593 0, nau8821_output_dac_event,
594 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
595
596 /* HPOL/R are ungrounded by disabling 16 Ohm pull-downs on playback */
597 SND_SOC_DAPM_PGA_S("HPOL Pulldown", 8,
598 NAU8821_R0D_JACK_DET_CTRL,
599 NAU8821_SPKR_DWN1L_SFT, 0, NULL, 0),
600 SND_SOC_DAPM_PGA_S("HPOR Pulldown", 8,
601 NAU8821_R0D_JACK_DET_CTRL,
602 NAU8821_SPKR_DWN1R_SFT, 0, NULL, 0),
603
604 /* High current HPOL/R boost driver */
605 SND_SOC_DAPM_PGA_S("HP Boost Driver", 9,
606 NAU8821_R76_BOOST, NAU8821_HP_BOOST_DIS_SFT, 1, NULL, 0),
607 SND_SOC_DAPM_PGA("Class G", NAU8821_R4B_CLASSG_CTRL,
608 NAU8821_CLASSG_EN_SFT, 0, NULL, 0),
609
610 SND_SOC_DAPM_INPUT("MICL"),
611 SND_SOC_DAPM_INPUT("MICR"),
612 SND_SOC_DAPM_INPUT("DMIC"),
613 SND_SOC_DAPM_OUTPUT("HPOL"),
614 SND_SOC_DAPM_OUTPUT("HPOR"),
615};
616
617static const struct snd_soc_dapm_route nau8821_dapm_routes[] = {
618 {"DMIC Enable", "Switch", "DMIC"},
619 {"DMIC Enable", NULL, "DMIC Clock"},
620
621 {"Frontend PGA L", NULL, "MICL"},
622 {"Frontend PGA R", NULL, "MICR"},
623 {"Frontend PGA L", NULL, "MICBIAS"},
624 {"Frontend PGA R", NULL, "MICBIAS"},
625
626 {"ADCL Power", NULL, "Frontend PGA L"},
627 {"ADCR Power", NULL, "Frontend PGA R"},
628
629 {"ADCL Digital path", NULL, "ADCL Power"},
630 {"ADCR Digital path", NULL, "ADCR Power"},
631 {"ADCL Digital path", NULL, "DMIC Enable"},
632 {"ADCR Digital path", NULL, "DMIC Enable"},
633
634 {"AIFTX", NULL, "ADCL Digital path"},
635 {"AIFTX", NULL, "ADCR Digital path"},
636
0cf470c0
WL		 637 {"AIFTX", NULL, "System Clock"},
638 {"AIFRX", NULL, "System Clock"},
639
aab1ad11
SL		 640 {"DDACL", NULL, "AIFRX"},
641 {"DDACR", NULL, "AIFRX"},
642
643 {"HP amp L", NULL, "DDACL"},
644 {"HP amp R", NULL, "DDACR"},
645
646 {"Charge Pump", NULL, "HP amp L"},
647 {"Charge Pump", NULL, "HP amp R"},
648
649 {"ADACL", NULL, "Charge Pump"},
650 {"ADACR", NULL, "Charge Pump"},
651 {"ADACL Clock", NULL, "ADACL"},
652 {"ADACR Clock", NULL, "ADACR"},
653
654 {"Output Driver L Stage 1", NULL, "ADACL Clock"},
655 {"Output Driver R Stage 1", NULL, "ADACR Clock"},
656 {"Output Driver L Stage 2", NULL, "Output Driver L Stage 1"},
657 {"Output Driver R Stage 2", NULL, "Output Driver R Stage 1"},
658 {"Output Driver L Stage 3", NULL, "Output Driver L Stage 2"},
659 {"Output Driver R Stage 3", NULL, "Output Driver R Stage 2"},
660 {"Output DACL", NULL, "Output Driver L Stage 3"},
661 {"Output DACR", NULL, "Output Driver R Stage 3"},
662
663 {"HPOL Pulldown", NULL, "Output DACL"},
664 {"HPOR Pulldown", NULL, "Output DACR"},
665 {"HP Boost Driver", NULL, "HPOL Pulldown"},
666 {"HP Boost Driver", NULL, "HPOR Pulldown"},
667
668 {"Class G", NULL, "HP Boost Driver"},
669 {"HPOL", NULL, "Class G"},
670 {"HPOR", NULL, "Class G"},
671};
672
cf507187
TI		 673static const struct nau8821_osr_attr *
674nau8821_get_osr(struct nau8821 *nau8821, int stream)
aab1ad11 675{
cf507187 676 unsigned int osr;
aab1ad11
SL		 677
678 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
cf507187
TI		 679 regmap_read(nau8821->regmap, NAU8821_R2C_DAC_CTRL1, &osr);
680 osr &= NAU8821_DAC_OVERSAMPLE_MASK;
aab1ad11 681 if (osr >= ARRAY_SIZE(osr_dac_sel))
cf507187
TI		 682 return NULL;
683 return &osr_dac_sel[osr];
aab1ad11 684 } else {
cf507187
TI		 685 regmap_read(nau8821->regmap, NAU8821_R2B_ADC_RATE, &osr);
686 osr &= NAU8821_ADC_SYNC_DOWN_MASK;
aab1ad11 687 if (osr >= ARRAY_SIZE(osr_adc_sel))
cf507187
TI		 688 return NULL;
689 return &osr_adc_sel[osr];
aab1ad11 690 }
cf507187
TI		 691}
692
693static int nau8821_dai_startup(struct snd_pcm_substream *substream,
694 struct snd_soc_dai *dai)
695{
696 struct snd_soc_component *component = dai->component;
697 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
698 const struct nau8821_osr_attr *osr;
aab1ad11 699
cf507187
TI		 700 osr = nau8821_get_osr(nau8821, substream->stream);
701 if (!osr || !osr->osr)
aab1ad11 702 return -EINVAL;
aab1ad11 703
cf507187
TI		 704 return snd_pcm_hw_constraint_minmax(substream->runtime,
705 SNDRV_PCM_HW_PARAM_RATE,
706 0, CLK_DA_AD_MAX / osr->osr);
aab1ad11
SL		 707}
708
709static int nau8821_hw_params(struct snd_pcm_substream *substream,
710 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
711{
712 struct snd_soc_component *component = dai->component;
713 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
cf507187
TI		 714 unsigned int val_len = 0, ctrl_val, bclk_fs, clk_div;
715 const struct nau8821_osr_attr *osr;
aab1ad11
SL		 716
717 nau8821->fs = params_rate(params);
718 /* CLK_DAC or CLK_ADC = OSR * FS
719 * DAC or ADC clock frequency is defined as Over Sampling Rate (OSR)
720 * multiplied by the audio sample rate (Fs). Note that the OSR and Fs
721 * values must be selected such that the maximum frequency is less
722 * than 6.144 MHz.
723 */
cf507187
TI		 724 osr = nau8821_get_osr(nau8821, substream->stream);
725 if (!osr || !osr->osr)
726 return -EINVAL;
727 if (nau8821->fs * osr->osr > CLK_DA_AD_MAX)
728 return -EINVAL;
729 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
aab1ad11
SL		 730 regmap_update_bits(nau8821->regmap, NAU8821_R03_CLK_DIVIDER,
731 NAU8821_CLK_DAC_SRC_MASK,
cf507187
TI		 732 osr->clk_src << NAU8821_CLK_DAC_SRC_SFT);
733 else
aab1ad11
SL		 734 regmap_update_bits(nau8821->regmap, NAU8821_R03_CLK_DIVIDER,
735 NAU8821_CLK_ADC_SRC_MASK,
cf507187 736 osr->clk_src << NAU8821_CLK_ADC_SRC_SFT);
aab1ad11
SL		 737
738 /* make BCLK and LRC divde configuration if the codec as master. */
739 regmap_read(nau8821->regmap, NAU8821_R1D_I2S_PCM_CTRL2, &ctrl_val);
740 if (ctrl_val & NAU8821_I2S_MS_MASTER) {
741 /* get the bclk and fs ratio */
742 bclk_fs = snd_soc_params_to_bclk(params) / nau8821->fs;
743 if (bclk_fs <= 32)
744 clk_div = 3;
745 else if (bclk_fs <= 64)
746 clk_div = 2;
747 else if (bclk_fs <= 128)
748 clk_div = 1;
749 else {
750 return -EINVAL;
751 }
752 regmap_update_bits(nau8821->regmap, NAU8821_R1D_I2S_PCM_CTRL2,
753 NAU8821_I2S_LRC_DIV_MASK | NAU8821_I2S_BLK_DIV_MASK,
754 (clk_div << NAU8821_I2S_LRC_DIV_SFT) | clk_div);
755 }
756
757 switch (params_width(params)) {
758 case 16:
759 val_len |= NAU8821_I2S_DL_16;
760 break;
761 case 20:
762 val_len |= NAU8821_I2S_DL_20;
763 break;
764 case 24:
765 val_len |= NAU8821_I2S_DL_24;
766 break;
767 case 32:
768 val_len |= NAU8821_I2S_DL_32;
769 break;
770 default:
771 return -EINVAL;
772 }
773
774 regmap_update_bits(nau8821->regmap, NAU8821_R1C_I2S_PCM_CTRL1,
775 NAU8821_I2S_DL_MASK, val_len);
776
777 return 0;
778}
779
780static int nau8821_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
781{
782 struct snd_soc_component *component = codec_dai->component;
783 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
784 unsigned int ctrl1_val = 0, ctrl2_val = 0;
785
786 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
787 case SND_SOC_DAIFMT_CBP_CFP:
788 ctrl2_val |= NAU8821_I2S_MS_MASTER;
789 break;
790 case SND_SOC_DAIFMT_CBC_CFC:
791 break;
792 default:
793 return -EINVAL;
794 }
795
796 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
797 case SND_SOC_DAIFMT_NB_NF:
798 break;
799 case SND_SOC_DAIFMT_IB_NF:
800 ctrl1_val |= NAU8821_I2S_BP_INV;
801 break;
802 default:
803 return -EINVAL;
804 }
805
806 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
807 case SND_SOC_DAIFMT_I2S:
808 ctrl1_val |= NAU8821_I2S_DF_I2S;
809 break;
810 case SND_SOC_DAIFMT_LEFT_J:
811 ctrl1_val |= NAU8821_I2S_DF_LEFT;
812 break;
813 case SND_SOC_DAIFMT_RIGHT_J:
814 ctrl1_val |= NAU8821_I2S_DF_RIGTH;
815 break;
816 case SND_SOC_DAIFMT_DSP_A:
817 ctrl1_val |= NAU8821_I2S_DF_PCM_AB;
818 break;
819 case SND_SOC_DAIFMT_DSP_B:
820 ctrl1_val |= NAU8821_I2S_DF_PCM_AB;
821 ctrl1_val |= NAU8821_I2S_PCMB_EN;
822 break;
823 default:
824 return -EINVAL;
825 }
826
827 regmap_update_bits(nau8821->regmap, NAU8821_R1C_I2S_PCM_CTRL1,
828 NAU8821_I2S_DL_MASK | NAU8821_I2S_DF_MASK |
829 NAU8821_I2S_BP_MASK | NAU8821_I2S_PCMB_MASK, ctrl1_val);
830 regmap_update_bits(nau8821->regmap, NAU8821_R1D_I2S_PCM_CTRL2,
831 NAU8821_I2S_MS_MASK, ctrl2_val);
832
833 return 0;
834}
835
836static int nau8821_digital_mute(struct snd_soc_dai *dai, int mute,
837 int direction)
838{
839 struct snd_soc_component *component = dai->component;
840 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
841 unsigned int val = 0;
842
843 if (mute)
844 val = NAU8821_DAC_SOFT_MUTE;
845
846 return regmap_update_bits(nau8821->regmap,
847 NAU8821_R31_MUTE_CTRL, NAU8821_DAC_SOFT_MUTE, val);
848}
849
850static const struct snd_soc_dai_ops nau8821_dai_ops = {
cf507187 851 .startup = nau8821_dai_startup,
aab1ad11
SL		 852 .hw_params = nau8821_hw_params,
853 .set_fmt = nau8821_set_dai_fmt,
854 .mute_stream = nau8821_digital_mute,
aa9753a4 855 .no_capture_mute = 1,
aab1ad11
SL		 856};
857
858#define NAU8821_RATES SNDRV_PCM_RATE_8000_192000
859#define NAU8821_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
860 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
861
862static struct snd_soc_dai_driver nau8821_dai = {
863 .name = NUVOTON_CODEC_DAI,
864 .playback = {
865 .stream_name = "Playback",
866 .channels_min = 1,
867 .channels_max = 2,
868 .rates = NAU8821_RATES,
869 .formats = NAU8821_FORMATS,
870 },
871 .capture = {
872 .stream_name = "Capture",
873 .channels_min = 1,
874 .channels_max = 2,
875 .rates = NAU8821_RATES,
876 .formats = NAU8821_FORMATS,
877 },
878 .ops = &nau8821_dai_ops,
879};
880
881
882static bool nau8821_is_jack_inserted(struct regmap *regmap)
883{
884 bool active_high, is_high;
885 int status, jkdet;
886
887 regmap_read(regmap, NAU8821_R0D_JACK_DET_CTRL, &jkdet);
888 active_high = jkdet & NAU8821_JACK_POLARITY;
889 regmap_read(regmap, NAU8821_R82_GENERAL_STATUS, &status);
890 is_high = status & NAU8821_GPIO2_IN;
891 /* return jack connection status according to jack insertion logic
892 * active high or active low.
893 */
894 return active_high == is_high;
895}
896
897static void nau8821_int_status_clear_all(struct regmap *regmap)
898{
899 int active_irq, clear_irq, i;
900
901 /* Reset the intrruption status from rightmost bit if the corres-
902 * ponding irq event occurs.
903 */
904 regmap_read(regmap, NAU8821_R10_IRQ_STATUS, &active_irq);
905 for (i = 0; i < NAU8821_REG_DATA_LEN; i++) {
906 clear_irq = (0x1 << i);
907 if (active_irq & clear_irq)
908 regmap_write(regmap,
909 NAU8821_R11_INT_CLR_KEY_STATUS, clear_irq);
910 }
911}
912
913static void nau8821_eject_jack(struct nau8821 *nau8821)
914{
915 struct snd_soc_dapm_context *dapm = nau8821->dapm;
916 struct regmap *regmap = nau8821->regmap;
917 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm);
918
919 /* Detach 2kOhm Resistors from MICBIAS to MICGND */
920 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS,
921 NAU8821_MICBIAS_JKR2, 0);
922 /* HPL/HPR short to ground */
923 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
924 NAU8821_SPKR_DWN1R | NAU8821_SPKR_DWN1L, 0);
925 snd_soc_component_disable_pin(component, "MICBIAS");
926 snd_soc_dapm_sync(dapm);
927
928 /* Clear all interruption status */
929 nau8821_int_status_clear_all(regmap);
930
931 /* Enable the insertion interruption, disable the ejection inter-
932 * ruption, and then bypass de-bounce circuit.
933 */
934 regmap_update_bits(regmap, NAU8821_R12_INTERRUPT_DIS_CTRL,
935 NAU8821_IRQ_EJECT_DIS | NAU8821_IRQ_INSERT_DIS,
936 NAU8821_IRQ_EJECT_DIS);
937 /* Mask unneeded IRQs: 1 - disable, 0 - enable */
938 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK,
939 NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN,
940 NAU8821_IRQ_EJECT_EN);
941
942 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
943 NAU8821_JACK_DET_DB_BYPASS, NAU8821_JACK_DET_DB_BYPASS);
944
945 /* Close clock for jack type detection at manual mode */
946 if (dapm->bias_level < SND_SOC_BIAS_PREPARE)
947 nau8821_configure_sysclk(nau8821, NAU8821_CLK_DIS, 0);
948
949 /* Recover to normal channel input */
950 regmap_update_bits(regmap, NAU8821_R2B_ADC_RATE,
951 NAU8821_ADC_R_SRC_EN, 0);
2551b6e8
SL		 952 if (nau8821->key_enable) {
953 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK,
954 NAU8821_IRQ_KEY_RELEASE_EN |
955 NAU8821_IRQ_KEY_PRESS_EN,
956 NAU8821_IRQ_KEY_RELEASE_EN |
957 NAU8821_IRQ_KEY_PRESS_EN);
958 regmap_update_bits(regmap,
959 NAU8821_R12_INTERRUPT_DIS_CTRL,
960 NAU8821_IRQ_KEY_RELEASE_DIS |
961 NAU8821_IRQ_KEY_PRESS_DIS,
962 NAU8821_IRQ_KEY_RELEASE_DIS |
963 NAU8821_IRQ_KEY_PRESS_DIS);
964 }
965
aab1ad11
SL		 966}
967
968static void nau8821_jdet_work(struct work_struct *work)
969{
970 struct nau8821 *nau8821 =
971 container_of(work, struct nau8821, jdet_work);
972 struct snd_soc_dapm_context *dapm = nau8821->dapm;
973 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm);
974 struct regmap *regmap = nau8821->regmap;
975 int jack_status_reg, mic_detected, event = 0, event_mask = 0;
976
977 snd_soc_component_force_enable_pin(component, "MICBIAS");
978 snd_soc_dapm_sync(dapm);
979 msleep(20);
980
981 regmap_read(regmap, NAU8821_R58_I2C_DEVICE_ID, &jack_status_reg);
982 mic_detected = !(jack_status_reg & NAU8821_KEYDET);
983 if (mic_detected) {
984 dev_dbg(nau8821->dev, "Headset connected\n");
985 event |= SND_JACK_HEADSET;
986
987 /* 2kOhm Resistor from MICBIAS to MICGND1 */
988 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS,
989 NAU8821_MICBIAS_JKR2, NAU8821_MICBIAS_JKR2);
990 /* Latch Right Channel Analog data
991 * input into the Right Channel Filter
992 */
993 regmap_update_bits(regmap, NAU8821_R2B_ADC_RATE,
994 NAU8821_ADC_R_SRC_EN, NAU8821_ADC_R_SRC_EN);
2551b6e8
SL		 995 if (nau8821->key_enable) {
996 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK,
997 NAU8821_IRQ_KEY_RELEASE_EN |
998 NAU8821_IRQ_KEY_PRESS_EN, 0);
999 regmap_update_bits(regmap,
1000 NAU8821_R12_INTERRUPT_DIS_CTRL,
1001 NAU8821_IRQ_KEY_RELEASE_DIS |
1002 NAU8821_IRQ_KEY_PRESS_DIS, 0);
1003 }
aab1ad11
SL		 1004 } else {
1005 dev_dbg(nau8821->dev, "Headphone connected\n");
1006 event |= SND_JACK_HEADPHONE;
1007 snd_soc_component_disable_pin(component, "MICBIAS");
1008 snd_soc_dapm_sync(dapm);
1009 }
1010 event_mask |= SND_JACK_HEADSET;
1011 snd_soc_jack_report(nau8821->jack, event, event_mask);
1012}
1013
1014/* Enable interruptions with internal clock. */
1015static void nau8821_setup_inserted_irq(struct nau8821 *nau8821)
1016{
1017 struct regmap *regmap = nau8821->regmap;
1018
1019 /* Enable internal VCO needed for interruptions */
1020 if (nau8821->dapm->bias_level < SND_SOC_BIAS_PREPARE)
1021 nau8821_configure_sysclk(nau8821, NAU8821_CLK_INTERNAL, 0);
1022
1023 /* Chip needs one FSCLK cycle in order to generate interruptions,
1024 * as we cannot guarantee one will be provided by the system. Turning
1025 * master mode on then off enables us to generate that FSCLK cycle
1026 * with a minimum of contention on the clock bus.
1027 */
1028 regmap_update_bits(regmap, NAU8821_R1D_I2S_PCM_CTRL2,
1029 NAU8821_I2S_MS_MASK, NAU8821_I2S_MS_MASTER);
1030 regmap_update_bits(regmap, NAU8821_R1D_I2S_PCM_CTRL2,
1031 NAU8821_I2S_MS_MASK, NAU8821_I2S_MS_SLAVE);
1032
1033 /* Not bypass de-bounce circuit */
1034 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
1035 NAU8821_JACK_DET_DB_BYPASS, 0);
1036
1037 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK,
1038 NAU8821_IRQ_EJECT_EN, 0);
1039 regmap_update_bits(regmap, NAU8821_R12_INTERRUPT_DIS_CTRL,
1040 NAU8821_IRQ_EJECT_DIS, 0);
1041}
1042
1043static irqreturn_t nau8821_interrupt(int irq, void *data)
1044{
1045 struct nau8821 *nau8821 = (struct nau8821 *)data;
1046 struct regmap *regmap = nau8821->regmap;
1047 int active_irq, clear_irq = 0, event = 0, event_mask = 0;
1048
1049 if (regmap_read(regmap, NAU8821_R10_IRQ_STATUS, &active_irq)) {
1050 dev_err(nau8821->dev, "failed to read irq status\n");
1051 return IRQ_NONE;
1052 }
1053
1054 dev_dbg(nau8821->dev, "IRQ %d\n", active_irq);
1055
1056 if ((active_irq & NAU8821_JACK_EJECT_IRQ_MASK) ==
1057 NAU8821_JACK_EJECT_DETECTED) {
1058 regmap_update_bits(regmap, NAU8821_R71_ANALOG_ADC_1,
1059 NAU8821_MICDET_MASK, NAU8821_MICDET_DIS);
1060 nau8821_eject_jack(nau8821);
1061 event_mask |= SND_JACK_HEADSET;
1062 clear_irq = NAU8821_JACK_EJECT_IRQ_MASK;
2551b6e8
SL		 1063 } else if (active_irq & NAU8821_KEY_SHORT_PRESS_IRQ) {
1064 event |= NAU8821_BUTTON;
1065 event_mask |= NAU8821_BUTTON;
1066 clear_irq = NAU8821_KEY_SHORT_PRESS_IRQ;
1067 } else if (active_irq & NAU8821_KEY_RELEASE_IRQ) {
1068 event_mask = NAU8821_BUTTON;
1069 clear_irq = NAU8821_KEY_RELEASE_IRQ;
aab1ad11
SL		 1070 } else if ((active_irq & NAU8821_JACK_INSERT_IRQ_MASK) ==
1071 NAU8821_JACK_INSERT_DETECTED) {
1072 regmap_update_bits(regmap, NAU8821_R71_ANALOG_ADC_1,
1073 NAU8821_MICDET_MASK, NAU8821_MICDET_EN);
1074 if (nau8821_is_jack_inserted(regmap)) {
1075 /* detect microphone and jack type */
1076 cancel_work_sync(&nau8821->jdet_work);
1077 schedule_work(&nau8821->jdet_work);
1078 /* Turn off insertion interruption at manual mode */
1079 regmap_update_bits(regmap,
1080 NAU8821_R12_INTERRUPT_DIS_CTRL,
1081 NAU8821_IRQ_INSERT_DIS,
1082 NAU8821_IRQ_INSERT_DIS);
1083 regmap_update_bits(regmap,
1084 NAU8821_R0F_INTERRUPT_MASK,
1085 NAU8821_IRQ_INSERT_EN,
1086 NAU8821_IRQ_INSERT_EN);
1087 nau8821_setup_inserted_irq(nau8821);
1088 } else {
1089 dev_warn(nau8821->dev,
1090 "Inserted IRQ fired but not connected\n");
1091 nau8821_eject_jack(nau8821);
1092 }
1093 }
1094
1095 if (!clear_irq)
1096 clear_irq = active_irq;
1097 /* clears the rightmost interruption */
1098 regmap_write(regmap, NAU8821_R11_INT_CLR_KEY_STATUS, clear_irq);
1099
1100 if (event_mask)
1101 snd_soc_jack_report(nau8821->jack, event, event_mask);
1102
1103 return IRQ_HANDLED;
1104}
1105
1106static const struct regmap_config nau8821_regmap_config = {
1107 .val_bits = NAU8821_REG_DATA_LEN,
1108 .reg_bits = NAU8821_REG_ADDR_LEN,
1109
1110 .max_register = NAU8821_REG_MAX,
1111 .readable_reg = nau8821_readable_reg,
1112 .writeable_reg = nau8821_writeable_reg,
1113 .volatile_reg = nau8821_volatile_reg,
1114
1115 .cache_type = REGCACHE_RBTREE,
1116 .reg_defaults = nau8821_reg_defaults,
1117 .num_reg_defaults = ARRAY_SIZE(nau8821_reg_defaults),
1118};
1119
1120static int nau8821_component_probe(struct snd_soc_component *component)
1121{
1122 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
1123 struct snd_soc_dapm_context *dapm =
1124 snd_soc_component_get_dapm(component);
1125
1126 nau8821->dapm = dapm;
1127
1128 return 0;
1129}
1130
1131/**
1132 * nau8821_calc_fll_param - Calculate FLL parameters.
1133 * @fll_in: external clock provided to codec.
1134 * @fs: sampling rate.
1135 * @fll_param: Pointer to structure of FLL parameters.
1136 *
1137 * Calculate FLL parameters to configure codec.
1138 *
1139 * Returns 0 for success or negative error code.
1140 */
1141static int nau8821_calc_fll_param(unsigned int fll_in,
1142 unsigned int fs, struct nau8821_fll *fll_param)
1143{
1144 u64 fvco, fvco_max;
1145 unsigned int fref, i, fvco_sel;
1146
1147 /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by
1148 * dividing freq_in by 1, 2, 4, or 8 using FLL pre-scalar.
1149 * FREF = freq_in / NAU8821_FLL_REF_DIV_MASK
1150 */
1151 for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) {
1152 fref = fll_in >> fll_pre_scalar[i].param;
1153 if (fref <= NAU_FREF_MAX)
1154 break;
1155 }
1156 if (i == ARRAY_SIZE(fll_pre_scalar))
1157 return -EINVAL;
1158 fll_param->clk_ref_div = fll_pre_scalar[i].val;
1159
1160 /* Choose the FLL ratio based on FREF */
1161 for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) {
1162 if (fref >= fll_ratio[i].param)
1163 break;
1164 }
1165 if (i == ARRAY_SIZE(fll_ratio))
1166 return -EINVAL;
1167 fll_param->ratio = fll_ratio[i].val;
1168
1169 /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs.
1170 * FDCO must be within the 90MHz - 100MHz or the FFL cannot be
1171 * guaranteed across the full range of operation.
1172 * FDCO = freq_out * 2 * mclk_src_scaling
1173 */
1174 fvco_max = 0;
1175 fvco_sel = ARRAY_SIZE(mclk_src_scaling);
1176 for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) {
1177 fvco = 256ULL * fs * 2 * mclk_src_scaling[i].param;
1178 if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX &&
1179 fvco_max < fvco) {
1180 fvco_max = fvco;
1181 fvco_sel = i;
1182 }
1183 }
1184 if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel)
1185 return -EINVAL;
1186 fll_param->mclk_src = mclk_src_scaling[fvco_sel].val;
1187
1188 /* Calculate the FLL 10-bit integer input and the FLL 24-bit fractional
1189 * input based on FDCO, FREF and FLL ratio.
1190 */
1191 fvco = div_u64(fvco_max << 24, fref * fll_param->ratio);
1192 fll_param->fll_int = (fvco >> 24) & 0x3ff;
1193 fll_param->fll_frac = fvco & 0xffffff;
1194
1195 return 0;
1196}
1197
1198static void nau8821_fll_apply(struct nau8821 *nau8821,
1199 struct nau8821_fll *fll_param)
1200{
1201 struct regmap *regmap = nau8821->regmap;
1202
1203 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER,
1204 NAU8821_CLK_SRC_MASK | NAU8821_CLK_MCLK_SRC_MASK,
1205 NAU8821_CLK_SRC_MCLK | fll_param->mclk_src);
1206 /* Make DSP operate at high speed for better performance. */
1207 regmap_update_bits(regmap, NAU8821_R04_FLL1,
1208 NAU8821_FLL_RATIO_MASK | NAU8821_ICTRL_LATCH_MASK,
1209 fll_param->ratio | (0x6 << NAU8821_ICTRL_LATCH_SFT));
1210 /* FLL 24-bit fractional input */
1211 regmap_write(regmap, NAU8821_R0A_FLL7,
1212 (fll_param->fll_frac >> 16) & 0xff);
1213 regmap_write(regmap, NAU8821_R0B_FLL8, fll_param->fll_frac & 0xffff);
1214 /* FLL 10-bit integer input */
1215 regmap_update_bits(regmap, NAU8821_R06_FLL3,
1216 NAU8821_FLL_INTEGER_MASK, fll_param->fll_int);
1217 /* FLL pre-scaler */
1218 regmap_update_bits(regmap, NAU8821_R07_FLL4,
1219 NAU8821_HIGHBW_EN | NAU8821_FLL_REF_DIV_MASK,
1220 NAU8821_HIGHBW_EN |
1221 (fll_param->clk_ref_div << NAU8821_FLL_REF_DIV_SFT));
1222 /* select divided VCO input */
1223 regmap_update_bits(regmap, NAU8821_R08_FLL5,
1224 NAU8821_FLL_CLK_SW_MASK, NAU8821_FLL_CLK_SW_REF);
1225 /* Disable free-running mode */
1226 regmap_update_bits(regmap,
1227 NAU8821_R09_FLL6, NAU8821_DCO_EN, 0);
1228 if (fll_param->fll_frac) {
1229 /* set FLL loop filter enable and cutoff frequency at 500Khz */
1230 regmap_update_bits(regmap, NAU8821_R08_FLL5,
1231 NAU8821_FLL_PDB_DAC_EN | NAU8821_FLL_LOOP_FTR_EN |
1232 NAU8821_FLL_FTR_SW_MASK,
1233 NAU8821_FLL_PDB_DAC_EN | NAU8821_FLL_LOOP_FTR_EN |
1234 NAU8821_FLL_FTR_SW_FILTER);
1235 regmap_update_bits(regmap, NAU8821_R09_FLL6,
1236 NAU8821_SDM_EN | NAU8821_CUTOFF500,
1237 NAU8821_SDM_EN | NAU8821_CUTOFF500);
1238 } else {
1239 /* disable FLL loop filter and cutoff frequency */
1240 regmap_update_bits(regmap, NAU8821_R08_FLL5,
1241 NAU8821_FLL_PDB_DAC_EN | NAU8821_FLL_LOOP_FTR_EN |
1242 NAU8821_FLL_FTR_SW_MASK, NAU8821_FLL_FTR_SW_ACCU);
1243 regmap_update_bits(regmap, NAU8821_R09_FLL6,
1244 NAU8821_SDM_EN | NAU8821_CUTOFF500, 0);
1245 }
1246}
1247
1248/**
1249 * nau8821_set_fll - FLL configuration of nau8821
765e08bd
PLB		 1250 * @component: codec component
1251 * @pll_id: PLL requested
1252 * @source: clock source
aab1ad11
SL		 1253 * @freq_in: frequency of input clock source
1254 * @freq_out: must be 256*Fs in order to achieve the best performance
1255 *
1256 * The FLL function can select BCLK or MCLK as the input clock source.
1257 *
1258 * Returns 0 if the parameters have been applied successfully
1259 * or negative error code.
1260 */
1261static int nau8821_set_fll(struct snd_soc_component *component,
1262 int pll_id, int source, unsigned int freq_in, unsigned int freq_out)
1263{
1264 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
1265 struct nau8821_fll fll_set_param, *fll_param = &fll_set_param;
1266 int ret, fs;
1267
1268 fs = freq_out >> 8;
1269 ret = nau8821_calc_fll_param(freq_in, fs, fll_param);
1270 if (ret) {
1271 dev_err(nau8821->dev,
1272 "Unsupported input clock %d to output clock %d\n",
1273 freq_in, freq_out);
1274 return ret;
1275 }
1276 dev_dbg(nau8821->dev,
1277 "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",
1278 fll_param->mclk_src, fll_param->ratio, fll_param->fll_frac,
1279 fll_param->fll_int, fll_param->clk_ref_div);
1280
1281 nau8821_fll_apply(nau8821, fll_param);
1282 mdelay(2);
1283 regmap_update_bits(nau8821->regmap, NAU8821_R03_CLK_DIVIDER,
1284 NAU8821_CLK_SRC_MASK, NAU8821_CLK_SRC_VCO);
1285
1286 return 0;
1287}
1288
1289static void nau8821_configure_mclk_as_sysclk(struct regmap *regmap)
1290{
1291 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER,
1292 NAU8821_CLK_SRC_MASK, NAU8821_CLK_SRC_MCLK);
1293 regmap_update_bits(regmap, NAU8821_R09_FLL6,
1294 NAU8821_DCO_EN, 0);
1295 /* Make DSP operate as default setting for power saving. */
1296 regmap_update_bits(regmap, NAU8821_R04_FLL1,
1297 NAU8821_ICTRL_LATCH_MASK, 0);
1298}
1299
1300static int nau8821_configure_sysclk(struct nau8821 *nau8821,
1301 int clk_id, unsigned int freq)
1302{
1303 struct regmap *regmap = nau8821->regmap;
1304
1305 switch (clk_id) {
1306 case NAU8821_CLK_DIS:
1307 /* Clock provided externally and disable internal VCO clock */
1308 nau8821_configure_mclk_as_sysclk(regmap);
1309 break;
1310 case NAU8821_CLK_MCLK:
1311 nau8821_configure_mclk_as_sysclk(regmap);
1312 /* MCLK not changed by clock tree */
1313 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER,
1314 NAU8821_CLK_MCLK_SRC_MASK, 0);
1315 break;
1316 case NAU8821_CLK_INTERNAL:
1317 if (nau8821_is_jack_inserted(regmap)) {
1318 regmap_update_bits(regmap, NAU8821_R09_FLL6,
1319 NAU8821_DCO_EN, NAU8821_DCO_EN);
1320 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER,
1321 NAU8821_CLK_SRC_MASK, NAU8821_CLK_SRC_VCO);
1322 /* Decrease the VCO frequency and make DSP operate
1323 * as default setting for power saving.
1324 */
1325 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER,
1326 NAU8821_CLK_MCLK_SRC_MASK, 0xf);
1327 regmap_update_bits(regmap, NAU8821_R04_FLL1,
1328 NAU8821_ICTRL_LATCH_MASK |
1329 NAU8821_FLL_RATIO_MASK, 0x10);
1330 regmap_update_bits(regmap, NAU8821_R09_FLL6,
1331 NAU8821_SDM_EN, NAU8821_SDM_EN);
1332 }
1333 break;
1334 case NAU8821_CLK_FLL_MCLK:
1335 /* Higher FLL reference input frequency can only set lower
1336 * gain error, such as 0000 for input reference from MCLK
1337 * 12.288Mhz.
1338 */
1339 regmap_update_bits(regmap, NAU8821_R06_FLL3,
1340 NAU8821_FLL_CLK_SRC_MASK | NAU8821_GAIN_ERR_MASK,
1341 NAU8821_FLL_CLK_SRC_MCLK | 0);
1342 break;
1343 case NAU8821_CLK_FLL_BLK:
1344 /* If FLL reference input is from low frequency source,
1345 * higher error gain can apply such as 0xf which has
1346 * the most sensitive gain error correction threshold,
1347 * Therefore, FLL has the most accurate DCO to
1348 * target frequency.
1349 */
1350 regmap_update_bits(regmap, NAU8821_R06_FLL3,
1351 NAU8821_FLL_CLK_SRC_MASK | NAU8821_GAIN_ERR_MASK,
1352 NAU8821_FLL_CLK_SRC_BLK |
1353 (0xf << NAU8821_GAIN_ERR_SFT));
1354 break;
1355 case NAU8821_CLK_FLL_FS:
1356 /* If FLL reference input is from low frequency source,
1357 * higher error gain can apply such as 0xf which has
1358 * the most sensitive gain error correction threshold,
1359 * Therefore, FLL has the most accurate DCO to
1360 * target frequency.
1361 */
1362 regmap_update_bits(regmap, NAU8821_R06_FLL3,
1363 NAU8821_FLL_CLK_SRC_MASK | NAU8821_GAIN_ERR_MASK,
1364 NAU8821_FLL_CLK_SRC_FS |
1365 (0xf << NAU8821_GAIN_ERR_SFT));
1366 break;
1367 default:
1368 dev_err(nau8821->dev, "Invalid clock id (%d)\n", clk_id);
1369 return -EINVAL;
1370 }
1371 nau8821->clk_id = clk_id;
1372 dev_dbg(nau8821->dev, "Sysclk is %dHz and clock id is %d\n", freq,
1373 nau8821->clk_id);
1374
1375 return 0;
1376}
1377
1378static int nau8821_set_sysclk(struct snd_soc_component *component, int clk_id,
1379 int source, unsigned int freq, int dir)
1380{
1381 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
1382
1383 return nau8821_configure_sysclk(nau8821, clk_id, freq);
1384}
1385
1386static int nau8821_resume_setup(struct nau8821 *nau8821)
1387{
1388 struct regmap *regmap = nau8821->regmap;
1389
1390 /* Close clock when jack type detection at manual mode */
1391 nau8821_configure_sysclk(nau8821, NAU8821_CLK_DIS, 0);
1392 if (nau8821->irq) {
1393 /* Clear all interruption status */
1394 nau8821_int_status_clear_all(regmap);
1395
1396 /* Enable both insertion and ejection interruptions, and then
1397 * bypass de-bounce circuit.
1398 */
1399 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK,
1400 NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN, 0);
1401 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
1402 NAU8821_JACK_DET_DB_BYPASS,
1403 NAU8821_JACK_DET_DB_BYPASS);
1404 regmap_update_bits(regmap, NAU8821_R12_INTERRUPT_DIS_CTRL,
1405 NAU8821_IRQ_INSERT_DIS | NAU8821_IRQ_EJECT_DIS, 0);
1406 }
1407
1408 return 0;
1409}
1410
1411static int nau8821_set_bias_level(struct snd_soc_component *component,
1412 enum snd_soc_bias_level level)
1413{
1414 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
1415 struct regmap *regmap = nau8821->regmap;
1416
1417 switch (level) {
1418 case SND_SOC_BIAS_ON:
1419 break;
1420
1421 case SND_SOC_BIAS_PREPARE:
1422 break;
1423
1424 case SND_SOC_BIAS_STANDBY:
1425 /* Setup codec configuration after resume */
1426 if (snd_soc_component_get_bias_level(component) ==
1427 SND_SOC_BIAS_OFF)
1428 nau8821_resume_setup(nau8821);
1429 break;
1430
1431 case SND_SOC_BIAS_OFF:
1432 /* HPL/HPR short to ground */
1433 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
1434 NAU8821_SPKR_DWN1R | NAU8821_SPKR_DWN1L, 0);
1435 if (nau8821->irq) {
1436 /* Reset the configuration of jack type for detection.
1437 * Detach 2kOhm Resistors from MICBIAS to MICGND1/2.
1438 */
1439 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS,
1440 NAU8821_MICBIAS_JKR2, 0);
1441 /* Turn off all interruptions before system shutdown.
1442 * Keep theinterruption quiet before resume
1443 * setup completes.
1444 */
1445 regmap_write(regmap,
1446 NAU8821_R12_INTERRUPT_DIS_CTRL, 0xffff);
1447 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK,
1448 NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN,
1449 NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN);
1450 }
1451 break;
1452 default:
1453 break;
1454 }
1455
1456 return 0;
1457}
1458
1459static int __maybe_unused nau8821_suspend(struct snd_soc_component *component)
1460{
1461 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
1462
1463 if (nau8821->irq)
1464 disable_irq(nau8821->irq);
1465 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
1466 /* Power down codec power; don't support button wakeup */
1467 snd_soc_component_disable_pin(component, "MICBIAS");
1468 snd_soc_dapm_sync(nau8821->dapm);
1469 regcache_cache_only(nau8821->regmap, true);
1470 regcache_mark_dirty(nau8821->regmap);
1471
1472 return 0;
1473}
1474
1475static int __maybe_unused nau8821_resume(struct snd_soc_component *component)
1476{
1477 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
1478
1479 regcache_cache_only(nau8821->regmap, false);
1480 regcache_sync(nau8821->regmap);
1481 if (nau8821->irq)
1482 enable_irq(nau8821->irq);
1483
1484 return 0;
1485}
1486
1487static const struct snd_soc_component_driver nau8821_component_driver = {
1488 .probe = nau8821_component_probe,
1489 .set_sysclk = nau8821_set_sysclk,
1490 .set_pll = nau8821_set_fll,
1491 .set_bias_level = nau8821_set_bias_level,
1492 .suspend = nau8821_suspend,
1493 .resume = nau8821_resume,
1494 .controls = nau8821_controls,
1495 .num_controls = ARRAY_SIZE(nau8821_controls),
1496 .dapm_widgets = nau8821_dapm_widgets,
1497 .num_dapm_widgets = ARRAY_SIZE(nau8821_dapm_widgets),
1498 .dapm_routes = nau8821_dapm_routes,
1499 .num_dapm_routes = ARRAY_SIZE(nau8821_dapm_routes),
1500 .suspend_bias_off = 1,
aab1ad11
SL		 1501 .idle_bias_on = 1,
1502 .use_pmdown_time = 1,
1503 .endianness = 1,
1504};
1505
1506/**
1507 * nau8821_enable_jack_detect - Specify a jack for event reporting
1508 *
1509 * @component: component to register the jack with
1510 * @jack: jack to use to report headset and button events on
1511 *
1512 * After this function has been called the headset insert/remove and button
1513 * events will be routed to the given jack. Jack can be null to stop
1514 * reporting.
1515 */
1516int nau8821_enable_jack_detect(struct snd_soc_component *component,
1517 struct snd_soc_jack *jack)
1518{
1519 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
1520 int ret;
1521
1522 nau8821->jack = jack;
1523 /* Initiate jack detection work queue */
1524 INIT_WORK(&nau8821->jdet_work, nau8821_jdet_work);
1525 ret = devm_request_threaded_irq(nau8821->dev, nau8821->irq, NULL,
1526 nau8821_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1527 "nau8821", nau8821);
1528 if (ret) {
1529 dev_err(nau8821->dev, "Cannot request irq %d (%d)\n",
1530 nau8821->irq, ret);
1531 return ret;
1532 }
1533
1534 return ret;
1535}
1536EXPORT_SYMBOL_GPL(nau8821_enable_jack_detect);
1537
1538static void nau8821_reset_chip(struct regmap *regmap)
1539{
1540 regmap_write(regmap, NAU8821_R00_RESET, 0xffff);
1541 regmap_write(regmap, NAU8821_R00_RESET, 0xffff);
1542}
1543
1544static void nau8821_print_device_properties(struct nau8821 *nau8821)
1545{
1546 struct device *dev = nau8821->dev;
1547
1548 dev_dbg(dev, "jkdet-enable: %d\n", nau8821->jkdet_enable);
1549 dev_dbg(dev, "jkdet-pull-enable: %d\n", nau8821->jkdet_pull_enable);
1550 dev_dbg(dev, "jkdet-pull-up: %d\n", nau8821->jkdet_pull_up);
1551 dev_dbg(dev, "jkdet-polarity: %d\n", nau8821->jkdet_polarity);
1552 dev_dbg(dev, "micbias-voltage: %d\n", nau8821->micbias_voltage);
1553 dev_dbg(dev, "vref-impedance: %d\n", nau8821->vref_impedance);
1554 dev_dbg(dev, "jack-insert-debounce: %d\n",
1555 nau8821->jack_insert_debounce);
1556 dev_dbg(dev, "jack-eject-debounce: %d\n",
1557 nau8821->jack_eject_debounce);
1558 dev_dbg(dev, "dmic-clk-threshold: %d\n",
1559 nau8821->dmic_clk_threshold);
2551b6e8 1560 dev_dbg(dev, "key_enable: %d\n", nau8821->key_enable);
aab1ad11
SL		 1561}
1562
1563static int nau8821_read_device_properties(struct device *dev,
1564 struct nau8821 *nau8821)
1565{
1566 int ret;
1567
1568 nau8821->jkdet_enable = device_property_read_bool(dev,
1569 "nuvoton,jkdet-enable");
1570 nau8821->jkdet_pull_enable = device_property_read_bool(dev,
1571 "nuvoton,jkdet-pull-enable");
1572 nau8821->jkdet_pull_up = device_property_read_bool(dev,
1573 "nuvoton,jkdet-pull-up");
2551b6e8
SL		 1574 nau8821->key_enable = device_property_read_bool(dev,
1575 "nuvoton,key-enable");
aab1ad11
SL		 1576 ret = device_property_read_u32(dev, "nuvoton,jkdet-polarity",
1577 &nau8821->jkdet_polarity);
1578 if (ret)
1579 nau8821->jkdet_polarity = 1;
1580 ret = device_property_read_u32(dev, "nuvoton,micbias-voltage",
1581 &nau8821->micbias_voltage);
1582 if (ret)
1583 nau8821->micbias_voltage = 6;
1584 ret = device_property_read_u32(dev, "nuvoton,vref-impedance",
1585 &nau8821->vref_impedance);
1586 if (ret)
1587 nau8821->vref_impedance = 2;
1588 ret = device_property_read_u32(dev, "nuvoton,jack-insert-debounce",
1589 &nau8821->jack_insert_debounce);
1590 if (ret)
1591 nau8821->jack_insert_debounce = 7;
1592 ret = device_property_read_u32(dev, "nuvoton,jack-eject-debounce",
1593 &nau8821->jack_eject_debounce);
1594 if (ret)
1595 nau8821->jack_eject_debounce = 0;
1596 ret = device_property_read_u32(dev, "nuvoton,dmic-clk-threshold",
1597 &nau8821->dmic_clk_threshold);
1598 if (ret)
1599 nau8821->dmic_clk_threshold = 3072000;
1600
1601 return 0;
1602}
1603
1604static void nau8821_init_regs(struct nau8821 *nau8821)
1605{
1606 struct regmap *regmap = nau8821->regmap;
1607
1608 /* Enable Bias/Vmid */
1609 regmap_update_bits(regmap, NAU8821_R66_BIAS_ADJ,
1610 NAU8821_BIAS_VMID, NAU8821_BIAS_VMID);
1611 regmap_update_bits(regmap, NAU8821_R76_BOOST,
1612 NAU8821_GLOBAL_BIAS_EN, NAU8821_GLOBAL_BIAS_EN);
1613 /* VMID Tieoff setting and enable TESTDAC.
1614 * This sets the analog DAC inputs to a '0' input signal to avoid
1615 * any glitches due to power up transients in both the analog and
1616 * digital DAC circuit.
1617 */
1618 regmap_update_bits(regmap, NAU8821_R66_BIAS_ADJ,
1619 NAU8821_BIAS_VMID_SEL_MASK | NAU8821_BIAS_TESTDAC_EN,
1620 (nau8821->vref_impedance << NAU8821_BIAS_VMID_SEL_SFT) |
1621 NAU8821_BIAS_TESTDAC_EN);
1622 /* Disable short Frame Sync detection logic */
1623 regmap_update_bits(regmap, NAU8821_R1E_LEFT_TIME_SLOT,
1624 NAU8821_DIS_FS_SHORT_DET, NAU8821_DIS_FS_SHORT_DET);
1625 /* Disable Boost Driver, Automatic Short circuit protection enable */
1626 regmap_update_bits(regmap, NAU8821_R76_BOOST,
1627 NAU8821_PRECHARGE_DIS | NAU8821_HP_BOOST_DIS |
1628 NAU8821_HP_BOOST_G_DIS | NAU8821_SHORT_SHUTDOWN_EN,
1629 NAU8821_PRECHARGE_DIS | NAU8821_HP_BOOST_DIS |
1630 NAU8821_HP_BOOST_G_DIS | NAU8821_SHORT_SHUTDOWN_EN);
1631 /* Class G timer 64ms */
1632 regmap_update_bits(regmap, NAU8821_R4B_CLASSG_CTRL,
1633 NAU8821_CLASSG_TIMER_MASK,
1634 0x20 << NAU8821_CLASSG_TIMER_SFT);
1635 /* Class AB bias current to 2x, DAC Capacitor enable MSB/LSB */
1636 regmap_update_bits(regmap, NAU8821_R6A_ANALOG_CONTROL_2,
1637 NAU8821_HP_NON_CLASSG_CURRENT_2xADJ |
1638 NAU8821_DAC_CAPACITOR_MSB | NAU8821_DAC_CAPACITOR_LSB,
1639 NAU8821_HP_NON_CLASSG_CURRENT_2xADJ |
1640 NAU8821_DAC_CAPACITOR_MSB | NAU8821_DAC_CAPACITOR_LSB);
1641 /* Disable DACR/L power */
1642 regmap_update_bits(regmap, NAU8821_R80_CHARGE_PUMP,
1643 NAU8821_POWER_DOWN_DACR | NAU8821_POWER_DOWN_DACL, 0);
1644 /* DAC clock delay 2ns, VREF */
1645 regmap_update_bits(regmap, NAU8821_R73_RDAC,
1646 NAU8821_DAC_CLK_DELAY_MASK | NAU8821_DAC_VREF_MASK,
1647 (0x2 << NAU8821_DAC_CLK_DELAY_SFT) |
1648 (0x3 << NAU8821_DAC_VREF_SFT));
1649
1650 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS,
1651 NAU8821_MICBIAS_VOLTAGE_MASK, nau8821->micbias_voltage);
1652 /* Default oversampling/decimations settings are unusable
1653 * (audible hiss). Set it to something better.
1654 */
1655 regmap_update_bits(regmap, NAU8821_R2B_ADC_RATE,
1656 NAU8821_ADC_SYNC_DOWN_MASK, NAU8821_ADC_SYNC_DOWN_64);
1657 regmap_update_bits(regmap, NAU8821_R2C_DAC_CTRL1,
1658 NAU8821_DAC_OVERSAMPLE_MASK, NAU8821_DAC_OVERSAMPLE_64);
1659}
1660
1661static int nau8821_setup_irq(struct nau8821 *nau8821)
1662{
1663 struct regmap *regmap = nau8821->regmap;
1664
1665 /* Jack detection */
1666 regmap_update_bits(regmap, NAU8821_R1A_GPIO12_CTRL,
1667 NAU8821_JKDET_OUTPUT_EN,
1668 nau8821->jkdet_enable ? 0 : NAU8821_JKDET_OUTPUT_EN);
1669 regmap_update_bits(regmap, NAU8821_R1A_GPIO12_CTRL,
1670 NAU8821_JKDET_PULL_EN,
1671 nau8821->jkdet_pull_enable ? 0 : NAU8821_JKDET_PULL_EN);
1672 regmap_update_bits(regmap, NAU8821_R1A_GPIO12_CTRL,
1673 NAU8821_JKDET_PULL_UP,
1674 nau8821->jkdet_pull_up ? NAU8821_JKDET_PULL_UP : 0);
1675 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
1676 NAU8821_JACK_POLARITY,
1677 /* jkdet_polarity - 1 is for active-low */
1678 nau8821->jkdet_polarity ? 0 : NAU8821_JACK_POLARITY);
1679 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
1680 NAU8821_JACK_INSERT_DEBOUNCE_MASK,
1681 nau8821->jack_insert_debounce <<
1682 NAU8821_JACK_INSERT_DEBOUNCE_SFT);
1683 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
1684 NAU8821_JACK_EJECT_DEBOUNCE_MASK,
1685 nau8821->jack_eject_debounce <<
1686 NAU8821_JACK_EJECT_DEBOUNCE_SFT);
1687 /* Pull up IRQ pin */
1688 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK,
1689 NAU8821_IRQ_PIN_PULL_UP | NAU8821_IRQ_PIN_PULL_EN |
1690 NAU8821_IRQ_OUTPUT_EN, NAU8821_IRQ_PIN_PULL_UP |
1691 NAU8821_IRQ_PIN_PULL_EN | NAU8821_IRQ_OUTPUT_EN);
1692 /* Disable interruption before codec initiation done */
1693 /* Mask unneeded IRQs: 1 - disable, 0 - enable */
1694 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 0x3f5, 0x3f5);
1695
1696 return 0;
1697}
1698
7325ed4d 1699static int nau8821_i2c_probe(struct i2c_client *i2c)
aab1ad11
SL		 1700{
1701 struct device *dev = &i2c->dev;
1702 struct nau8821 *nau8821 = dev_get_platdata(&i2c->dev);
1703 int ret, value;
1704
1705 if (!nau8821) {
1706 nau8821 = devm_kzalloc(dev, sizeof(*nau8821), GFP_KERNEL);
1707 if (!nau8821)
1708 return -ENOMEM;
1709 nau8821_read_device_properties(dev, nau8821);
1710 }
1711 i2c_set_clientdata(i2c, nau8821);
1712
1713 nau8821->regmap = devm_regmap_init_i2c(i2c, &nau8821_regmap_config);
1714 if (IS_ERR(nau8821->regmap))
1715 return PTR_ERR(nau8821->regmap);
1716
1717 nau8821->dev = dev;
1718 nau8821->irq = i2c->irq;
1719 nau8821_print_device_properties(nau8821);
1720
1721 nau8821_reset_chip(nau8821->regmap);
1722 ret = regmap_read(nau8821->regmap, NAU8821_R58_I2C_DEVICE_ID, &value);
1723 if (ret) {
1724 dev_err(dev, "Failed to read device id (%d)\n", ret);
1725 return ret;
1726 }
1727 nau8821_init_regs(nau8821);
1728
1729 if (i2c->irq)
1730 nau8821_setup_irq(nau8821);
1731
1732 ret = devm_snd_soc_register_component(&i2c->dev,
1733 &nau8821_component_driver, &nau8821_dai, 1);
1734
1735 return ret;
1736}
1737
aab1ad11
SL		 1738static const struct i2c_device_id nau8821_i2c_ids[] = {
1739 { "nau8821", 0 },
1740 { }
1741};
1742MODULE_DEVICE_TABLE(i2c, nau8821_i2c_ids);
1743
1744#ifdef CONFIG_OF
1745static const struct of_device_id nau8821_of_ids[] = {
1746 { .compatible = "nuvoton,nau8821", },
1747 {}
1748};
1749MODULE_DEVICE_TABLE(of, nau8821_of_ids);
1750#endif
1751
1752#ifdef CONFIG_ACPI
1753static const struct acpi_device_id nau8821_acpi_match[] = {
1754 { "NVTN2020", 0 },
1755 {},
1756};
1757MODULE_DEVICE_TABLE(acpi, nau8821_acpi_match);
1758#endif
1759
1760static struct i2c_driver nau8821_driver = {
1761 .driver = {
1762 .name = "nau8821",
1763 .of_match_table = of_match_ptr(nau8821_of_ids),
1764 .acpi_match_table = ACPI_PTR(nau8821_acpi_match),
1765 },
7325ed4d 1766 .probe_new = nau8821_i2c_probe,
aab1ad11
SL		 1767 .id_table = nau8821_i2c_ids,
1768};
1769module_i2c_driver(nau8821_driver);
1770
1771MODULE_DESCRIPTION("ASoC nau8821 driver");
1772MODULE_AUTHOR("John Hsu <kchsu0@nuvoton.com>");
1773MODULE_AUTHOR("Seven Lee <wtli@nuvoton.com>");
1774MODULE_LICENSE("GPL");
Michael's Linux tree.