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ASoC: rt5645: Remove the incorrect setting of the JD mode
[people/ms/linux.git] / sound / soc / codecs / rt5645.c
CommitLineData
1319b2f6
OC		 1/*
2 * rt5645.c -- RT5645 ALSA SoC audio codec driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/platform_device.h>
19#include <linux/spi/spi.h>
f3fa1bbd 20#include <linux/gpio.h>
baf2a0e1 21#include <linux/gpio/consumer.h>
3168c201 22#include <linux/acpi.h>
78c34fd4 23#include <linux/dmi.h>
9fc114c5 24#include <linux/regulator/consumer.h>
1319b2f6
OC		 25#include <sound/core.h>
26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/jack.h>
29#include <sound/soc.h>
30#include <sound/soc-dapm.h>
31#include <sound/initval.h>
32#include <sound/tlv.h>
33
49ef7925 34#include "rl6231.h"
1319b2f6
OC		 35#include "rt5645.h"
36
37#define RT5645_DEVICE_ID 0x6308
5c4ca99d 38#define RT5650_DEVICE_ID 0x6419
1319b2f6
OC		 39
40#define RT5645_PR_RANGE_BASE (0xff + 1)
41#define RT5645_PR_SPACING 0x100
42
43#define RT5645_PR_BASE (RT5645_PR_RANGE_BASE + (0 * RT5645_PR_SPACING))
44
45static const struct regmap_range_cfg rt5645_ranges[] = {
46 {
47 .name = "PR",
48 .range_min = RT5645_PR_BASE,
49 .range_max = RT5645_PR_BASE + 0xf8,
50 .selector_reg = RT5645_PRIV_INDEX,
51 .selector_mask = 0xff,
52 .selector_shift = 0x0,
53 .window_start = RT5645_PRIV_DATA,
54 .window_len = 0x1,
55 },
56};
57
58static const struct reg_default init_list[] = {
59 {RT5645_PR_BASE + 0x3d, 0x3600},
4809b96e
OC		 60 {RT5645_PR_BASE + 0x1c, 0xfd20},
61 {RT5645_PR_BASE + 0x20, 0x611f},
62 {RT5645_PR_BASE + 0x21, 0x4040},
63 {RT5645_PR_BASE + 0x23, 0x0004},
1319b2f6
OC		 64};
65#define RT5645_INIT_REG_LEN ARRAY_SIZE(init_list)
66
5c4ca99d
BL		 67static const struct reg_default rt5650_init_list[] = {
68 {0xf6, 0x0100},
69};
70
1319b2f6
OC		 71static const struct reg_default rt5645_reg[] = {
72 { 0x00, 0x0000 },
73 { 0x01, 0xc8c8 },
74 { 0x02, 0xc8c8 },
75 { 0x03, 0xc8c8 },
76 { 0x0a, 0x0002 },
77 { 0x0b, 0x2827 },
78 { 0x0c, 0xe000 },
79 { 0x0d, 0x0000 },
80 { 0x0e, 0x0000 },
81 { 0x0f, 0x0808 },
82 { 0x14, 0x3333 },
83 { 0x16, 0x4b00 },
84 { 0x18, 0x018b },
85 { 0x19, 0xafaf },
86 { 0x1a, 0xafaf },
87 { 0x1b, 0x0001 },
88 { 0x1c, 0x2f2f },
89 { 0x1d, 0x2f2f },
90 { 0x1e, 0x0000 },
91 { 0x20, 0x0000 },
92 { 0x27, 0x7060 },
93 { 0x28, 0x7070 },
94 { 0x29, 0x8080 },
95 { 0x2a, 0x5656 },
96 { 0x2b, 0x5454 },
97 { 0x2c, 0xaaa0 },
5c4ca99d 98 { 0x2d, 0x0000 },
1319b2f6
OC		 99 { 0x2f, 0x1002 },
100 { 0x31, 0x5000 },
101 { 0x32, 0x0000 },
102 { 0x33, 0x0000 },
103 { 0x34, 0x0000 },
104 { 0x35, 0x0000 },
105 { 0x3b, 0x0000 },
106 { 0x3c, 0x007f },
107 { 0x3d, 0x0000 },
108 { 0x3e, 0x007f },
109 { 0x3f, 0x0000 },
110 { 0x40, 0x001f },
111 { 0x41, 0x0000 },
112 { 0x42, 0x001f },
113 { 0x45, 0x6000 },
114 { 0x46, 0x003e },
115 { 0x47, 0x003e },
116 { 0x48, 0xf807 },
117 { 0x4a, 0x0004 },
118 { 0x4d, 0x0000 },
119 { 0x4e, 0x0000 },
120 { 0x4f, 0x01ff },
121 { 0x50, 0x0000 },
122 { 0x51, 0x0000 },
123 { 0x52, 0x01ff },
124 { 0x53, 0xf000 },
125 { 0x56, 0x0111 },
126 { 0x57, 0x0064 },
127 { 0x58, 0xef0e },
128 { 0x59, 0xf0f0 },
129 { 0x5a, 0xef0e },
130 { 0x5b, 0xf0f0 },
131 { 0x5c, 0xef0e },
132 { 0x5d, 0xf0f0 },
133 { 0x5e, 0xf000 },
134 { 0x5f, 0x0000 },
135 { 0x61, 0x0300 },
136 { 0x62, 0x0000 },
137 { 0x63, 0x00c2 },
138 { 0x64, 0x0000 },
139 { 0x65, 0x0000 },
140 { 0x66, 0x0000 },
141 { 0x6a, 0x0000 },
142 { 0x6c, 0x0aaa },
143 { 0x70, 0x8000 },
144 { 0x71, 0x8000 },
145 { 0x72, 0x8000 },
146 { 0x73, 0x7770 },
147 { 0x74, 0x3e00 },
148 { 0x75, 0x2409 },
149 { 0x76, 0x000a },
150 { 0x77, 0x0c00 },
151 { 0x78, 0x0000 },
df078d29 152 { 0x79, 0x0123 },
1319b2f6
OC		 153 { 0x80, 0x0000 },
154 { 0x81, 0x0000 },
155 { 0x82, 0x0000 },
156 { 0x83, 0x0000 },
157 { 0x84, 0x0000 },
158 { 0x85, 0x0000 },
159 { 0x8a, 0x0000 },
160 { 0x8e, 0x0004 },
161 { 0x8f, 0x1100 },
162 { 0x90, 0x0646 },
163 { 0x91, 0x0c06 },
164 { 0x93, 0x0000 },
165 { 0x94, 0x0200 },
166 { 0x95, 0x0000 },
167 { 0x9a, 0x2184 },
168 { 0x9b, 0x010a },
169 { 0x9c, 0x0aea },
170 { 0x9d, 0x000c },
171 { 0x9e, 0x0400 },
172 { 0xa0, 0xa0a8 },
173 { 0xa1, 0x0059 },
174 { 0xa2, 0x0001 },
175 { 0xae, 0x6000 },
176 { 0xaf, 0x0000 },
177 { 0xb0, 0x6000 },
178 { 0xb1, 0x0000 },
179 { 0xb2, 0x0000 },
180 { 0xb3, 0x001f },
181 { 0xb4, 0x020c },
182 { 0xb5, 0x1f00 },
183 { 0xb6, 0x0000 },
184 { 0xbb, 0x0000 },
185 { 0xbc, 0x0000 },
186 { 0xbd, 0x0000 },
187 { 0xbe, 0x0000 },
188 { 0xbf, 0x3100 },
189 { 0xc0, 0x0000 },
190 { 0xc1, 0x0000 },
191 { 0xc2, 0x0000 },
192 { 0xc3, 0x2000 },
193 { 0xcd, 0x0000 },
194 { 0xce, 0x0000 },
195 { 0xcf, 0x1813 },
196 { 0xd0, 0x0690 },
197 { 0xd1, 0x1c17 },
198 { 0xd3, 0xb320 },
199 { 0xd4, 0x0000 },
200 { 0xd6, 0x0400 },
201 { 0xd9, 0x0809 },
202 { 0xda, 0x0000 },
203 { 0xdb, 0x0003 },
204 { 0xdc, 0x0049 },
205 { 0xdd, 0x001b },
5c4ca99d
BL		 206 { 0xdf, 0x0008 },
207 { 0xe0, 0x4000 },
1319b2f6
OC		 208 { 0xe6, 0x8000 },
209 { 0xe7, 0x0200 },
210 { 0xec, 0xb300 },
211 { 0xed, 0x0000 },
212 { 0xf0, 0x001f },
213 { 0xf1, 0x020c },
214 { 0xf2, 0x1f00 },
215 { 0xf3, 0x0000 },
216 { 0xf4, 0x4000 },
217 { 0xf8, 0x0000 },
218 { 0xf9, 0x0000 },
219 { 0xfa, 0x2060 },
220 { 0xfb, 0x4040 },
221 { 0xfc, 0x0000 },
222 { 0xfd, 0x0002 },
223 { 0xfe, 0x10ec },
224 { 0xff, 0x6308 },
225};
226
9fc114c5
KC		 227static const char *const rt5645_supply_names[] = {
228 "avdd",
229 "cpvdd",
230};
231
232struct rt5645_priv {
233 struct snd_soc_codec *codec;
234 struct rt5645_platform_data pdata;
235 struct regmap *regmap;
236 struct i2c_client *i2c;
237 struct gpio_desc *gpiod_hp_det;
238 struct snd_soc_jack *hp_jack;
239 struct snd_soc_jack *mic_jack;
240 struct snd_soc_jack *btn_jack;
241 struct delayed_work jack_detect_work;
242 struct regulator_bulk_data supplies[ARRAY_SIZE(rt5645_supply_names)];
243
244 int codec_type;
245 int sysclk;
246 int sysclk_src;
247 int lrck[RT5645_AIFS];
248 int bclk[RT5645_AIFS];
249 int master[RT5645_AIFS];
250
251 int pll_src;
252 int pll_in;
253 int pll_out;
254
255 int jack_type;
256 bool en_button_func;
588cd850 257 bool hp_on;
9fc114c5
KC		 258};
259
1319b2f6
OC		 260static int rt5645_reset(struct snd_soc_codec *codec)
261{
262 return snd_soc_write(codec, RT5645_RESET, 0);
263}
264
265static bool rt5645_volatile_register(struct device *dev, unsigned int reg)
266{
267 int i;
268
269 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
270 if (reg >= rt5645_ranges[i].range_min &&
271 reg <= rt5645_ranges[i].range_max) {
272 return true;
273 }
274 }
275
276 switch (reg) {
277 case RT5645_RESET:
278 case RT5645_PRIV_DATA:
279 case RT5645_IN1_CTRL1:
280 case RT5645_IN1_CTRL2:
281 case RT5645_IN1_CTRL3:
282 case RT5645_A_JD_CTRL1:
283 case RT5645_ADC_EQ_CTRL1:
284 case RT5645_EQ_CTRL1:
285 case RT5645_ALC_CTRL_1:
286 case RT5645_IRQ_CTRL2:
287 case RT5645_IRQ_CTRL3:
288 case RT5645_INT_IRQ_ST:
289 case RT5645_IL_CMD:
5c4ca99d 290 case RT5650_4BTN_IL_CMD1:
1319b2f6
OC		 291 case RT5645_VENDOR_ID:
292 case RT5645_VENDOR_ID1:
293 case RT5645_VENDOR_ID2:
71bfa9b4 294 return true;
1319b2f6 295 default:
71bfa9b4 296 return false;
1319b2f6
OC		 297 }
298}
299
300static bool rt5645_readable_register(struct device *dev, unsigned int reg)
301{
302 int i;
303
304 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
305 if (reg >= rt5645_ranges[i].range_min &&
306 reg <= rt5645_ranges[i].range_max) {
307 return true;
308 }
309 }
310
311 switch (reg) {
312 case RT5645_RESET:
313 case RT5645_SPK_VOL:
314 case RT5645_HP_VOL:
315 case RT5645_LOUT1:
316 case RT5645_IN1_CTRL1:
317 case RT5645_IN1_CTRL2:
318 case RT5645_IN1_CTRL3:
319 case RT5645_IN2_CTRL:
320 case RT5645_INL1_INR1_VOL:
321 case RT5645_SPK_FUNC_LIM:
322 case RT5645_ADJ_HPF_CTRL:
323 case RT5645_DAC1_DIG_VOL:
324 case RT5645_DAC2_DIG_VOL:
325 case RT5645_DAC_CTRL:
326 case RT5645_STO1_ADC_DIG_VOL:
327 case RT5645_MONO_ADC_DIG_VOL:
328 case RT5645_ADC_BST_VOL1:
329 case RT5645_ADC_BST_VOL2:
330 case RT5645_STO1_ADC_MIXER:
331 case RT5645_MONO_ADC_MIXER:
332 case RT5645_AD_DA_MIXER:
333 case RT5645_STO_DAC_MIXER:
334 case RT5645_MONO_DAC_MIXER:
335 case RT5645_DIG_MIXER:
5c4ca99d 336 case RT5650_A_DAC_SOUR:
1319b2f6
OC		 337 case RT5645_DIG_INF1_DATA:
338 case RT5645_PDM_OUT_CTRL:
339 case RT5645_REC_L1_MIXER:
340 case RT5645_REC_L2_MIXER:
341 case RT5645_REC_R1_MIXER:
342 case RT5645_REC_R2_MIXER:
343 case RT5645_HPMIXL_CTRL:
344 case RT5645_HPOMIXL_CTRL:
345 case RT5645_HPMIXR_CTRL:
346 case RT5645_HPOMIXR_CTRL:
347 case RT5645_HPO_MIXER:
348 case RT5645_SPK_L_MIXER:
349 case RT5645_SPK_R_MIXER:
350 case RT5645_SPO_MIXER:
351 case RT5645_SPO_CLSD_RATIO:
352 case RT5645_OUT_L1_MIXER:
353 case RT5645_OUT_R1_MIXER:
354 case RT5645_OUT_L_GAIN1:
355 case RT5645_OUT_L_GAIN2:
356 case RT5645_OUT_R_GAIN1:
357 case RT5645_OUT_R_GAIN2:
358 case RT5645_LOUT_MIXER:
359 case RT5645_HAPTIC_CTRL1:
360 case RT5645_HAPTIC_CTRL2:
361 case RT5645_HAPTIC_CTRL3:
362 case RT5645_HAPTIC_CTRL4:
363 case RT5645_HAPTIC_CTRL5:
364 case RT5645_HAPTIC_CTRL6:
365 case RT5645_HAPTIC_CTRL7:
366 case RT5645_HAPTIC_CTRL8:
367 case RT5645_HAPTIC_CTRL9:
368 case RT5645_HAPTIC_CTRL10:
369 case RT5645_PWR_DIG1:
370 case RT5645_PWR_DIG2:
371 case RT5645_PWR_ANLG1:
372 case RT5645_PWR_ANLG2:
373 case RT5645_PWR_MIXER:
374 case RT5645_PWR_VOL:
375 case RT5645_PRIV_INDEX:
376 case RT5645_PRIV_DATA:
377 case RT5645_I2S1_SDP:
378 case RT5645_I2S2_SDP:
379 case RT5645_ADDA_CLK1:
380 case RT5645_ADDA_CLK2:
381 case RT5645_DMIC_CTRL1:
382 case RT5645_DMIC_CTRL2:
383 case RT5645_TDM_CTRL_1:
384 case RT5645_TDM_CTRL_2:
df078d29 385 case RT5645_TDM_CTRL_3:
1fcb76db 386 case RT5650_TDM_CTRL_4:
1319b2f6
OC		 387 case RT5645_GLB_CLK:
388 case RT5645_PLL_CTRL1:
389 case RT5645_PLL_CTRL2:
390 case RT5645_ASRC_1:
391 case RT5645_ASRC_2:
392 case RT5645_ASRC_3:
393 case RT5645_ASRC_4:
394 case RT5645_DEPOP_M1:
395 case RT5645_DEPOP_M2:
396 case RT5645_DEPOP_M3:
397 case RT5645_MICBIAS:
398 case RT5645_A_JD_CTRL1:
399 case RT5645_VAD_CTRL4:
400 case RT5645_CLSD_OUT_CTRL:
401 case RT5645_ADC_EQ_CTRL1:
402 case RT5645_ADC_EQ_CTRL2:
403 case RT5645_EQ_CTRL1:
404 case RT5645_EQ_CTRL2:
405 case RT5645_ALC_CTRL_1:
406 case RT5645_ALC_CTRL_2:
407 case RT5645_ALC_CTRL_3:
408 case RT5645_ALC_CTRL_4:
409 case RT5645_ALC_CTRL_5:
410 case RT5645_JD_CTRL:
411 case RT5645_IRQ_CTRL1:
412 case RT5645_IRQ_CTRL2:
413 case RT5645_IRQ_CTRL3:
414 case RT5645_INT_IRQ_ST:
415 case RT5645_GPIO_CTRL1:
416 case RT5645_GPIO_CTRL2:
417 case RT5645_GPIO_CTRL3:
418 case RT5645_BASS_BACK:
419 case RT5645_MP3_PLUS1:
420 case RT5645_MP3_PLUS2:
421 case RT5645_ADJ_HPF1:
422 case RT5645_ADJ_HPF2:
423 case RT5645_HP_CALIB_AMP_DET:
424 case RT5645_SV_ZCD1:
425 case RT5645_SV_ZCD2:
426 case RT5645_IL_CMD:
427 case RT5645_IL_CMD2:
428 case RT5645_IL_CMD3:
5c4ca99d
BL		 429 case RT5650_4BTN_IL_CMD1:
430 case RT5650_4BTN_IL_CMD2:
1319b2f6
OC		 431 case RT5645_DRC1_HL_CTRL1:
432 case RT5645_DRC2_HL_CTRL1:
433 case RT5645_ADC_MONO_HP_CTRL1:
434 case RT5645_ADC_MONO_HP_CTRL2:
435 case RT5645_DRC2_CTRL1:
436 case RT5645_DRC2_CTRL2:
437 case RT5645_DRC2_CTRL3:
438 case RT5645_DRC2_CTRL4:
439 case RT5645_DRC2_CTRL5:
440 case RT5645_JD_CTRL3:
441 case RT5645_JD_CTRL4:
442 case RT5645_GEN_CTRL1:
443 case RT5645_GEN_CTRL2:
444 case RT5645_GEN_CTRL3:
445 case RT5645_VENDOR_ID:
446 case RT5645_VENDOR_ID1:
447 case RT5645_VENDOR_ID2:
71bfa9b4 448 return true;
1319b2f6 449 default:
71bfa9b4 450 return false;
1319b2f6
OC		 451 }
452}
453
454static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
177e1e1f 455static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
1319b2f6 456static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
177e1e1f 457static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
1319b2f6
OC		 458static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
459
460/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
461static unsigned int bst_tlv[] = {
462 TLV_DB_RANGE_HEAD(7),
463 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
464 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
465 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
466 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
467 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
468 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
469 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
470};
471
1319b2f6
OC		 472static const struct snd_kcontrol_new rt5645_snd_controls[] = {
473 /* Speaker Output Volume */
474 SOC_DOUBLE("Speaker Channel Switch", RT5645_SPK_VOL,
475 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
476 SOC_DOUBLE_TLV("Speaker Playback Volume", RT5645_SPK_VOL,
477 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
478
479 /* Headphone Output Volume */
692768c4 480 SOC_DOUBLE("Headphone Channel Switch", RT5645_HP_VOL,
1319b2f6 481 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
692768c4 482 SOC_DOUBLE_TLV("Headphone Playback Volume", RT5645_HP_VOL,
1319b2f6
OC		 483 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
484
485 /* OUTPUT Control */
486 SOC_DOUBLE("OUT Playback Switch", RT5645_LOUT1,
487 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
488 SOC_DOUBLE("OUT Channel Switch", RT5645_LOUT1,
489 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
490 SOC_DOUBLE_TLV("OUT Playback Volume", RT5645_LOUT1,
491 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
492
493 /* DAC Digital Volume */
494 SOC_DOUBLE("DAC2 Playback Switch", RT5645_DAC_CTRL,
495 RT5645_M_DAC_L2_VOL_SFT, RT5645_M_DAC_R2_VOL_SFT, 1, 1),
496 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5645_DAC1_DIG_VOL,
177e1e1f 497 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
1319b2f6 498 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5645_DAC2_DIG_VOL,
177e1e1f 499 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
1319b2f6
OC		 500
501 /* IN1/IN2 Control */
502 SOC_SINGLE_TLV("IN1 Boost", RT5645_IN1_CTRL1,
503 RT5645_BST_SFT1, 8, 0, bst_tlv),
504 SOC_SINGLE_TLV("IN2 Boost", RT5645_IN2_CTRL,
505 RT5645_BST_SFT2, 8, 0, bst_tlv),
506
507 /* INL/INR Volume Control */
508 SOC_DOUBLE_TLV("IN Capture Volume", RT5645_INL1_INR1_VOL,
509 RT5645_INL_VOL_SFT, RT5645_INR_VOL_SFT, 31, 1, in_vol_tlv),
510
511 /* ADC Digital Volume Control */
512 SOC_DOUBLE("ADC Capture Switch", RT5645_STO1_ADC_DIG_VOL,
513 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
514 SOC_DOUBLE_TLV("ADC Capture Volume", RT5645_STO1_ADC_DIG_VOL,
177e1e1f 515 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
1319b2f6
OC		 516 SOC_DOUBLE("Mono ADC Capture Switch", RT5645_MONO_ADC_DIG_VOL,
517 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
518 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5645_MONO_ADC_DIG_VOL,
177e1e1f 519 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
1319b2f6
OC		 520
521 /* ADC Boost Volume Control */
522 SOC_DOUBLE_TLV("STO1 ADC Boost Gain", RT5645_ADC_BST_VOL1,
523 RT5645_STO1_ADC_L_BST_SFT, RT5645_STO1_ADC_R_BST_SFT, 3, 0,
524 adc_bst_tlv),
525 SOC_DOUBLE_TLV("STO2 ADC Boost Gain", RT5645_ADC_BST_VOL1,
526 RT5645_STO2_ADC_L_BST_SFT, RT5645_STO2_ADC_R_BST_SFT, 3, 0,
527 adc_bst_tlv),
528
529 /* I2S2 function select */
530 SOC_SINGLE("I2S2 Func Switch", RT5645_GPIO_CTRL1, RT5645_I2S2_SEL_SFT,
531 1, 1),
1319b2f6
OC		 532};
533
534/**
535 * set_dmic_clk - Set parameter of dmic.
536 *
537 * @w: DAPM widget.
538 * @kcontrol: The kcontrol of this widget.
539 * @event: Event id.
540 *
1319b2f6
OC		 541 */
542static int set_dmic_clk(struct snd_soc_dapm_widget *w,
543 struct snd_kcontrol *kcontrol, int event)
544{
c5f596cb 545 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1319b2f6 546 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
49ef7925
OC		 547 int idx = -EINVAL;
548
549 idx = rl6231_calc_dmic_clk(rt5645->sysclk);
1319b2f6
OC		 550
551 if (idx < 0)
552 dev_err(codec->dev, "Failed to set DMIC clock\n");
553 else
554 snd_soc_update_bits(codec, RT5645_DMIC_CTRL1,
555 RT5645_DMIC_CLK_MASK, idx << RT5645_DMIC_CLK_SFT);
556 return idx;
557}
558
559static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
560 struct snd_soc_dapm_widget *sink)
561{
c5f596cb 562 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
1319b2f6
OC		 563 unsigned int val;
564
c5f596cb 565 val = snd_soc_read(codec, RT5645_GLB_CLK);
1319b2f6
OC		 566 val &= RT5645_SCLK_SRC_MASK;
567 if (val == RT5645_SCLK_SRC_PLL1)
568 return 1;
569 else
570 return 0;
571}
572
9e268353
BL		 573static int is_using_asrc(struct snd_soc_dapm_widget *source,
574 struct snd_soc_dapm_widget *sink)
575{
c5f596cb 576 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
9e268353
BL		 577 unsigned int reg, shift, val;
578
579 switch (source->shift) {
580 case 0:
581 reg = RT5645_ASRC_3;
582 shift = 0;
583 break;
584 case 1:
585 reg = RT5645_ASRC_3;
586 shift = 4;
587 break;
588 case 3:
589 reg = RT5645_ASRC_2;
590 shift = 0;
591 break;
592 case 8:
593 reg = RT5645_ASRC_2;
594 shift = 4;
595 break;
596 case 9:
597 reg = RT5645_ASRC_2;
598 shift = 8;
599 break;
600 case 10:
601 reg = RT5645_ASRC_2;
602 shift = 12;
603 break;
604 default:
605 return 0;
606 }
607
c5f596cb 608 val = (snd_soc_read(codec, reg) >> shift) & 0xf;
9e268353
BL		 609 switch (val) {
610 case 1:
611 case 2:
612 case 3:
613 case 4:
614 return 1;
615 default:
616 return 0;
617 }
618
619}
620
79080a8b
FY		 621/**
622 * rt5645_sel_asrc_clk_src - select ASRC clock source for a set of filters
623 * @codec: SoC audio codec device.
624 * @filter_mask: mask of filters.
625 * @clk_src: clock source
626 *
627 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5645 can
628 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
629 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
630 * ASRC function will track i2s clock and generate a corresponding system clock
631 * for codec. This function provides an API to select the clock source for a
632 * set of filters specified by the mask. And the codec driver will turn on ASRC
633 * for these filters if ASRC is selected as their clock source.
634 */
635int rt5645_sel_asrc_clk_src(struct snd_soc_codec *codec,
636 unsigned int filter_mask, unsigned int clk_src)
637{
638 unsigned int asrc2_mask = 0;
639 unsigned int asrc2_value = 0;
640 unsigned int asrc3_mask = 0;
641 unsigned int asrc3_value = 0;
642
643 switch (clk_src) {
644 case RT5645_CLK_SEL_SYS:
645 case RT5645_CLK_SEL_I2S1_ASRC:
646 case RT5645_CLK_SEL_I2S2_ASRC:
647 case RT5645_CLK_SEL_SYS2:
648 break;
649
650 default:
651 return -EINVAL;
652 }
653
654 if (filter_mask & RT5645_DA_STEREO_FILTER) {
655 asrc2_mask |= RT5645_DA_STO_CLK_SEL_MASK;
656 asrc2_value = (asrc2_value & ~RT5645_DA_STO_CLK_SEL_MASK)
657 | (clk_src << RT5645_DA_STO_CLK_SEL_SFT);
658 }
659
660 if (filter_mask & RT5645_DA_MONO_L_FILTER) {
661 asrc2_mask |= RT5645_DA_MONOL_CLK_SEL_MASK;
662 asrc2_value = (asrc2_value & ~RT5645_DA_MONOL_CLK_SEL_MASK)
663 | (clk_src << RT5645_DA_MONOL_CLK_SEL_SFT);
664 }
665
666 if (filter_mask & RT5645_DA_MONO_R_FILTER) {
667 asrc2_mask |= RT5645_DA_MONOR_CLK_SEL_MASK;
668 asrc2_value = (asrc2_value & ~RT5645_DA_MONOR_CLK_SEL_MASK)
669 | (clk_src << RT5645_DA_MONOR_CLK_SEL_SFT);
670 }
671
672 if (filter_mask & RT5645_AD_STEREO_FILTER) {
673 asrc2_mask |= RT5645_AD_STO1_CLK_SEL_MASK;
674 asrc2_value = (asrc2_value & ~RT5645_AD_STO1_CLK_SEL_MASK)
675 | (clk_src << RT5645_AD_STO1_CLK_SEL_SFT);
676 }
677
678 if (filter_mask & RT5645_AD_MONO_L_FILTER) {
679 asrc3_mask |= RT5645_AD_MONOL_CLK_SEL_MASK;
680 asrc3_value = (asrc3_value & ~RT5645_AD_MONOL_CLK_SEL_MASK)
681 | (clk_src << RT5645_AD_MONOL_CLK_SEL_SFT);
682 }
683
684 if (filter_mask & RT5645_AD_MONO_R_FILTER) {
685 asrc3_mask |= RT5645_AD_MONOR_CLK_SEL_MASK;
686 asrc3_value = (asrc3_value & ~RT5645_AD_MONOR_CLK_SEL_MASK)
687 | (clk_src << RT5645_AD_MONOR_CLK_SEL_SFT);
688 }
689
690 if (asrc2_mask)
691 snd_soc_update_bits(codec, RT5645_ASRC_2,
692 asrc2_mask, asrc2_value);
693
694 if (asrc3_mask)
695 snd_soc_update_bits(codec, RT5645_ASRC_3,
696 asrc3_mask, asrc3_value);
697
698 return 0;
699}
700EXPORT_SYMBOL_GPL(rt5645_sel_asrc_clk_src);
701
1319b2f6
OC		 702/* Digital Mixer */
703static const struct snd_kcontrol_new rt5645_sto1_adc_l_mix[] = {
704 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
705 RT5645_M_ADC_L1_SFT, 1, 1),
706 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
707 RT5645_M_ADC_L2_SFT, 1, 1),
708};
709
710static const struct snd_kcontrol_new rt5645_sto1_adc_r_mix[] = {
711 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
712 RT5645_M_ADC_R1_SFT, 1, 1),
713 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
714 RT5645_M_ADC_R2_SFT, 1, 1),
715};
716
717static const struct snd_kcontrol_new rt5645_mono_adc_l_mix[] = {
718 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
719 RT5645_M_MONO_ADC_L1_SFT, 1, 1),
720 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
721 RT5645_M_MONO_ADC_L2_SFT, 1, 1),
722};
723
724static const struct snd_kcontrol_new rt5645_mono_adc_r_mix[] = {
725 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
726 RT5645_M_MONO_ADC_R1_SFT, 1, 1),
727 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
728 RT5645_M_MONO_ADC_R2_SFT, 1, 1),
729};
730
731static const struct snd_kcontrol_new rt5645_dac_l_mix[] = {
732 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
733 RT5645_M_ADCMIX_L_SFT, 1, 1),
734 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_AD_DA_MIXER,
735 RT5645_M_DAC1_L_SFT, 1, 1),
736};
737
738static const struct snd_kcontrol_new rt5645_dac_r_mix[] = {
739 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
740 RT5645_M_ADCMIX_R_SFT, 1, 1),
741 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_AD_DA_MIXER,
742 RT5645_M_DAC1_R_SFT, 1, 1),
743};
744
745static const struct snd_kcontrol_new rt5645_sto_dac_l_mix[] = {
746 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
747 RT5645_M_DAC_L1_SFT, 1, 1),
748 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_STO_DAC_MIXER,
749 RT5645_M_DAC_L2_SFT, 1, 1),
750 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
751 RT5645_M_DAC_R1_STO_L_SFT, 1, 1),
752};
753
754static const struct snd_kcontrol_new rt5645_sto_dac_r_mix[] = {
755 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
756 RT5645_M_DAC_R1_SFT, 1, 1),
757 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_STO_DAC_MIXER,
758 RT5645_M_DAC_R2_SFT, 1, 1),
759 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
760 RT5645_M_DAC_L1_STO_R_SFT, 1, 1),
761};
762
763static const struct snd_kcontrol_new rt5645_mono_dac_l_mix[] = {
764 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_MONO_DAC_MIXER,
765 RT5645_M_DAC_L1_MONO_L_SFT, 1, 1),
766 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
767 RT5645_M_DAC_L2_MONO_L_SFT, 1, 1),
768 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
769 RT5645_M_DAC_R2_MONO_L_SFT, 1, 1),
770};
771
772static const struct snd_kcontrol_new rt5645_mono_dac_r_mix[] = {
773 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_MONO_DAC_MIXER,
774 RT5645_M_DAC_R1_MONO_R_SFT, 1, 1),
775 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
776 RT5645_M_DAC_R2_MONO_R_SFT, 1, 1),
777 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
778 RT5645_M_DAC_L2_MONO_R_SFT, 1, 1),
779};
780
781static const struct snd_kcontrol_new rt5645_dig_l_mix[] = {
782 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5645_DIG_MIXER,
783 RT5645_M_STO_L_DAC_L_SFT, 1, 1),
784 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
785 RT5645_M_DAC_L2_DAC_L_SFT, 1, 1),
786 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
787 RT5645_M_DAC_R2_DAC_L_SFT, 1, 1),
788};
789
790static const struct snd_kcontrol_new rt5645_dig_r_mix[] = {
791 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5645_DIG_MIXER,
792 RT5645_M_STO_R_DAC_R_SFT, 1, 1),
793 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
794 RT5645_M_DAC_R2_DAC_R_SFT, 1, 1),
795 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
796 RT5645_M_DAC_L2_DAC_R_SFT, 1, 1),
797};
798
799/* Analog Input Mixer */
800static const struct snd_kcontrol_new rt5645_rec_l_mix[] = {
801 SOC_DAPM_SINGLE("HPOL Switch", RT5645_REC_L2_MIXER,
802 RT5645_M_HP_L_RM_L_SFT, 1, 1),
803 SOC_DAPM_SINGLE("INL Switch", RT5645_REC_L2_MIXER,
804 RT5645_M_IN_L_RM_L_SFT, 1, 1),
805 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_L2_MIXER,
806 RT5645_M_BST2_RM_L_SFT, 1, 1),
807 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_L2_MIXER,
808 RT5645_M_BST1_RM_L_SFT, 1, 1),
809 SOC_DAPM_SINGLE("OUT MIXL Switch", RT5645_REC_L2_MIXER,
810 RT5645_M_OM_L_RM_L_SFT, 1, 1),
811};
812
813static const struct snd_kcontrol_new rt5645_rec_r_mix[] = {
814 SOC_DAPM_SINGLE("HPOR Switch", RT5645_REC_R2_MIXER,
815 RT5645_M_HP_R_RM_R_SFT, 1, 1),
816 SOC_DAPM_SINGLE("INR Switch", RT5645_REC_R2_MIXER,
817 RT5645_M_IN_R_RM_R_SFT, 1, 1),
818 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_R2_MIXER,
819 RT5645_M_BST2_RM_R_SFT, 1, 1),
820 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_R2_MIXER,
821 RT5645_M_BST1_RM_R_SFT, 1, 1),
822 SOC_DAPM_SINGLE("OUT MIXR Switch", RT5645_REC_R2_MIXER,
823 RT5645_M_OM_R_RM_R_SFT, 1, 1),
824};
825
826static const struct snd_kcontrol_new rt5645_spk_l_mix[] = {
827 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPK_L_MIXER,
828 RT5645_M_DAC_L1_SM_L_SFT, 1, 1),
829 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_SPK_L_MIXER,
830 RT5645_M_DAC_L2_SM_L_SFT, 1, 1),
831 SOC_DAPM_SINGLE("INL Switch", RT5645_SPK_L_MIXER,
832 RT5645_M_IN_L_SM_L_SFT, 1, 1),
833 SOC_DAPM_SINGLE("BST1 Switch", RT5645_SPK_L_MIXER,
834 RT5645_M_BST1_L_SM_L_SFT, 1, 1),
835};
836
837static const struct snd_kcontrol_new rt5645_spk_r_mix[] = {
838 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPK_R_MIXER,
839 RT5645_M_DAC_R1_SM_R_SFT, 1, 1),
840 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_SPK_R_MIXER,
841 RT5645_M_DAC_R2_SM_R_SFT, 1, 1),
842 SOC_DAPM_SINGLE("INR Switch", RT5645_SPK_R_MIXER,
843 RT5645_M_IN_R_SM_R_SFT, 1, 1),
844 SOC_DAPM_SINGLE("BST2 Switch", RT5645_SPK_R_MIXER,
845 RT5645_M_BST2_R_SM_R_SFT, 1, 1),
846};
847
848static const struct snd_kcontrol_new rt5645_out_l_mix[] = {
849 SOC_DAPM_SINGLE("BST1 Switch", RT5645_OUT_L1_MIXER,
850 RT5645_M_BST1_OM_L_SFT, 1, 1),
851 SOC_DAPM_SINGLE("INL Switch", RT5645_OUT_L1_MIXER,
852 RT5645_M_IN_L_OM_L_SFT, 1, 1),
853 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_OUT_L1_MIXER,
854 RT5645_M_DAC_L2_OM_L_SFT, 1, 1),
855 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_OUT_L1_MIXER,
856 RT5645_M_DAC_L1_OM_L_SFT, 1, 1),
857};
858
859static const struct snd_kcontrol_new rt5645_out_r_mix[] = {
860 SOC_DAPM_SINGLE("BST2 Switch", RT5645_OUT_R1_MIXER,
861 RT5645_M_BST2_OM_R_SFT, 1, 1),
862 SOC_DAPM_SINGLE("INR Switch", RT5645_OUT_R1_MIXER,
863 RT5645_M_IN_R_OM_R_SFT, 1, 1),
864 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_OUT_R1_MIXER,
865 RT5645_M_DAC_R2_OM_R_SFT, 1, 1),
866 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_OUT_R1_MIXER,
867 RT5645_M_DAC_R1_OM_R_SFT, 1, 1),
868};
869
870static const struct snd_kcontrol_new rt5645_spo_l_mix[] = {
871 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
872 RT5645_M_DAC_R1_SPM_L_SFT, 1, 1),
873 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPO_MIXER,
874 RT5645_M_DAC_L1_SPM_L_SFT, 1, 1),
875 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
876 RT5645_M_SV_R_SPM_L_SFT, 1, 1),
877 SOC_DAPM_SINGLE("SPKVOL L Switch", RT5645_SPO_MIXER,
878 RT5645_M_SV_L_SPM_L_SFT, 1, 1),
879};
880
881static const struct snd_kcontrol_new rt5645_spo_r_mix[] = {
882 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
883 RT5645_M_DAC_R1_SPM_R_SFT, 1, 1),
884 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
885 RT5645_M_SV_R_SPM_R_SFT, 1, 1),
886};
887
888static const struct snd_kcontrol_new rt5645_hpo_mix[] = {
889 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPO_MIXER,
890 RT5645_M_DAC1_HM_SFT, 1, 1),
891 SOC_DAPM_SINGLE("HPVOL Switch", RT5645_HPO_MIXER,
892 RT5645_M_HPVOL_HM_SFT, 1, 1),
893};
894
895static const struct snd_kcontrol_new rt5645_hpvoll_mix[] = {
896 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXL_CTRL,
897 RT5645_M_DAC1_HV_SFT, 1, 1),
898 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXL_CTRL,
899 RT5645_M_DAC2_HV_SFT, 1, 1),
900 SOC_DAPM_SINGLE("INL Switch", RT5645_HPOMIXL_CTRL,
901 RT5645_M_IN_HV_SFT, 1, 1),
902 SOC_DAPM_SINGLE("BST1 Switch", RT5645_HPOMIXL_CTRL,
903 RT5645_M_BST1_HV_SFT, 1, 1),
904};
905
906static const struct snd_kcontrol_new rt5645_hpvolr_mix[] = {
907 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXR_CTRL,
908 RT5645_M_DAC1_HV_SFT, 1, 1),
909 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXR_CTRL,
910 RT5645_M_DAC2_HV_SFT, 1, 1),
911 SOC_DAPM_SINGLE("INR Switch", RT5645_HPOMIXR_CTRL,
912 RT5645_M_IN_HV_SFT, 1, 1),
913 SOC_DAPM_SINGLE("BST2 Switch", RT5645_HPOMIXR_CTRL,
914 RT5645_M_BST2_HV_SFT, 1, 1),
915};
916
917static const struct snd_kcontrol_new rt5645_lout_mix[] = {
918 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_LOUT_MIXER,
919 RT5645_M_DAC_L1_LM_SFT, 1, 1),
920 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_LOUT_MIXER,
921 RT5645_M_DAC_R1_LM_SFT, 1, 1),
922 SOC_DAPM_SINGLE("OUTMIX L Switch", RT5645_LOUT_MIXER,
923 RT5645_M_OV_L_LM_SFT, 1, 1),
924 SOC_DAPM_SINGLE("OUTMIX R Switch", RT5645_LOUT_MIXER,
925 RT5645_M_OV_R_LM_SFT, 1, 1),
926};
927
928/*DAC1 L/R source*/ /* MX-29 [9:8] [11:10] */
929static const char * const rt5645_dac1_src[] = {
930 "IF1 DAC", "IF2 DAC", "IF3 DAC"
931};
932
933static SOC_ENUM_SINGLE_DECL(
934 rt5645_dac1l_enum, RT5645_AD_DA_MIXER,
935 RT5645_DAC1_L_SEL_SFT, rt5645_dac1_src);
936
937static const struct snd_kcontrol_new rt5645_dac1l_mux =
938 SOC_DAPM_ENUM("DAC1 L source", rt5645_dac1l_enum);
939
940static SOC_ENUM_SINGLE_DECL(
941 rt5645_dac1r_enum, RT5645_AD_DA_MIXER,
942 RT5645_DAC1_R_SEL_SFT, rt5645_dac1_src);
943
944static const struct snd_kcontrol_new rt5645_dac1r_mux =
945 SOC_DAPM_ENUM("DAC1 R source", rt5645_dac1r_enum);
946
947/*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */
948static const char * const rt5645_dac12_src[] = {
949 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "VAD_ADC"
950};
951
952static SOC_ENUM_SINGLE_DECL(
953 rt5645_dac2l_enum, RT5645_DAC_CTRL,
954 RT5645_DAC2_L_SEL_SFT, rt5645_dac12_src);
955
956static const struct snd_kcontrol_new rt5645_dac_l2_mux =
957 SOC_DAPM_ENUM("DAC2 L source", rt5645_dac2l_enum);
958
959static const char * const rt5645_dacr2_src[] = {
960 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "Haptic"
961};
962
963static SOC_ENUM_SINGLE_DECL(
964 rt5645_dac2r_enum, RT5645_DAC_CTRL,
965 RT5645_DAC2_R_SEL_SFT, rt5645_dacr2_src);
966
967static const struct snd_kcontrol_new rt5645_dac_r2_mux =
968 SOC_DAPM_ENUM("DAC2 R source", rt5645_dac2r_enum);
969
970
971/* INL/R source */
972static const char * const rt5645_inl_src[] = {
973 "IN2P", "MonoP"
974};
975
976static SOC_ENUM_SINGLE_DECL(
977 rt5645_inl_enum, RT5645_INL1_INR1_VOL,
978 RT5645_INL_SEL_SFT, rt5645_inl_src);
979
980static const struct snd_kcontrol_new rt5645_inl_mux =
981 SOC_DAPM_ENUM("INL source", rt5645_inl_enum);
982
983static const char * const rt5645_inr_src[] = {
984 "IN2N", "MonoN"
985};
986
987static SOC_ENUM_SINGLE_DECL(
988 rt5645_inr_enum, RT5645_INL1_INR1_VOL,
989 RT5645_INR_SEL_SFT, rt5645_inr_src);
990
991static const struct snd_kcontrol_new rt5645_inr_mux =
992 SOC_DAPM_ENUM("INR source", rt5645_inr_enum);
993
994/* Stereo1 ADC source */
995/* MX-27 [12] */
996static const char * const rt5645_stereo_adc1_src[] = {
997 "DAC MIX", "ADC"
998};
999
1000static SOC_ENUM_SINGLE_DECL(
1001 rt5645_stereo1_adc1_enum, RT5645_STO1_ADC_MIXER,
1002 RT5645_ADC_1_SRC_SFT, rt5645_stereo_adc1_src);
1003
1004static const struct snd_kcontrol_new rt5645_sto_adc1_mux =
1005 SOC_DAPM_ENUM("Stereo1 ADC1 Mux", rt5645_stereo1_adc1_enum);
1006
1007/* MX-27 [11] */
1008static const char * const rt5645_stereo_adc2_src[] = {
1009 "DAC MIX", "DMIC"
1010};
1011
1012static SOC_ENUM_SINGLE_DECL(
1013 rt5645_stereo1_adc2_enum, RT5645_STO1_ADC_MIXER,
1014 RT5645_ADC_2_SRC_SFT, rt5645_stereo_adc2_src);
1015
1016static const struct snd_kcontrol_new rt5645_sto_adc2_mux =
1017 SOC_DAPM_ENUM("Stereo1 ADC2 Mux", rt5645_stereo1_adc2_enum);
1018
1019/* MX-27 [8] */
1020static const char * const rt5645_stereo_dmic_src[] = {
1021 "DMIC1", "DMIC2"
1022};
1023
1024static SOC_ENUM_SINGLE_DECL(
1025 rt5645_stereo1_dmic_enum, RT5645_STO1_ADC_MIXER,
1026 RT5645_DMIC_SRC_SFT, rt5645_stereo_dmic_src);
1027
1028static const struct snd_kcontrol_new rt5645_sto1_dmic_mux =
1029 SOC_DAPM_ENUM("Stereo1 DMIC source", rt5645_stereo1_dmic_enum);
1030
1031/* Mono ADC source */
1032/* MX-28 [12] */
1033static const char * const rt5645_mono_adc_l1_src[] = {
1034 "Mono DAC MIXL", "ADC"
1035};
1036
1037static SOC_ENUM_SINGLE_DECL(
1038 rt5645_mono_adc_l1_enum, RT5645_MONO_ADC_MIXER,
1039 RT5645_MONO_ADC_L1_SRC_SFT, rt5645_mono_adc_l1_src);
1040
1041static const struct snd_kcontrol_new rt5645_mono_adc_l1_mux =
1042 SOC_DAPM_ENUM("Mono ADC1 left source", rt5645_mono_adc_l1_enum);
1043/* MX-28 [11] */
1044static const char * const rt5645_mono_adc_l2_src[] = {
1045 "Mono DAC MIXL", "DMIC"
1046};
1047
1048static SOC_ENUM_SINGLE_DECL(
1049 rt5645_mono_adc_l2_enum, RT5645_MONO_ADC_MIXER,
1050 RT5645_MONO_ADC_L2_SRC_SFT, rt5645_mono_adc_l2_src);
1051
1052static const struct snd_kcontrol_new rt5645_mono_adc_l2_mux =
1053 SOC_DAPM_ENUM("Mono ADC2 left source", rt5645_mono_adc_l2_enum);
1054
1055/* MX-28 [8] */
1056static const char * const rt5645_mono_dmic_src[] = {
1057 "DMIC1", "DMIC2"
1058};
1059
1060static SOC_ENUM_SINGLE_DECL(
1061 rt5645_mono_dmic_l_enum, RT5645_MONO_ADC_MIXER,
1062 RT5645_MONO_DMIC_L_SRC_SFT, rt5645_mono_dmic_src);
1063
1064static const struct snd_kcontrol_new rt5645_mono_dmic_l_mux =
1065 SOC_DAPM_ENUM("Mono DMIC left source", rt5645_mono_dmic_l_enum);
1066/* MX-28 [1:0] */
1067static SOC_ENUM_SINGLE_DECL(
1068 rt5645_mono_dmic_r_enum, RT5645_MONO_ADC_MIXER,
1069 RT5645_MONO_DMIC_R_SRC_SFT, rt5645_mono_dmic_src);
1070
1071static const struct snd_kcontrol_new rt5645_mono_dmic_r_mux =
1072 SOC_DAPM_ENUM("Mono DMIC Right source", rt5645_mono_dmic_r_enum);
1073/* MX-28 [4] */
1074static const char * const rt5645_mono_adc_r1_src[] = {
1075 "Mono DAC MIXR", "ADC"
1076};
1077
1078static SOC_ENUM_SINGLE_DECL(
1079 rt5645_mono_adc_r1_enum, RT5645_MONO_ADC_MIXER,
1080 RT5645_MONO_ADC_R1_SRC_SFT, rt5645_mono_adc_r1_src);
1081
1082static const struct snd_kcontrol_new rt5645_mono_adc_r1_mux =
1083 SOC_DAPM_ENUM("Mono ADC1 right source", rt5645_mono_adc_r1_enum);
1084/* MX-28 [3] */
1085static const char * const rt5645_mono_adc_r2_src[] = {
1086 "Mono DAC MIXR", "DMIC"
1087};
1088
1089static SOC_ENUM_SINGLE_DECL(
1090 rt5645_mono_adc_r2_enum, RT5645_MONO_ADC_MIXER,
1091 RT5645_MONO_ADC_R2_SRC_SFT, rt5645_mono_adc_r2_src);
1092
1093static const struct snd_kcontrol_new rt5645_mono_adc_r2_mux =
1094 SOC_DAPM_ENUM("Mono ADC2 right source", rt5645_mono_adc_r2_enum);
1095
1096/* MX-77 [9:8] */
1097static const char * const rt5645_if1_adc_in_src[] = {
21ab3f2b
BL		 1098 "IF_ADC1/IF_ADC2/VAD_ADC", "IF_ADC2/IF_ADC1/VAD_ADC",
1099 "VAD_ADC/IF_ADC1/IF_ADC2", "VAD_ADC/IF_ADC2/IF_ADC1"
1319b2f6
OC		 1100};
1101
1102static SOC_ENUM_SINGLE_DECL(
1103 rt5645_if1_adc_in_enum, RT5645_TDM_CTRL_1,
1104 RT5645_IF1_ADC_IN_SFT, rt5645_if1_adc_in_src);
1105
1106static const struct snd_kcontrol_new rt5645_if1_adc_in_mux =
1107 SOC_DAPM_ENUM("IF1 ADC IN source", rt5645_if1_adc_in_enum);
1108
21ab3f2b
BL		 1109/* MX-78 [4:0] */
1110static const char * const rt5650_if1_adc_in_src[] = {
1111 "IF_ADC1/IF_ADC2/DAC_REF/Null",
1112 "IF_ADC1/IF_ADC2/Null/DAC_REF",
1113 "IF_ADC1/DAC_REF/IF_ADC2/Null",
1114 "IF_ADC1/DAC_REF/Null/IF_ADC2",
1115 "IF_ADC1/Null/DAC_REF/IF_ADC2",
1116 "IF_ADC1/Null/IF_ADC2/DAC_REF",
1117
1118 "IF_ADC2/IF_ADC1/DAC_REF/Null",
1119 "IF_ADC2/IF_ADC1/Null/DAC_REF",
1120 "IF_ADC2/DAC_REF/IF_ADC1/Null",
1121 "IF_ADC2/DAC_REF/Null/IF_ADC1",
1122 "IF_ADC2/Null/DAC_REF/IF_ADC1",
1123 "IF_ADC2/Null/IF_ADC1/DAC_REF",
1124
1125 "DAC_REF/IF_ADC1/IF_ADC2/Null",
1126 "DAC_REF/IF_ADC1/Null/IF_ADC2",
1127 "DAC_REF/IF_ADC2/IF_ADC1/Null",
1128 "DAC_REF/IF_ADC2/Null/IF_ADC1",
1129 "DAC_REF/Null/IF_ADC1/IF_ADC2",
1130 "DAC_REF/Null/IF_ADC2/IF_ADC1",
1131
1132 "Null/IF_ADC1/IF_ADC2/DAC_REF",
1133 "Null/IF_ADC1/DAC_REF/IF_ADC2",
1134 "Null/IF_ADC2/IF_ADC1/DAC_REF",
1135 "Null/IF_ADC2/DAC_REF/IF_ADC1",
1136 "Null/DAC_REF/IF_ADC1/IF_ADC2",
1137 "Null/DAC_REF/IF_ADC2/IF_ADC1",
1138};
1139
1140static SOC_ENUM_SINGLE_DECL(
1141 rt5650_if1_adc_in_enum, RT5645_TDM_CTRL_2,
1142 0, rt5650_if1_adc_in_src);
1143
1144static const struct snd_kcontrol_new rt5650_if1_adc_in_mux =
1145 SOC_DAPM_ENUM("IF1 ADC IN source", rt5650_if1_adc_in_enum);
1146
1147/* MX-78 [15:14][13:12][11:10] */
1148static const char * const rt5645_tdm_adc_swap_select[] = {
1149 "L/R", "R/L", "L/L", "R/R"
1150};
1151
1152static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot0_1_enum,
1153 RT5645_TDM_CTRL_2, 14, rt5645_tdm_adc_swap_select);
1154
1155static const struct snd_kcontrol_new rt5650_if1_adc1_in_mux =
1156 SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5650_tdm_adc_slot0_1_enum);
1157
1158static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot2_3_enum,
1159 RT5645_TDM_CTRL_2, 12, rt5645_tdm_adc_swap_select);
1160
1161static const struct snd_kcontrol_new rt5650_if1_adc2_in_mux =
1162 SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5650_tdm_adc_slot2_3_enum);
1163
1164static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot4_5_enum,
1165 RT5645_TDM_CTRL_2, 10, rt5645_tdm_adc_swap_select);
1166
1167static const struct snd_kcontrol_new rt5650_if1_adc3_in_mux =
1168 SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5650_tdm_adc_slot4_5_enum);
1169
1170/* MX-77 [7:6][5:4][3:2] */
1171static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot0_1_enum,
1172 RT5645_TDM_CTRL_1, 6, rt5645_tdm_adc_swap_select);
1173
1174static const struct snd_kcontrol_new rt5645_if1_adc1_in_mux =
1175 SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5645_tdm_adc_slot0_1_enum);
1176
1177static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot2_3_enum,
1178 RT5645_TDM_CTRL_1, 4, rt5645_tdm_adc_swap_select);
1179
1180static const struct snd_kcontrol_new rt5645_if1_adc2_in_mux =
1181 SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5645_tdm_adc_slot2_3_enum);
1182
1183static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot4_5_enum,
1184 RT5645_TDM_CTRL_1, 2, rt5645_tdm_adc_swap_select);
1185
1186static const struct snd_kcontrol_new rt5645_if1_adc3_in_mux =
1187 SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5645_tdm_adc_slot4_5_enum);
1188
1189/* MX-79 [14:12][10:8][6:4][2:0] */
1190static const char * const rt5645_tdm_dac_swap_select[] = {
1191 "Slot0", "Slot1", "Slot2", "Slot3"
1192};
1193
1194static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac0_enum,
1195 RT5645_TDM_CTRL_3, 12, rt5645_tdm_dac_swap_select);
1196
1197static const struct snd_kcontrol_new rt5645_if1_dac0_tdm_sel_mux =
1198 SOC_DAPM_ENUM("IF1 DAC0 source", rt5645_tdm_dac0_enum);
1199
1200static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac1_enum,
1201 RT5645_TDM_CTRL_3, 8, rt5645_tdm_dac_swap_select);
1202
1203static const struct snd_kcontrol_new rt5645_if1_dac1_tdm_sel_mux =
1204 SOC_DAPM_ENUM("IF1 DAC1 source", rt5645_tdm_dac1_enum);
1205
1206static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac2_enum,
1207 RT5645_TDM_CTRL_3, 4, rt5645_tdm_dac_swap_select);
1208
1209static const struct snd_kcontrol_new rt5645_if1_dac2_tdm_sel_mux =
1210 SOC_DAPM_ENUM("IF1 DAC2 source", rt5645_tdm_dac2_enum);
1211
1212static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac3_enum,
1213 RT5645_TDM_CTRL_3, 0, rt5645_tdm_dac_swap_select);
1214
1215static const struct snd_kcontrol_new rt5645_if1_dac3_tdm_sel_mux =
1216 SOC_DAPM_ENUM("IF1 DAC3 source", rt5645_tdm_dac3_enum);
1217
1218/* MX-7a [14:12][10:8][6:4][2:0] */
1219static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac0_enum,
1220 RT5650_TDM_CTRL_4, 12, rt5645_tdm_dac_swap_select);
1221
1222static const struct snd_kcontrol_new rt5650_if1_dac0_tdm_sel_mux =
1223 SOC_DAPM_ENUM("IF1 DAC0 source", rt5650_tdm_dac0_enum);
1224
1225static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac1_enum,
1226 RT5650_TDM_CTRL_4, 8, rt5645_tdm_dac_swap_select);
1227
1228static const struct snd_kcontrol_new rt5650_if1_dac1_tdm_sel_mux =
1229 SOC_DAPM_ENUM("IF1 DAC1 source", rt5650_tdm_dac1_enum);
1230
1231static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac2_enum,
1232 RT5650_TDM_CTRL_4, 4, rt5645_tdm_dac_swap_select);
1233
1234static const struct snd_kcontrol_new rt5650_if1_dac2_tdm_sel_mux =
1235 SOC_DAPM_ENUM("IF1 DAC2 source", rt5650_tdm_dac2_enum);
1236
1237static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac3_enum,
1238 RT5650_TDM_CTRL_4, 0, rt5645_tdm_dac_swap_select);
1239
1240static const struct snd_kcontrol_new rt5650_if1_dac3_tdm_sel_mux =
1241 SOC_DAPM_ENUM("IF1 DAC3 source", rt5650_tdm_dac3_enum);
1242
5c4ca99d
BL		 1243/* MX-2d [3] [2] */
1244static const char * const rt5650_a_dac1_src[] = {
1245 "DAC1", "Stereo DAC Mixer"
1246};
1247
1248static SOC_ENUM_SINGLE_DECL(
1249 rt5650_a_dac1_l_enum, RT5650_A_DAC_SOUR,
1250 RT5650_A_DAC1_L_IN_SFT, rt5650_a_dac1_src);
1251
1252static const struct snd_kcontrol_new rt5650_a_dac1_l_mux =
1253 SOC_DAPM_ENUM("A DAC1 L source", rt5650_a_dac1_l_enum);
1254
1255static SOC_ENUM_SINGLE_DECL(
1256 rt5650_a_dac1_r_enum, RT5650_A_DAC_SOUR,
1257 RT5650_A_DAC1_R_IN_SFT, rt5650_a_dac1_src);
1258
1259static const struct snd_kcontrol_new rt5650_a_dac1_r_mux =
1260 SOC_DAPM_ENUM("A DAC1 R source", rt5650_a_dac1_r_enum);
1261
1262/* MX-2d [1] [0] */
1263static const char * const rt5650_a_dac2_src[] = {
1264 "Stereo DAC Mixer", "Mono DAC Mixer"
1265};
1266
1267static SOC_ENUM_SINGLE_DECL(
1268 rt5650_a_dac2_l_enum, RT5650_A_DAC_SOUR,
1269 RT5650_A_DAC2_L_IN_SFT, rt5650_a_dac2_src);
1270
1271static const struct snd_kcontrol_new rt5650_a_dac2_l_mux =
1272 SOC_DAPM_ENUM("A DAC2 L source", rt5650_a_dac2_l_enum);
1273
1274static SOC_ENUM_SINGLE_DECL(
1275 rt5650_a_dac2_r_enum, RT5650_A_DAC_SOUR,
1276 RT5650_A_DAC2_R_IN_SFT, rt5650_a_dac2_src);
1277
1278static const struct snd_kcontrol_new rt5650_a_dac2_r_mux =
1279 SOC_DAPM_ENUM("A DAC2 R source", rt5650_a_dac2_r_enum);
1280
1319b2f6
OC		 1281/* MX-2F [13:12] */
1282static const char * const rt5645_if2_adc_in_src[] = {
1283 "IF_ADC1", "IF_ADC2", "VAD_ADC"
1284};
1285
1286static SOC_ENUM_SINGLE_DECL(
1287 rt5645_if2_adc_in_enum, RT5645_DIG_INF1_DATA,
1288 RT5645_IF2_ADC_IN_SFT, rt5645_if2_adc_in_src);
1289
1290static const struct snd_kcontrol_new rt5645_if2_adc_in_mux =
1291 SOC_DAPM_ENUM("IF2 ADC IN source", rt5645_if2_adc_in_enum);
1292
1293/* MX-2F [1:0] */
1294static const char * const rt5645_if3_adc_in_src[] = {
1295 "IF_ADC1", "IF_ADC2", "VAD_ADC"
1296};
1297
1298static SOC_ENUM_SINGLE_DECL(
1299 rt5645_if3_adc_in_enum, RT5645_DIG_INF1_DATA,
1300 RT5645_IF3_ADC_IN_SFT, rt5645_if3_adc_in_src);
1301
1302static const struct snd_kcontrol_new rt5645_if3_adc_in_mux =
1303 SOC_DAPM_ENUM("IF3 ADC IN source", rt5645_if3_adc_in_enum);
1304
1305/* MX-31 [15] [13] [11] [9] */
1306static const char * const rt5645_pdm_src[] = {
1307 "Mono DAC", "Stereo DAC"
1308};
1309
1310static SOC_ENUM_SINGLE_DECL(
1311 rt5645_pdm1_l_enum, RT5645_PDM_OUT_CTRL,
1312 RT5645_PDM1_L_SFT, rt5645_pdm_src);
1313
1314static const struct snd_kcontrol_new rt5645_pdm1_l_mux =
1315 SOC_DAPM_ENUM("PDM1 L source", rt5645_pdm1_l_enum);
1316
1317static SOC_ENUM_SINGLE_DECL(
1318 rt5645_pdm1_r_enum, RT5645_PDM_OUT_CTRL,
1319 RT5645_PDM1_R_SFT, rt5645_pdm_src);
1320
1321static const struct snd_kcontrol_new rt5645_pdm1_r_mux =
1322 SOC_DAPM_ENUM("PDM1 R source", rt5645_pdm1_r_enum);
1323
1324/* MX-9D [9:8] */
1325static const char * const rt5645_vad_adc_src[] = {
1326 "Sto1 ADC L", "Mono ADC L", "Mono ADC R"
1327};
1328
1329static SOC_ENUM_SINGLE_DECL(
1330 rt5645_vad_adc_enum, RT5645_VAD_CTRL4,
1331 RT5645_VAD_SEL_SFT, rt5645_vad_adc_src);
1332
1333static const struct snd_kcontrol_new rt5645_vad_adc_mux =
1334 SOC_DAPM_ENUM("VAD ADC source", rt5645_vad_adc_enum);
1335
1336static const struct snd_kcontrol_new spk_l_vol_control =
1337 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
1338 RT5645_L_MUTE_SFT, 1, 1);
1339
1340static const struct snd_kcontrol_new spk_r_vol_control =
1341 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
1342 RT5645_R_MUTE_SFT, 1, 1);
1343
1344static const struct snd_kcontrol_new hp_l_vol_control =
1345 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
1346 RT5645_L_MUTE_SFT, 1, 1);
1347
1348static const struct snd_kcontrol_new hp_r_vol_control =
1349 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
1350 RT5645_R_MUTE_SFT, 1, 1);
1351
1352static const struct snd_kcontrol_new pdm1_l_vol_control =
1353 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
1354 RT5645_M_PDM1_L, 1, 1);
1355
1356static const struct snd_kcontrol_new pdm1_r_vol_control =
1357 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
1358 RT5645_M_PDM1_R, 1, 1);
1359
1360static void hp_amp_power(struct snd_soc_codec *codec, int on)
1361{
1362 static int hp_amp_power_count;
1363 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1364
1365 if (on) {
1366 if (hp_amp_power_count <= 0) {
d12d6c4e 1367 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
588cd850 1368 snd_soc_write(codec, RT5645_DEPOP_M2, 0x3100);
d12d6c4e
JL		 1369 snd_soc_write(codec, RT5645_CHARGE_PUMP,
1370 0x0e06);
588cd850
OC		 1371 snd_soc_write(codec, RT5645_DEPOP_M1, 0x000d);
1372 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1373 RT5645_HP_DCC_INT1, 0x9f01);
1374 msleep(20);
1375 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1376 RT5645_HP_CO_MASK, RT5645_HP_CO_EN);
d12d6c4e
JL		 1377 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1378 0x3e, 0x7400);
1379 snd_soc_write(codec, RT5645_DEPOP_M3, 0x0737);
1380 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1381 RT5645_MAMP_INT_REG2, 0xfc00);
1382 snd_soc_write(codec, RT5645_DEPOP_M2, 0x1140);
588cd850
OC		 1383 mdelay(5);
1384 rt5645->hp_on = true;
d12d6c4e
JL		 1385 } else {
1386 /* depop parameters */
1387 snd_soc_update_bits(codec, RT5645_DEPOP_M2,
1388 RT5645_DEPOP_MASK, RT5645_DEPOP_MAN);
1389 snd_soc_write(codec, RT5645_DEPOP_M1, 0x000d);
1390 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1391 RT5645_HP_DCC_INT1, 0x9f01);
1392 mdelay(150);
1393 /* headphone amp power on */
1394 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1395 RT5645_PWR_FV1 | RT5645_PWR_FV2, 0);
1396 snd_soc_update_bits(codec, RT5645_PWR_VOL,
1397 RT5645_PWR_HV_L | RT5645_PWR_HV_R,
1398 RT5645_PWR_HV_L | RT5645_PWR_HV_R);
1399 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1400 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1401 RT5645_PWR_HA,
1402 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1403 RT5645_PWR_HA);
1404 mdelay(5);
1405 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1406 RT5645_PWR_FV1 | RT5645_PWR_FV2,
1407 RT5645_PWR_FV1 | RT5645_PWR_FV2);
1408
1409 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1410 RT5645_HP_CO_MASK | RT5645_HP_SG_MASK,
1411 RT5645_HP_CO_EN | RT5645_HP_SG_EN);
1412 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1413 0x14, 0x1aaa);
1414 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1415 0x24, 0x0430);
1416 }
1319b2f6
OC		 1417 }
1418 hp_amp_power_count++;
1419 } else {
1420 hp_amp_power_count--;
1421 if (hp_amp_power_count <= 0) {
d12d6c4e
JL		 1422 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
1423 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1424 0x3e, 0x7400);
1425 snd_soc_write(codec, RT5645_DEPOP_M3, 0x0737);
1426 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1427 RT5645_MAMP_INT_REG2, 0xfc00);
1428 snd_soc_write(codec, RT5645_DEPOP_M2, 0x1140);
1429 msleep(100);
1430 snd_soc_write(codec, RT5645_DEPOP_M1, 0x0001);
1431
1432 } else {
1433 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1434 RT5645_HP_SG_MASK |
1435 RT5645_HP_L_SMT_MASK |
1436 RT5645_HP_R_SMT_MASK,
1437 RT5645_HP_SG_DIS |
1438 RT5645_HP_L_SMT_DIS |
1439 RT5645_HP_R_SMT_DIS);
1440 /* headphone amp power down */
1441 snd_soc_write(codec, RT5645_DEPOP_M1, 0x0000);
1442 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1443 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1444 RT5645_PWR_HA, 0);
1445 snd_soc_update_bits(codec, RT5645_DEPOP_M2,
1446 RT5645_DEPOP_MASK, 0);
1447 }
1319b2f6
OC		 1448 }
1449 }
1450}
1451
1452static int rt5645_hp_event(struct snd_soc_dapm_widget *w,
1453 struct snd_kcontrol *kcontrol, int event)
1454{
c5f596cb 1455 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1319b2f6
OC		 1456 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1457
1458 switch (event) {
1459 case SND_SOC_DAPM_POST_PMU:
1460 hp_amp_power(codec, 1);
1461 /* headphone unmute sequence */
d12d6c4e 1462 if (rt5645->codec_type == CODEC_TYPE_RT5645) {
5c4ca99d
BL		 1463 snd_soc_update_bits(codec, RT5645_DEPOP_M3,
1464 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
1465 RT5645_CP_FQ3_MASK,
1466 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ1_SFT) |
1467 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1468 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ3_SFT));
d12d6c4e
JL		 1469 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1470 RT5645_MAMP_INT_REG2, 0xfc00);
1471 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1472 RT5645_SMT_TRIG_MASK, RT5645_SMT_TRIG_EN);
1473 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1474 RT5645_RSTN_MASK, RT5645_RSTN_EN);
1475 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1476 RT5645_RSTN_MASK | RT5645_HP_L_SMT_MASK |
1477 RT5645_HP_R_SMT_MASK, RT5645_RSTN_DIS |
1478 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1479 msleep(40);
1480 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1481 RT5645_HP_SG_MASK | RT5645_HP_L_SMT_MASK |
1482 RT5645_HP_R_SMT_MASK, RT5645_HP_SG_DIS |
1483 RT5645_HP_L_SMT_DIS | RT5645_HP_R_SMT_DIS);
5c4ca99d 1484 }
1319b2f6
OC		 1485 break;
1486
1487 case SND_SOC_DAPM_PRE_PMD:
1488 /* headphone mute sequence */
d12d6c4e 1489 if (rt5645->codec_type == CODEC_TYPE_RT5645) {
5c4ca99d
BL		 1490 snd_soc_update_bits(codec, RT5645_DEPOP_M3,
1491 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
1492 RT5645_CP_FQ3_MASK,
1493 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ1_SFT) |
1494 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1495 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ3_SFT));
d12d6c4e
JL		 1496 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1497 RT5645_MAMP_INT_REG2, 0xfc00);
1498 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1499 RT5645_HP_SG_MASK, RT5645_HP_SG_EN);
1500 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1501 RT5645_RSTP_MASK, RT5645_RSTP_EN);
1502 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1503 RT5645_RSTP_MASK | RT5645_HP_L_SMT_MASK |
1504 RT5645_HP_R_SMT_MASK, RT5645_RSTP_DIS |
1505 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1506 msleep(30);
5c4ca99d 1507 }
1319b2f6
OC		 1508 hp_amp_power(codec, 0);
1509 break;
1510
1511 default:
1512 return 0;
1513 }
1514
1515 return 0;
1516}
1517
1518static int rt5645_spk_event(struct snd_soc_dapm_widget *w,
1519 struct snd_kcontrol *kcontrol, int event)
1520{
c5f596cb 1521 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1319b2f6
OC		 1522
1523 switch (event) {
1524 case SND_SOC_DAPM_POST_PMU:
1525 snd_soc_update_bits(codec, RT5645_PWR_DIG1,
1526 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1527 RT5645_PWR_CLS_D_L,
1528 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1529 RT5645_PWR_CLS_D_L);
1530 break;
1531
1532 case SND_SOC_DAPM_PRE_PMD:
1533 snd_soc_update_bits(codec, RT5645_PWR_DIG1,
1534 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1535 RT5645_PWR_CLS_D_L, 0);
1536 break;
1537
1538 default:
1539 return 0;
1540 }
1541
1542 return 0;
1543}
1544
1545static int rt5645_lout_event(struct snd_soc_dapm_widget *w,
1546 struct snd_kcontrol *kcontrol, int event)
1547{
c5f596cb 1548 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1319b2f6
OC		 1549
1550 switch (event) {
1551 case SND_SOC_DAPM_POST_PMU:
1552 hp_amp_power(codec, 1);
1553 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1554 RT5645_PWR_LM, RT5645_PWR_LM);
1555 snd_soc_update_bits(codec, RT5645_LOUT1,
1556 RT5645_L_MUTE | RT5645_R_MUTE, 0);
1557 break;
1558
1559 case SND_SOC_DAPM_PRE_PMD:
1560 snd_soc_update_bits(codec, RT5645_LOUT1,
1561 RT5645_L_MUTE | RT5645_R_MUTE,
1562 RT5645_L_MUTE | RT5645_R_MUTE);
1563 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1564 RT5645_PWR_LM, 0);
1565 hp_amp_power(codec, 0);
1566 break;
1567
1568 default:
1569 return 0;
1570 }
1571
1572 return 0;
1573}
1574
1575static int rt5645_bst2_event(struct snd_soc_dapm_widget *w,
1576 struct snd_kcontrol *kcontrol, int event)
1577{
c5f596cb 1578 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1319b2f6
OC		 1579
1580 switch (event) {
1581 case SND_SOC_DAPM_POST_PMU:
1582 snd_soc_update_bits(codec, RT5645_PWR_ANLG2,
1583 RT5645_PWR_BST2_P, RT5645_PWR_BST2_P);
1584 break;
1585
1586 case SND_SOC_DAPM_PRE_PMD:
1587 snd_soc_update_bits(codec, RT5645_PWR_ANLG2,
1588 RT5645_PWR_BST2_P, 0);
1589 break;
1590
1591 default:
1592 return 0;
1593 }
1594
1595 return 0;
1596}
1597
588cd850
OC		 1598static int rt5650_hp_event(struct snd_soc_dapm_widget *w,
1599 struct snd_kcontrol *k, int event)
1600{
1601 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1602 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1603
1604 switch (event) {
1605 case SND_SOC_DAPM_POST_PMU:
1606 if (rt5645->hp_on) {
1607 msleep(100);
1608 rt5645->hp_on = false;
1609 }
1610 break;
1611
1612 default:
1613 return 0;
1614 }
1615
1616 return 0;
1617}
1618
1319b2f6
OC		 1619static const struct snd_soc_dapm_widget rt5645_dapm_widgets[] = {
1620 SND_SOC_DAPM_SUPPLY("LDO2", RT5645_PWR_MIXER,
1621 RT5645_PWR_LDO2_BIT, 0, NULL, 0),
1622 SND_SOC_DAPM_SUPPLY("PLL1", RT5645_PWR_ANLG2,
1623 RT5645_PWR_PLL_BIT, 0, NULL, 0),
1624
1625 SND_SOC_DAPM_SUPPLY("JD Power", RT5645_PWR_ANLG2,
1626 RT5645_PWR_JD1_BIT, 0, NULL, 0),
1627 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5645_PWR_VOL,
1628 RT5645_PWR_MIC_DET_BIT, 0, NULL, 0),
1629
9e268353
BL		 1630 /* ASRC */
1631 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5645_ASRC_1,
1632 11, 0, NULL, 0),
1633 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5645_ASRC_1,
1634 12, 0, NULL, 0),
1635 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5645_ASRC_1,
1636 10, 0, NULL, 0),
1637 SND_SOC_DAPM_SUPPLY_S("DAC MONO L ASRC", 1, RT5645_ASRC_1,
1638 9, 0, NULL, 0),
1639 SND_SOC_DAPM_SUPPLY_S("DAC MONO R ASRC", 1, RT5645_ASRC_1,
1640 8, 0, NULL, 0),
1641 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5645_ASRC_1,
1642 7, 0, NULL, 0),
1643 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5645_ASRC_1,
1644 5, 0, NULL, 0),
1645 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5645_ASRC_1,
1646 4, 0, NULL, 0),
1647 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5645_ASRC_1,
1648 3, 0, NULL, 0),
1649 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5645_ASRC_1,
1650 1, 0, NULL, 0),
1651 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5645_ASRC_1,
1652 0, 0, NULL, 0),
1653
1319b2f6
OC		 1654 /* Input Side */
1655 /* micbias */
1656 SND_SOC_DAPM_MICBIAS("micbias1", RT5645_PWR_ANLG2,
1657 RT5645_PWR_MB1_BIT, 0),
1658 SND_SOC_DAPM_MICBIAS("micbias2", RT5645_PWR_ANLG2,
1659 RT5645_PWR_MB2_BIT, 0),
1660 /* Input Lines */
1661 SND_SOC_DAPM_INPUT("DMIC L1"),
1662 SND_SOC_DAPM_INPUT("DMIC R1"),
1663 SND_SOC_DAPM_INPUT("DMIC L2"),
1664 SND_SOC_DAPM_INPUT("DMIC R2"),
1665
1666 SND_SOC_DAPM_INPUT("IN1P"),
1667 SND_SOC_DAPM_INPUT("IN1N"),
1668 SND_SOC_DAPM_INPUT("IN2P"),
1669 SND_SOC_DAPM_INPUT("IN2N"),
1670
1671 SND_SOC_DAPM_INPUT("Haptic Generator"),
1672
1673 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1674 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1675 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1676 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1677 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5645_DMIC_CTRL1,
1678 RT5645_DMIC_1_EN_SFT, 0, NULL, 0),
1679 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5645_DMIC_CTRL1,
1680 RT5645_DMIC_2_EN_SFT, 0, NULL, 0),
1681 /* Boost */
1682 SND_SOC_DAPM_PGA("BST1", RT5645_PWR_ANLG2,
1683 RT5645_PWR_BST1_BIT, 0, NULL, 0),
1684 SND_SOC_DAPM_PGA_E("BST2", RT5645_PWR_ANLG2,
1685 RT5645_PWR_BST2_BIT, 0, NULL, 0, rt5645_bst2_event,
1686 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1687 /* Input Volume */
1688 SND_SOC_DAPM_PGA("INL VOL", RT5645_PWR_VOL,
1689 RT5645_PWR_IN_L_BIT, 0, NULL, 0),
1690 SND_SOC_DAPM_PGA("INR VOL", RT5645_PWR_VOL,
1691 RT5645_PWR_IN_R_BIT, 0, NULL, 0),
1692 /* REC Mixer */
1693 SND_SOC_DAPM_MIXER("RECMIXL", RT5645_PWR_MIXER, RT5645_PWR_RM_L_BIT,
1694 0, rt5645_rec_l_mix, ARRAY_SIZE(rt5645_rec_l_mix)),
1695 SND_SOC_DAPM_MIXER("RECMIXR", RT5645_PWR_MIXER, RT5645_PWR_RM_R_BIT,
1696 0, rt5645_rec_r_mix, ARRAY_SIZE(rt5645_rec_r_mix)),
1697 /* ADCs */
1698 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
1699 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
1700
1701 SND_SOC_DAPM_SUPPLY("ADC L power", RT5645_PWR_DIG1,
1702 RT5645_PWR_ADC_L_BIT, 0, NULL, 0),
1703 SND_SOC_DAPM_SUPPLY("ADC R power", RT5645_PWR_DIG1,
1704 RT5645_PWR_ADC_R_BIT, 0, NULL, 0),
1705
1706 /* ADC Mux */
1707 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
1708 &rt5645_sto1_dmic_mux),
1709 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1710 &rt5645_sto_adc2_mux),
1711 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1712 &rt5645_sto_adc2_mux),
1713 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1714 &rt5645_sto_adc1_mux),
1715 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1716 &rt5645_sto_adc1_mux),
1717 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
1718 &rt5645_mono_dmic_l_mux),
1719 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
1720 &rt5645_mono_dmic_r_mux),
1721 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1722 &rt5645_mono_adc_l2_mux),
1723 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1724 &rt5645_mono_adc_l1_mux),
1725 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1726 &rt5645_mono_adc_r1_mux),
1727 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1728 &rt5645_mono_adc_r2_mux),
1729 /* ADC Mixer */
1730
1731 SND_SOC_DAPM_SUPPLY_S("adc stereo1 filter", 1, RT5645_PWR_DIG2,
1732 RT5645_PWR_ADC_S1F_BIT, 0, NULL, 0),
1319b2f6
OC		 1733 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
1734 rt5645_sto1_adc_l_mix, ARRAY_SIZE(rt5645_sto1_adc_l_mix),
1735 NULL, 0),
1736 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
1737 rt5645_sto1_adc_r_mix, ARRAY_SIZE(rt5645_sto1_adc_r_mix),
1738 NULL, 0),
1739 SND_SOC_DAPM_SUPPLY_S("adc mono left filter", 1, RT5645_PWR_DIG2,
1740 RT5645_PWR_ADC_MF_L_BIT, 0, NULL, 0),
1741 SND_SOC_DAPM_MIXER_E("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
1742 rt5645_mono_adc_l_mix, ARRAY_SIZE(rt5645_mono_adc_l_mix),
1743 NULL, 0),
1744 SND_SOC_DAPM_SUPPLY_S("adc mono right filter", 1, RT5645_PWR_DIG2,
1745 RT5645_PWR_ADC_MF_R_BIT, 0, NULL, 0),
1746 SND_SOC_DAPM_MIXER_E("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
1747 rt5645_mono_adc_r_mix, ARRAY_SIZE(rt5645_mono_adc_r_mix),
1748 NULL, 0),
1749
1750 /* ADC PGA */
1751 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1752 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1753 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1754 SND_SOC_DAPM_PGA("VAD_ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1755 SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1756 SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1757 SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1758 SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1759 SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1760 SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1761
1762 /* IF1 2 Mux */
1319b2f6
OC		 1763 SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM,
1764 0, 0, &rt5645_if2_adc_in_mux),
1765
1766 /* Digital Interface */
1767 SND_SOC_DAPM_SUPPLY("I2S1", RT5645_PWR_DIG1,
1768 RT5645_PWR_I2S1_BIT, 0, NULL, 0),
786aa09b 1769 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
1319b2f6
OC		 1770 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1771 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
786aa09b 1772 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1319b2f6
OC		 1773 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1774 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1775 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1776 SND_SOC_DAPM_SUPPLY("I2S2", RT5645_PWR_DIG1,
1777 RT5645_PWR_I2S2_BIT, 0, NULL, 0),
1778 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1779 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1780 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1781 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1782
1783 /* Digital Interface Select */
1784 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM,
1785 0, 0, &rt5645_vad_adc_mux),
1786
1787 /* Audio Interface */
1788 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1789 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1790 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1791 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1792
1793 /* Output Side */
1794 /* DAC mixer before sound effect */
1795 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1796 rt5645_dac_l_mix, ARRAY_SIZE(rt5645_dac_l_mix)),
1797 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1798 rt5645_dac_r_mix, ARRAY_SIZE(rt5645_dac_r_mix)),
1799
1800 /* DAC2 channel Mux */
1801 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_l2_mux),
1802 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_r2_mux),
1803 SND_SOC_DAPM_PGA("DAC L2 Volume", RT5645_PWR_DIG1,
1804 RT5645_PWR_DAC_L2_BIT, 0, NULL, 0),
1805 SND_SOC_DAPM_PGA("DAC R2 Volume", RT5645_PWR_DIG1,
1806 RT5645_PWR_DAC_R2_BIT, 0, NULL, 0),
1807
1808 SND_SOC_DAPM_MUX("DAC1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1l_mux),
1809 SND_SOC_DAPM_MUX("DAC1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1r_mux),
1810
1811 /* DAC Mixer */
1812 SND_SOC_DAPM_SUPPLY_S("dac stereo1 filter", 1, RT5645_PWR_DIG2,
1813 RT5645_PWR_DAC_S1F_BIT, 0, NULL, 0),
1814 SND_SOC_DAPM_SUPPLY_S("dac mono left filter", 1, RT5645_PWR_DIG2,
1815 RT5645_PWR_DAC_MF_L_BIT, 0, NULL, 0),
1816 SND_SOC_DAPM_SUPPLY_S("dac mono right filter", 1, RT5645_PWR_DIG2,
1817 RT5645_PWR_DAC_MF_R_BIT, 0, NULL, 0),
1818 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
1819 rt5645_sto_dac_l_mix, ARRAY_SIZE(rt5645_sto_dac_l_mix)),
1820 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
1821 rt5645_sto_dac_r_mix, ARRAY_SIZE(rt5645_sto_dac_r_mix)),
1822 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
1823 rt5645_mono_dac_l_mix, ARRAY_SIZE(rt5645_mono_dac_l_mix)),
1824 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
1825 rt5645_mono_dac_r_mix, ARRAY_SIZE(rt5645_mono_dac_r_mix)),
1826 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
1827 rt5645_dig_l_mix, ARRAY_SIZE(rt5645_dig_l_mix)),
1828 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
1829 rt5645_dig_r_mix, ARRAY_SIZE(rt5645_dig_r_mix)),
1830
1831 /* DACs */
1832 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L1_BIT,
1833 0),
1834 SND_SOC_DAPM_DAC("DAC L2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L2_BIT,
1835 0),
1836 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R1_BIT,
1837 0),
1838 SND_SOC_DAPM_DAC("DAC R2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R2_BIT,
1839 0),
1840 /* OUT Mixer */
1841 SND_SOC_DAPM_MIXER("SPK MIXL", RT5645_PWR_MIXER, RT5645_PWR_SM_L_BIT,
1842 0, rt5645_spk_l_mix, ARRAY_SIZE(rt5645_spk_l_mix)),
1843 SND_SOC_DAPM_MIXER("SPK MIXR", RT5645_PWR_MIXER, RT5645_PWR_SM_R_BIT,
1844 0, rt5645_spk_r_mix, ARRAY_SIZE(rt5645_spk_r_mix)),
1845 SND_SOC_DAPM_MIXER("OUT MIXL", RT5645_PWR_MIXER, RT5645_PWR_OM_L_BIT,
1846 0, rt5645_out_l_mix, ARRAY_SIZE(rt5645_out_l_mix)),
1847 SND_SOC_DAPM_MIXER("OUT MIXR", RT5645_PWR_MIXER, RT5645_PWR_OM_R_BIT,
1848 0, rt5645_out_r_mix, ARRAY_SIZE(rt5645_out_r_mix)),
1849 /* Ouput Volume */
1850 SND_SOC_DAPM_SWITCH("SPKVOL L", RT5645_PWR_VOL, RT5645_PWR_SV_L_BIT, 0,
1851 &spk_l_vol_control),
1852 SND_SOC_DAPM_SWITCH("SPKVOL R", RT5645_PWR_VOL, RT5645_PWR_SV_R_BIT, 0,
1853 &spk_r_vol_control),
1854 SND_SOC_DAPM_MIXER("HPOVOL MIXL", RT5645_PWR_VOL, RT5645_PWR_HV_L_BIT,
1855 0, rt5645_hpvoll_mix, ARRAY_SIZE(rt5645_hpvoll_mix)),
1856 SND_SOC_DAPM_MIXER("HPOVOL MIXR", RT5645_PWR_VOL, RT5645_PWR_HV_R_BIT,
1857 0, rt5645_hpvolr_mix, ARRAY_SIZE(rt5645_hpvolr_mix)),
1858 SND_SOC_DAPM_SUPPLY("HPOVOL MIXL Power", RT5645_PWR_MIXER,
1859 RT5645_PWR_HM_L_BIT, 0, NULL, 0),
1860 SND_SOC_DAPM_SUPPLY("HPOVOL MIXR Power", RT5645_PWR_MIXER,
1861 RT5645_PWR_HM_R_BIT, 0, NULL, 0),
1862 SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM, 0, 0, NULL, 0),
1863 SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM, 0, 0, NULL, 0),
1864 SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM, 0, 0, NULL, 0),
1865 SND_SOC_DAPM_SWITCH("HPOVOL L", SND_SOC_NOPM, 0, 0, &hp_l_vol_control),
1866 SND_SOC_DAPM_SWITCH("HPOVOL R", SND_SOC_NOPM, 0, 0, &hp_r_vol_control),
1867
1868 /* HPO/LOUT/Mono Mixer */
1869 SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_l_mix,
1870 ARRAY_SIZE(rt5645_spo_l_mix)),
1871 SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_r_mix,
1872 ARRAY_SIZE(rt5645_spo_r_mix)),
1873 SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0, rt5645_hpo_mix,
1874 ARRAY_SIZE(rt5645_hpo_mix)),
1875 SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0, rt5645_lout_mix,
1876 ARRAY_SIZE(rt5645_lout_mix)),
1877
1878 SND_SOC_DAPM_PGA_S("HP amp", 1, SND_SOC_NOPM, 0, 0, rt5645_hp_event,
1879 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1880 SND_SOC_DAPM_PGA_S("LOUT amp", 1, SND_SOC_NOPM, 0, 0, rt5645_lout_event,
1881 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1882 SND_SOC_DAPM_PGA_S("SPK amp", 2, SND_SOC_NOPM, 0, 0, rt5645_spk_event,
1883 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1884
1885 /* PDM */
1886 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5645_PWR_DIG2, RT5645_PWR_PDM1_BIT,
1887 0, NULL, 0),
1888 SND_SOC_DAPM_MUX("PDM1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_l_mux),
1889 SND_SOC_DAPM_MUX("PDM1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_r_mux),
1890
1891 SND_SOC_DAPM_SWITCH("PDM1 L", SND_SOC_NOPM, 0, 0, &pdm1_l_vol_control),
1892 SND_SOC_DAPM_SWITCH("PDM1 R", SND_SOC_NOPM, 0, 0, &pdm1_r_vol_control),
1893
1894 /* Output Lines */
1895 SND_SOC_DAPM_OUTPUT("HPOL"),
1896 SND_SOC_DAPM_OUTPUT("HPOR"),
1897 SND_SOC_DAPM_OUTPUT("LOUTL"),
1898 SND_SOC_DAPM_OUTPUT("LOUTR"),
1899 SND_SOC_DAPM_OUTPUT("PDM1L"),
1900 SND_SOC_DAPM_OUTPUT("PDM1R"),
1901 SND_SOC_DAPM_OUTPUT("SPOL"),
1902 SND_SOC_DAPM_OUTPUT("SPOR"),
588cd850 1903 SND_SOC_DAPM_POST("DAPM_POST", rt5650_hp_event),
1319b2f6
OC		 1904};
1905
83c09290
BL		 1906static const struct snd_soc_dapm_widget rt5645_specific_dapm_widgets[] = {
1907 SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0,
1908 &rt5645_if1_dac0_tdm_sel_mux),
1909 SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0,
1910 &rt5645_if1_dac1_tdm_sel_mux),
1911 SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0,
1912 &rt5645_if1_dac2_tdm_sel_mux),
1913 SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0,
1914 &rt5645_if1_dac3_tdm_sel_mux),
1915 SND_SOC_DAPM_MUX("RT5645 IF1 ADC Mux", SND_SOC_NOPM,
1916 0, 0, &rt5645_if1_adc_in_mux),
1917 SND_SOC_DAPM_MUX("RT5645 IF1 ADC1 Swap Mux", SND_SOC_NOPM,
1918 0, 0, &rt5645_if1_adc1_in_mux),
1919 SND_SOC_DAPM_MUX("RT5645 IF1 ADC2 Swap Mux", SND_SOC_NOPM,
1920 0, 0, &rt5645_if1_adc2_in_mux),
1921 SND_SOC_DAPM_MUX("RT5645 IF1 ADC3 Swap Mux", SND_SOC_NOPM,
1922 0, 0, &rt5645_if1_adc3_in_mux),
1923};
1924
5c4ca99d
BL		 1925static const struct snd_soc_dapm_widget rt5650_specific_dapm_widgets[] = {
1926 SND_SOC_DAPM_MUX("A DAC1 L Mux", SND_SOC_NOPM,
1927 0, 0, &rt5650_a_dac1_l_mux),
1928 SND_SOC_DAPM_MUX("A DAC1 R Mux", SND_SOC_NOPM,
1929 0, 0, &rt5650_a_dac1_r_mux),
1930 SND_SOC_DAPM_MUX("A DAC2 L Mux", SND_SOC_NOPM,
1931 0, 0, &rt5650_a_dac2_l_mux),
1932 SND_SOC_DAPM_MUX("A DAC2 R Mux", SND_SOC_NOPM,
1933 0, 0, &rt5650_a_dac2_r_mux),
851b81e8
MC		 1934
1935 SND_SOC_DAPM_MUX("RT5650 IF1 ADC1 Swap Mux", SND_SOC_NOPM,
1936 0, 0, &rt5650_if1_adc1_in_mux),
1937 SND_SOC_DAPM_MUX("RT5650 IF1 ADC2 Swap Mux", SND_SOC_NOPM,
1938 0, 0, &rt5650_if1_adc2_in_mux),
1939 SND_SOC_DAPM_MUX("RT5650 IF1 ADC3 Swap Mux", SND_SOC_NOPM,
1940 0, 0, &rt5650_if1_adc3_in_mux),
1941 SND_SOC_DAPM_MUX("RT5650 IF1 ADC Mux", SND_SOC_NOPM,
1942 0, 0, &rt5650_if1_adc_in_mux),
1943
1944 SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0,
1945 &rt5650_if1_dac0_tdm_sel_mux),
1946 SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0,
1947 &rt5650_if1_dac1_tdm_sel_mux),
1948 SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0,
1949 &rt5650_if1_dac2_tdm_sel_mux),
1950 SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0,
1951 &rt5650_if1_dac3_tdm_sel_mux),
5c4ca99d
BL		 1952};
1953
1319b2f6 1954static const struct snd_soc_dapm_route rt5645_dapm_routes[] = {
9e268353 1955 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc },
9e268353
BL		 1956 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc },
1957 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc },
1958 { "dac mono left filter", NULL, "DAC MONO L ASRC", is_using_asrc },
1959 { "dac mono right filter", NULL, "DAC MONO R ASRC", is_using_asrc },
1960 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc },
1961
1962 { "I2S1", NULL, "I2S1 ASRC" },
1963 { "I2S2", NULL, "I2S2 ASRC" },
1964
1319b2f6
OC		 1965 { "IN1P", NULL, "LDO2" },
1966 { "IN2P", NULL, "LDO2" },
1967
1968 { "DMIC1", NULL, "DMIC L1" },
1969 { "DMIC1", NULL, "DMIC R1" },
1970 { "DMIC2", NULL, "DMIC L2" },
1971 { "DMIC2", NULL, "DMIC R2" },
1972
1973 { "BST1", NULL, "IN1P" },
1974 { "BST1", NULL, "IN1N" },
1975 { "BST1", NULL, "JD Power" },
1976 { "BST1", NULL, "Mic Det Power" },
1977 { "BST2", NULL, "IN2P" },
1978 { "BST2", NULL, "IN2N" },
1979
1980 { "INL VOL", NULL, "IN2P" },
1981 { "INR VOL", NULL, "IN2N" },
1982
1983 { "RECMIXL", "HPOL Switch", "HPOL" },
1984 { "RECMIXL", "INL Switch", "INL VOL" },
1985 { "RECMIXL", "BST2 Switch", "BST2" },
1986 { "RECMIXL", "BST1 Switch", "BST1" },
1987 { "RECMIXL", "OUT MIXL Switch", "OUT MIXL" },
1988
1989 { "RECMIXR", "HPOR Switch", "HPOR" },
1990 { "RECMIXR", "INR Switch", "INR VOL" },
1991 { "RECMIXR", "BST2 Switch", "BST2" },
1992 { "RECMIXR", "BST1 Switch", "BST1" },
1993 { "RECMIXR", "OUT MIXR Switch", "OUT MIXR" },
1994
1995 { "ADC L", NULL, "RECMIXL" },
1996 { "ADC L", NULL, "ADC L power" },
1997 { "ADC R", NULL, "RECMIXR" },
1998 { "ADC R", NULL, "ADC R power" },
1999
2000 {"DMIC L1", NULL, "DMIC CLK"},
2001 {"DMIC L1", NULL, "DMIC1 Power"},
2002 {"DMIC R1", NULL, "DMIC CLK"},
2003 {"DMIC R1", NULL, "DMIC1 Power"},
2004 {"DMIC L2", NULL, "DMIC CLK"},
2005 {"DMIC L2", NULL, "DMIC2 Power"},
2006 {"DMIC R2", NULL, "DMIC CLK"},
2007 {"DMIC R2", NULL, "DMIC2 Power"},
2008
2009 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
2010 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
9e268353 2011 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC" },
1319b2f6
OC		 2012
2013 { "Mono DMIC L Mux", "DMIC1", "DMIC L1" },
2014 { "Mono DMIC L Mux", "DMIC2", "DMIC L2" },
9e268353 2015 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC" },
1319b2f6
OC		 2016
2017 { "Mono DMIC R Mux", "DMIC1", "DMIC R1" },
2018 { "Mono DMIC R Mux", "DMIC2", "DMIC R2" },
9e268353 2019 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC" },
1319b2f6
OC		 2020
2021 { "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC Mux" },
2022 { "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" },
2023 { "Stereo1 ADC L1 Mux", "ADC", "ADC L" },
2024 { "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" },
2025
2026 { "Stereo1 ADC R1 Mux", "ADC", "ADC R" },
2027 { "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" },
2028 { "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC Mux" },
2029 { "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" },
2030
2031 { "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" },
2032 { "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
2033 { "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
2034 { "Mono ADC L1 Mux", "ADC", "ADC L" },
2035
2036 { "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
2037 { "Mono ADC R1 Mux", "ADC", "ADC R" },
2038 { "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" },
2039 { "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
2040
2041 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" },
2042 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" },
2043 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" },
2044 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" },
2045
2046 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
2047 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
2048 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
2049
2050 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
2051 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
2052 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
2053
2054 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" },
2055 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" },
2056 { "Mono ADC MIXL", NULL, "adc mono left filter" },
2057 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
2058
2059 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" },
2060 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" },
2061 { "Mono ADC MIXR", NULL, "adc mono right filter" },
2062 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
2063
2064 { "VAD ADC Mux", "Sto1 ADC L", "Stereo1 ADC MIXL" },
2065 { "VAD ADC Mux", "Mono ADC L", "Mono ADC MIXL" },
2066 { "VAD ADC Mux", "Mono ADC R", "Mono ADC MIXR" },
2067
2068 { "IF_ADC1", NULL, "Stereo1 ADC MIXL" },
2069 { "IF_ADC1", NULL, "Stereo1 ADC MIXR" },
2070 { "IF_ADC2", NULL, "Mono ADC MIXL" },
2071 { "IF_ADC2", NULL, "Mono ADC MIXR" },
2072 { "VAD_ADC", NULL, "VAD ADC Mux" },
2073
1319b2f6
OC		 2074 { "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" },
2075 { "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" },
2076 { "IF2 ADC Mux", "VAD_ADC", "VAD_ADC" },
2077
2078 { "IF1 ADC", NULL, "I2S1" },
1319b2f6
OC		 2079 { "IF2 ADC", NULL, "I2S2" },
2080 { "IF2 ADC", NULL, "IF2 ADC Mux" },
2081
1319b2f6
OC		 2082 { "AIF2TX", NULL, "IF2 ADC" },
2083
21ab3f2b 2084 { "IF1 DAC0", NULL, "AIF1RX" },
1319b2f6
OC		 2085 { "IF1 DAC1", NULL, "AIF1RX" },
2086 { "IF1 DAC2", NULL, "AIF1RX" },
21ab3f2b 2087 { "IF1 DAC3", NULL, "AIF1RX" },
1319b2f6
OC		 2088 { "IF2 DAC", NULL, "AIF2RX" },
2089
21ab3f2b 2090 { "IF1 DAC0", NULL, "I2S1" },
1319b2f6
OC		 2091 { "IF1 DAC1", NULL, "I2S1" },
2092 { "IF1 DAC2", NULL, "I2S1" },
21ab3f2b 2093 { "IF1 DAC3", NULL, "I2S1" },
1319b2f6
OC		 2094 { "IF2 DAC", NULL, "I2S2" },
2095
1319b2f6
OC		 2096 { "IF2 DAC L", NULL, "IF2 DAC" },
2097 { "IF2 DAC R", NULL, "IF2 DAC" },
2098
1319b2f6 2099 { "DAC1 L Mux", "IF2 DAC", "IF2 DAC L" },
1319b2f6
OC		 2100 { "DAC1 R Mux", "IF2 DAC", "IF2 DAC R" },
2101
2102 { "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL" },
2103 { "DAC1 MIXL", "DAC1 Switch", "DAC1 L Mux" },
2104 { "DAC1 MIXL", NULL, "dac stereo1 filter" },
2105 { "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR" },
2106 { "DAC1 MIXR", "DAC1 Switch", "DAC1 R Mux" },
2107 { "DAC1 MIXR", NULL, "dac stereo1 filter" },
2108
1319b2f6
OC		 2109 { "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" },
2110 { "DAC L2 Mux", "Mono ADC", "Mono ADC MIXL" },
2111 { "DAC L2 Mux", "VAD_ADC", "VAD_ADC" },
2112 { "DAC L2 Volume", NULL, "DAC L2 Mux" },
2113 { "DAC L2 Volume", NULL, "dac mono left filter" },
2114
1319b2f6
OC		 2115 { "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" },
2116 { "DAC R2 Mux", "Mono ADC", "Mono ADC MIXR" },
2117 { "DAC R2 Mux", "Haptic", "Haptic Generator" },
2118 { "DAC R2 Volume", NULL, "DAC R2 Mux" },
2119 { "DAC R2 Volume", NULL, "dac mono right filter" },
2120
2121 { "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
2122 { "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" },
2123 { "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2124 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
2125 { "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
2126 { "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" },
2127 { "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2128 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
2129
2130 { "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
2131 { "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2132 { "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
2133 { "Mono DAC MIXL", NULL, "dac mono left filter" },
2134 { "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
2135 { "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2136 { "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
2137 { "Mono DAC MIXR", NULL, "dac mono right filter" },
2138
2139 { "DAC MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
2140 { "DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2141 { "DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
2142 { "DAC MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
2143 { "DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2144 { "DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
2145
1319b2f6 2146 { "DAC L1", NULL, "PLL1", is_sys_clk_from_pll },
1319b2f6 2147 { "DAC R1", NULL, "PLL1", is_sys_clk_from_pll },
1319b2f6 2148 { "DAC L2", NULL, "PLL1", is_sys_clk_from_pll },
1319b2f6
OC		 2149 { "DAC R2", NULL, "PLL1", is_sys_clk_from_pll },
2150
2151 { "SPK MIXL", "BST1 Switch", "BST1" },
2152 { "SPK MIXL", "INL Switch", "INL VOL" },
2153 { "SPK MIXL", "DAC L1 Switch", "DAC L1" },
2154 { "SPK MIXL", "DAC L2 Switch", "DAC L2" },
2155 { "SPK MIXR", "BST2 Switch", "BST2" },
2156 { "SPK MIXR", "INR Switch", "INR VOL" },
2157 { "SPK MIXR", "DAC R1 Switch", "DAC R1" },
2158 { "SPK MIXR", "DAC R2 Switch", "DAC R2" },
2159
2160 { "OUT MIXL", "BST1 Switch", "BST1" },
2161 { "OUT MIXL", "INL Switch", "INL VOL" },
2162 { "OUT MIXL", "DAC L2 Switch", "DAC L2" },
2163 { "OUT MIXL", "DAC L1 Switch", "DAC L1" },
2164
2165 { "OUT MIXR", "BST2 Switch", "BST2" },
2166 { "OUT MIXR", "INR Switch", "INR VOL" },
2167 { "OUT MIXR", "DAC R2 Switch", "DAC R2" },
2168 { "OUT MIXR", "DAC R1 Switch", "DAC R1" },
2169
2170 { "HPOVOL MIXL", "DAC1 Switch", "DAC L1" },
2171 { "HPOVOL MIXL", "DAC2 Switch", "DAC L2" },
2172 { "HPOVOL MIXL", "INL Switch", "INL VOL" },
2173 { "HPOVOL MIXL", "BST1 Switch", "BST1" },
2174 { "HPOVOL MIXL", NULL, "HPOVOL MIXL Power" },
2175 { "HPOVOL MIXR", "DAC1 Switch", "DAC R1" },
2176 { "HPOVOL MIXR", "DAC2 Switch", "DAC R2" },
2177 { "HPOVOL MIXR", "INR Switch", "INR VOL" },
2178 { "HPOVOL MIXR", "BST2 Switch", "BST2" },
2179 { "HPOVOL MIXR", NULL, "HPOVOL MIXR Power" },
2180
2181 { "DAC 2", NULL, "DAC L2" },
2182 { "DAC 2", NULL, "DAC R2" },
2183 { "DAC 1", NULL, "DAC L1" },
2184 { "DAC 1", NULL, "DAC R1" },
2185 { "HPOVOL L", "Switch", "HPOVOL MIXL" },
2186 { "HPOVOL R", "Switch", "HPOVOL MIXR" },
2187 { "HPOVOL", NULL, "HPOVOL L" },
2188 { "HPOVOL", NULL, "HPOVOL R" },
2189 { "HPO MIX", "DAC1 Switch", "DAC 1" },
2190 { "HPO MIX", "HPVOL Switch", "HPOVOL" },
2191
2192 { "SPKVOL L", "Switch", "SPK MIXL" },
2193 { "SPKVOL R", "Switch", "SPK MIXR" },
2194
2195 { "SPOL MIX", "DAC R1 Switch", "DAC R1" },
2196 { "SPOL MIX", "DAC L1 Switch", "DAC L1" },
2197 { "SPOL MIX", "SPKVOL R Switch", "SPKVOL R" },
2198 { "SPOL MIX", "SPKVOL L Switch", "SPKVOL L" },
2199 { "SPOR MIX", "DAC R1 Switch", "DAC R1" },
2200 { "SPOR MIX", "SPKVOL R Switch", "SPKVOL R" },
2201
2202 { "LOUT MIX", "DAC L1 Switch", "DAC L1" },
2203 { "LOUT MIX", "DAC R1 Switch", "DAC R1" },
2204 { "LOUT MIX", "OUTMIX L Switch", "OUT MIXL" },
2205 { "LOUT MIX", "OUTMIX R Switch", "OUT MIXR" },
2206
2207 { "PDM1 L Mux", "Stereo DAC", "Stereo DAC MIXL" },
2208 { "PDM1 L Mux", "Mono DAC", "Mono DAC MIXL" },
2209 { "PDM1 L Mux", NULL, "PDM1 Power" },
2210 { "PDM1 R Mux", "Stereo DAC", "Stereo DAC MIXR" },
2211 { "PDM1 R Mux", "Mono DAC", "Mono DAC MIXR" },
2212 { "PDM1 R Mux", NULL, "PDM1 Power" },
2213
2214 { "HP amp", NULL, "HPO MIX" },
2215 { "HP amp", NULL, "JD Power" },
2216 { "HP amp", NULL, "Mic Det Power" },
2217 { "HP amp", NULL, "LDO2" },
2218 { "HPOL", NULL, "HP amp" },
2219 { "HPOR", NULL, "HP amp" },
2220
2221 { "LOUT amp", NULL, "LOUT MIX" },
2222 { "LOUTL", NULL, "LOUT amp" },
2223 { "LOUTR", NULL, "LOUT amp" },
2224
2225 { "PDM1 L", "Switch", "PDM1 L Mux" },
2226 { "PDM1 R", "Switch", "PDM1 R Mux" },
2227
2228 { "PDM1L", NULL, "PDM1 L" },
2229 { "PDM1R", NULL, "PDM1 R" },
2230
2231 { "SPK amp", NULL, "SPOL MIX" },
2232 { "SPK amp", NULL, "SPOR MIX" },
2233 { "SPOL", NULL, "SPK amp" },
2234 { "SPOR", NULL, "SPK amp" },
2235};
2236
5c4ca99d
BL		 2237static const struct snd_soc_dapm_route rt5650_specific_dapm_routes[] = {
2238 { "A DAC1 L Mux", "DAC1", "DAC1 MIXL"},
2239 { "A DAC1 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"},
2240 { "A DAC1 R Mux", "DAC1", "DAC1 MIXR"},
2241 { "A DAC1 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"},
2242
2243 { "A DAC2 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"},
2244 { "A DAC2 L Mux", "Mono DAC Mixer", "Mono DAC MIXL"},
2245 { "A DAC2 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"},
2246 { "A DAC2 R Mux", "Mono DAC Mixer", "Mono DAC MIXR"},
2247
2248 { "DAC L1", NULL, "A DAC1 L Mux" },
2249 { "DAC R1", NULL, "A DAC1 R Mux" },
2250 { "DAC L2", NULL, "A DAC2 L Mux" },
2251 { "DAC R2", NULL, "A DAC2 R Mux" },
21ab3f2b
BL		 2252
2253 { "RT5650 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" },
2254 { "RT5650 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" },
2255 { "RT5650 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" },
2256 { "RT5650 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" },
2257
2258 { "RT5650 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" },
2259 { "RT5650 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" },
2260 { "RT5650 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" },
2261 { "RT5650 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" },
2262
2263 { "RT5650 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" },
2264 { "RT5650 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" },
2265 { "RT5650 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" },
2266 { "RT5650 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" },
2267
2268 { "IF1 ADC", NULL, "RT5650 IF1 ADC1 Swap Mux" },
2269 { "IF1 ADC", NULL, "RT5650 IF1 ADC2 Swap Mux" },
2270 { "IF1 ADC", NULL, "RT5650 IF1 ADC3 Swap Mux" },
2271
2272 { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/DAC_REF/Null", "IF1 ADC" },
2273 { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/Null/DAC_REF", "IF1 ADC" },
2274 { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/IF_ADC2/Null", "IF1 ADC" },
2275 { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/Null/IF_ADC2", "IF1 ADC" },
2276 { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/DAC_REF/IF_ADC2", "IF1 ADC" },
2277 { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/IF_ADC2/DAC_REF", "IF1 ADC" },
2278
2279 { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/DAC_REF/Null", "IF1 ADC" },
2280 { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/Null/DAC_REF", "IF1 ADC" },
2281 { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/IF_ADC1/Null", "IF1 ADC" },
2282 { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/Null/IF_ADC1", "IF1 ADC" },
2283 { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/DAC_REF/IF_ADC1", "IF1 ADC" },
2284 { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/IF_ADC1/DAC_REF", "IF1 ADC" },
2285
2286 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/IF_ADC2/Null", "IF1 ADC" },
2287 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/Null/IF_ADC2", "IF1 ADC" },
2288 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/IF_ADC1/Null", "IF1 ADC" },
2289 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/Null/IF_ADC1", "IF1 ADC" },
2290 { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC1/IF_ADC2", "IF1 ADC" },
2291 { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC2/IF_ADC1", "IF1 ADC" },
2292
2293 { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/IF_ADC2/DAC_REF", "IF1 ADC" },
2294 { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/DAC_REF/IF_ADC2", "IF1 ADC" },
2295 { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/IF_ADC1/DAC_REF", "IF1 ADC" },
2296 { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/DAC_REF/IF_ADC1", "IF1 ADC" },
2297 { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC1/IF_ADC2", "IF1 ADC" },
2298 { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC2/IF_ADC1", "IF1 ADC" },
2299 { "AIF1TX", NULL, "RT5650 IF1 ADC Mux" },
2300
2301 { "RT5650 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" },
2302 { "RT5650 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" },
2303 { "RT5650 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" },
2304 { "RT5650 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" },
2305
2306 { "RT5650 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" },
2307 { "RT5650 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" },
2308 { "RT5650 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" },
2309 { "RT5650 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" },
2310
2311 { "RT5650 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" },
2312 { "RT5650 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" },
2313 { "RT5650 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" },
2314 { "RT5650 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" },
2315
2316 { "RT5650 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" },
2317 { "RT5650 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" },
2318 { "RT5650 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" },
2319 { "RT5650 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" },
2320
2321 { "DAC1 L Mux", "IF1 DAC", "RT5650 IF1 DAC1 L Mux" },
2322 { "DAC1 R Mux", "IF1 DAC", "RT5650 IF1 DAC1 R Mux" },
2323
2324 { "DAC L2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 L Mux" },
2325 { "DAC R2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 R Mux" },
5c4ca99d
BL		 2326};
2327
2328static const struct snd_soc_dapm_route rt5645_specific_dapm_routes[] = {
2329 { "DAC L1", NULL, "Stereo DAC MIXL" },
2330 { "DAC R1", NULL, "Stereo DAC MIXR" },
2331 { "DAC L2", NULL, "Mono DAC MIXL" },
2332 { "DAC R2", NULL, "Mono DAC MIXR" },
21ab3f2b
BL		 2333
2334 { "RT5645 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" },
2335 { "RT5645 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" },
2336 { "RT5645 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" },
2337 { "RT5645 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" },
2338
2339 { "RT5645 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" },
2340 { "RT5645 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" },
2341 { "RT5645 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" },
2342 { "RT5645 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" },
2343
2344 { "RT5645 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" },
2345 { "RT5645 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" },
2346 { "RT5645 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" },
2347 { "RT5645 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" },
2348
2349 { "IF1 ADC", NULL, "RT5645 IF1 ADC1 Swap Mux" },
2350 { "IF1 ADC", NULL, "RT5645 IF1 ADC2 Swap Mux" },
2351 { "IF1 ADC", NULL, "RT5645 IF1 ADC3 Swap Mux" },
2352
2353 { "RT5645 IF1 ADC Mux", "IF_ADC1/IF_ADC2/VAD_ADC", "IF1 ADC" },
2354 { "RT5645 IF1 ADC Mux", "IF_ADC2/IF_ADC1/VAD_ADC", "IF1 ADC" },
2355 { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC1/IF_ADC2", "IF1 ADC" },
2356 { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC2/IF_ADC1", "IF1 ADC" },
2357 { "AIF1TX", NULL, "RT5645 IF1 ADC Mux" },
2358
2359 { "RT5645 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" },
2360 { "RT5645 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" },
2361 { "RT5645 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" },
2362 { "RT5645 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" },
2363
2364 { "RT5645 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" },
2365 { "RT5645 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" },
2366 { "RT5645 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" },
2367 { "RT5645 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" },
2368
2369 { "RT5645 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" },
2370 { "RT5645 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" },
2371 { "RT5645 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" },
2372 { "RT5645 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" },
2373
2374 { "RT5645 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" },
2375 { "RT5645 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" },
2376 { "RT5645 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" },
2377 { "RT5645 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" },
2378
2379 { "DAC1 L Mux", "IF1 DAC", "RT5645 IF1 DAC1 L Mux" },
2380 { "DAC1 R Mux", "IF1 DAC", "RT5645 IF1 DAC1 R Mux" },
2381
2382 { "DAC L2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 L Mux" },
2383 { "DAC R2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 R Mux" },
5c4ca99d
BL		 2384};
2385
1319b2f6
OC		 2386static int rt5645_hw_params(struct snd_pcm_substream *substream,
2387 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2388{
2389 struct snd_soc_codec *codec = dai->codec;
2390 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
57bf2736 2391 unsigned int val_len = 0, val_clk, mask_clk, dl_sft;
1319b2f6
OC		 2392 int pre_div, bclk_ms, frame_size;
2393
2394 rt5645->lrck[dai->id] = params_rate(params);
d92950e7 2395 pre_div = rl6231_get_clk_info(rt5645->sysclk, rt5645->lrck[dai->id]);
1319b2f6
OC		 2396 if (pre_div < 0) {
2397 dev_err(codec->dev, "Unsupported clock setting\n");
2398 return -EINVAL;
2399 }
2400 frame_size = snd_soc_params_to_frame_size(params);
2401 if (frame_size < 0) {
2402 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
2403 return -EINVAL;
2404 }
57bf2736
BL		 2405
2406 switch (rt5645->codec_type) {
2407 case CODEC_TYPE_RT5650:
2408 dl_sft = 4;
2409 break;
2410 default:
2411 dl_sft = 2;
2412 break;
2413 }
2414
1319b2f6
OC		 2415 bclk_ms = frame_size > 32;
2416 rt5645->bclk[dai->id] = rt5645->lrck[dai->id] * (32 << bclk_ms);
2417
2418 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
2419 rt5645->bclk[dai->id], rt5645->lrck[dai->id]);
2420 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
2421 bclk_ms, pre_div, dai->id);
2422
2423 switch (params_width(params)) {
2424 case 16:
2425 break;
2426 case 20:
57bf2736 2427 val_len = 0x1;
1319b2f6
OC		 2428 break;
2429 case 24:
57bf2736 2430 val_len = 0x2;
1319b2f6
OC		 2431 break;
2432 case 8:
57bf2736 2433 val_len = 0x3;
1319b2f6
OC		 2434 break;
2435 default:
2436 return -EINVAL;
2437 }
2438
2439 switch (dai->id) {
2440 case RT5645_AIF1:
33de3d54
BL		 2441 mask_clk = RT5645_I2S_PD1_MASK;
2442 val_clk = pre_div << RT5645_I2S_PD1_SFT;
1319b2f6 2443 snd_soc_update_bits(codec, RT5645_I2S1_SDP,
57bf2736 2444 (0x3 << dl_sft), (val_len << dl_sft));
1319b2f6
OC		 2445 snd_soc_update_bits(codec, RT5645_ADDA_CLK1, mask_clk, val_clk);
2446 break;
2447 case RT5645_AIF2:
2448 mask_clk = RT5645_I2S_BCLK_MS2_MASK | RT5645_I2S_PD2_MASK;
2449 val_clk = bclk_ms << RT5645_I2S_BCLK_MS2_SFT |
2450 pre_div << RT5645_I2S_PD2_SFT;
2451 snd_soc_update_bits(codec, RT5645_I2S2_SDP,
57bf2736 2452 (0x3 << dl_sft), (val_len << dl_sft));
1319b2f6
OC		 2453 snd_soc_update_bits(codec, RT5645_ADDA_CLK1, mask_clk, val_clk);
2454 break;
2455 default:
2456 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2457 return -EINVAL;
2458 }
2459
2460 return 0;
2461}
2462
2463static int rt5645_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2464{
2465 struct snd_soc_codec *codec = dai->codec;
2466 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
57bf2736
BL		 2467 unsigned int reg_val = 0, pol_sft;
2468
2469 switch (rt5645->codec_type) {
2470 case CODEC_TYPE_RT5650:
2471 pol_sft = 8;
2472 break;
2473 default:
2474 pol_sft = 7;
2475 break;
2476 }
1319b2f6
OC		 2477
2478 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2479 case SND_SOC_DAIFMT_CBM_CFM:
2480 rt5645->master[dai->id] = 1;
2481 break;
2482 case SND_SOC_DAIFMT_CBS_CFS:
2483 reg_val |= RT5645_I2S_MS_S;
2484 rt5645->master[dai->id] = 0;
2485 break;
2486 default:
2487 return -EINVAL;
2488 }
2489
2490 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2491 case SND_SOC_DAIFMT_NB_NF:
2492 break;
2493 case SND_SOC_DAIFMT_IB_NF:
57bf2736 2494 reg_val |= (1 << pol_sft);
1319b2f6
OC		 2495 break;
2496 default:
2497 return -EINVAL;
2498 }
2499
2500 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2501 case SND_SOC_DAIFMT_I2S:
2502 break;
2503 case SND_SOC_DAIFMT_LEFT_J:
2504 reg_val |= RT5645_I2S_DF_LEFT;
2505 break;
2506 case SND_SOC_DAIFMT_DSP_A:
2507 reg_val |= RT5645_I2S_DF_PCM_A;
2508 break;
2509 case SND_SOC_DAIFMT_DSP_B:
2510 reg_val |= RT5645_I2S_DF_PCM_B;
2511 break;
2512 default:
2513 return -EINVAL;
2514 }
2515 switch (dai->id) {
2516 case RT5645_AIF1:
2517 snd_soc_update_bits(codec, RT5645_I2S1_SDP,
57bf2736 2518 RT5645_I2S_MS_MASK | (1 << pol_sft) |
1319b2f6
OC		 2519 RT5645_I2S_DF_MASK, reg_val);
2520 break;
8c325704
AL		 2521 case RT5645_AIF2:
2522 snd_soc_update_bits(codec, RT5645_I2S2_SDP,
57bf2736 2523 RT5645_I2S_MS_MASK | (1 << pol_sft) |
1319b2f6
OC		 2524 RT5645_I2S_DF_MASK, reg_val);
2525 break;
2526 default:
2527 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2528 return -EINVAL;
2529 }
2530 return 0;
2531}
2532
2533static int rt5645_set_dai_sysclk(struct snd_soc_dai *dai,
2534 int clk_id, unsigned int freq, int dir)
2535{
2536 struct snd_soc_codec *codec = dai->codec;
2537 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2538 unsigned int reg_val = 0;
2539
2540 if (freq == rt5645->sysclk && clk_id == rt5645->sysclk_src)
2541 return 0;
2542
2543 switch (clk_id) {
2544 case RT5645_SCLK_S_MCLK:
2545 reg_val |= RT5645_SCLK_SRC_MCLK;
2546 break;
2547 case RT5645_SCLK_S_PLL1:
2548 reg_val |= RT5645_SCLK_SRC_PLL1;
2549 break;
2550 case RT5645_SCLK_S_RCCLK:
2551 reg_val |= RT5645_SCLK_SRC_RCCLK;
2552 break;
2553 default:
2554 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
2555 return -EINVAL;
2556 }
2557 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2558 RT5645_SCLK_SRC_MASK, reg_val);
2559 rt5645->sysclk = freq;
2560 rt5645->sysclk_src = clk_id;
2561
2562 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
2563
2564 return 0;
2565}
2566
1319b2f6
OC		 2567static int rt5645_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2568 unsigned int freq_in, unsigned int freq_out)
2569{
2570 struct snd_soc_codec *codec = dai->codec;
2571 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
71c7a2d6 2572 struct rl6231_pll_code pll_code;
1319b2f6
OC		 2573 int ret;
2574
2575 if (source == rt5645->pll_src && freq_in == rt5645->pll_in &&
2576 freq_out == rt5645->pll_out)
2577 return 0;
2578
2579 if (!freq_in || !freq_out) {
2580 dev_dbg(codec->dev, "PLL disabled\n");
2581
2582 rt5645->pll_in = 0;
2583 rt5645->pll_out = 0;
2584 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2585 RT5645_SCLK_SRC_MASK, RT5645_SCLK_SRC_MCLK);
2586 return 0;
2587 }
2588
2589 switch (source) {
2590 case RT5645_PLL1_S_MCLK:
2591 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2592 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_MCLK);
2593 break;
2594 case RT5645_PLL1_S_BCLK1:
2595 case RT5645_PLL1_S_BCLK2:
2596 switch (dai->id) {
2597 case RT5645_AIF1:
2598 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2599 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK1);
2600 break;
2601 case RT5645_AIF2:
2602 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2603 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK2);
2604 break;
2605 default:
2606 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2607 return -EINVAL;
2608 }
2609 break;
2610 default:
2611 dev_err(codec->dev, "Unknown PLL source %d\n", source);
2612 return -EINVAL;
2613 }
2614
71c7a2d6 2615 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
1319b2f6
OC		 2616 if (ret < 0) {
2617 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
2618 return ret;
2619 }
2620
2621 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
2622 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2623 pll_code.n_code, pll_code.k_code);
2624
2625 snd_soc_write(codec, RT5645_PLL_CTRL1,
2626 pll_code.n_code << RT5645_PLL_N_SFT | pll_code.k_code);
2627 snd_soc_write(codec, RT5645_PLL_CTRL2,
2628 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5645_PLL_M_SFT |
2629 pll_code.m_bp << RT5645_PLL_M_BP_SFT);
2630
2631 rt5645->pll_in = freq_in;
2632 rt5645->pll_out = freq_out;
2633 rt5645->pll_src = source;
2634
2635 return 0;
2636}
2637
2638static int rt5645_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2639 unsigned int rx_mask, int slots, int slot_width)
2640{
2641 struct snd_soc_codec *codec = dai->codec;
42ce5b8a
BL		 2642 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2643 unsigned int i_slot_sft, o_slot_sft, i_width_sht, o_width_sht, en_sft;
2644 unsigned int mask, val = 0;
2645
2646 switch (rt5645->codec_type) {
2647 case CODEC_TYPE_RT5650:
2648 en_sft = 15;
2649 i_slot_sft = 10;
2650 o_slot_sft = 8;
2651 i_width_sht = 6;
2652 o_width_sht = 4;
2653 mask = 0x8ff0;
2654 break;
2655 default:
2656 en_sft = 14;
2657 i_slot_sft = o_slot_sft = 12;
2658 i_width_sht = o_width_sht = 10;
2659 mask = 0x7c00;
2660 break;
2661 }
850577db 2662 if (rx_mask || tx_mask) {
42ce5b8a
BL		 2663 val |= (1 << en_sft);
2664 if (rt5645->codec_type == CODEC_TYPE_RT5645)
2665 snd_soc_update_bits(codec, RT5645_BASS_BACK,
2666 RT5645_G_BB_BST_MASK, RT5645_G_BB_BST_25DB);
850577db 2667 }
1319b2f6
OC		 2668
2669 switch (slots) {
2670 case 4:
42ce5b8a 2671 val |= (1 << i_slot_sft) | (1 << o_slot_sft);
1319b2f6
OC		 2672 break;
2673 case 6:
42ce5b8a 2674 val |= (2 << i_slot_sft) | (2 << o_slot_sft);
1319b2f6
OC		 2675 break;
2676 case 8:
42ce5b8a 2677 val |= (3 << i_slot_sft) | (3 << o_slot_sft);
1319b2f6
OC		 2678 break;
2679 case 2:
2680 default:
2681 break;
2682 }
2683
2684 switch (slot_width) {
2685 case 20:
42ce5b8a 2686 val |= (1 << i_width_sht) | (1 << o_width_sht);
1319b2f6
OC		 2687 break;
2688 case 24:
42ce5b8a 2689 val |= (2 << i_width_sht) | (2 << o_width_sht);
1319b2f6
OC		 2690 break;
2691 case 32:
42ce5b8a 2692 val |= (3 << i_width_sht) | (3 << o_width_sht);
1319b2f6
OC		 2693 break;
2694 case 16:
2695 default:
2696 break;
2697 }
2698
42ce5b8a 2699 snd_soc_update_bits(codec, RT5645_TDM_CTRL_1, mask, val);
1319b2f6
OC		 2700
2701 return 0;
2702}
2703
2704static int rt5645_set_bias_level(struct snd_soc_codec *codec,
2705 enum snd_soc_bias_level level)
2706{
6e747d53
BL		 2707 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2708
1319b2f6 2709 switch (level) {
0b2e4959 2710 case SND_SOC_BIAS_PREPARE:
e2ada818 2711 if (SND_SOC_BIAS_STANDBY == snd_soc_codec_get_bias_level(codec)) {
1319b2f6
OC		 2712 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2713 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2714 RT5645_PWR_BG | RT5645_PWR_VREF2,
2715 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2716 RT5645_PWR_BG | RT5645_PWR_VREF2);
2717 mdelay(10);
2718 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2719 RT5645_PWR_FV1 | RT5645_PWR_FV2,
2720 RT5645_PWR_FV1 | RT5645_PWR_FV2);
2721 snd_soc_update_bits(codec, RT5645_GEN_CTRL1,
2722 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL);
2723 }
2724 break;
2725
0b2e4959
BL		 2726 case SND_SOC_BIAS_STANDBY:
2727 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2728 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2729 RT5645_PWR_BG | RT5645_PWR_VREF2,
2730 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2731 RT5645_PWR_BG | RT5645_PWR_VREF2);
2732 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2733 RT5645_PWR_FV1 | RT5645_PWR_FV2,
2734 RT5645_PWR_FV1 | RT5645_PWR_FV2);
2735 break;
2736
1319b2f6
OC		 2737 case SND_SOC_BIAS_OFF:
2738 snd_soc_write(codec, RT5645_DEPOP_M2, 0x1100);
6e747d53
BL		 2739 if (!rt5645->en_button_func)
2740 snd_soc_update_bits(codec, RT5645_GEN_CTRL1,
2741 RT5645_DIG_GATE_CTRL, 0);
0b2e4959
BL		 2742 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2743 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2744 RT5645_PWR_BG | RT5645_PWR_VREF2 |
2745 RT5645_PWR_FV1 | RT5645_PWR_FV2, 0x0);
1319b2f6
OC		 2746 break;
2747
2748 default:
2749 break;
2750 }
1319b2f6
OC		 2751
2752 return 0;
2753}
2754
6e747d53
BL		 2755static void rt5645_enable_push_button_irq(struct snd_soc_codec *codec,
2756 bool enable)
f3fa1bbd 2757{
e2ada818 2758 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
f3fa1bbd 2759
6e747d53 2760 if (enable) {
a4e3c5fa
NB		 2761 snd_soc_dapm_force_enable_pin(dapm, "ADC L power");
2762 snd_soc_dapm_force_enable_pin(dapm, "ADC R power");
2763 snd_soc_dapm_sync(dapm);
22f5d9f8 2764
6e747d53
BL		 2765 snd_soc_update_bits(codec,
2766 RT5645_INT_IRQ_ST, 0x8, 0x8);
2767 snd_soc_update_bits(codec,
2768 RT5650_4BTN_IL_CMD2, 0x8000, 0x8000);
2769 snd_soc_read(codec, RT5650_4BTN_IL_CMD1);
2770 pr_debug("%s read %x = %x\n", __func__, RT5650_4BTN_IL_CMD1,
2771 snd_soc_read(codec, RT5650_4BTN_IL_CMD1));
2772 } else {
2773 snd_soc_update_bits(codec, RT5650_4BTN_IL_CMD2, 0x8000, 0x0);
2774 snd_soc_update_bits(codec, RT5645_INT_IRQ_ST, 0x8, 0x0);
22f5d9f8 2775
a4e3c5fa
NB		 2776 snd_soc_dapm_disable_pin(dapm, "ADC L power");
2777 snd_soc_dapm_disable_pin(dapm, "ADC R power");
2778 snd_soc_dapm_sync(dapm);
75945896 2779 }
6e747d53 2780}
f3fa1bbd 2781
6e747d53
BL		 2782static int rt5645_jack_detect(struct snd_soc_codec *codec, int jack_insert)
2783{
e2ada818 2784 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
6e747d53
BL		 2785 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2786 unsigned int val;
f3fa1bbd 2787
6e747d53 2788 if (jack_insert) {
05a9b46a
JL		 2789 regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0006);
2790
b14c9174
NB		 2791 /* for jack type detect */
2792 snd_soc_dapm_force_enable_pin(dapm, "LDO2");
2793 snd_soc_dapm_force_enable_pin(dapm, "Mic Det Power");
2794 snd_soc_dapm_sync(dapm);
2795 if (!dapm->card->instantiated) {
6e747d53
BL		 2796 /* Power up necessary bits for JD if dapm is
2797 not ready yet */
05a9b46a
JL		 2798 regmap_update_bits(rt5645->regmap, RT5645_PWR_ANLG1,
2799 RT5645_PWR_MB | RT5645_PWR_VREF2,
2800 RT5645_PWR_MB | RT5645_PWR_VREF2);
2801 regmap_update_bits(rt5645->regmap, RT5645_PWR_MIXER,
6e747d53 2802 RT5645_PWR_LDO2, RT5645_PWR_LDO2);
05a9b46a 2803 regmap_update_bits(rt5645->regmap, RT5645_PWR_VOL,
6e747d53
BL		 2804 RT5645_PWR_MIC_DET, RT5645_PWR_MIC_DET);
2805 }
f3fa1bbd 2806
05a9b46a 2807 regmap_write(rt5645->regmap, RT5645_JD_CTRL3, 0x00f0);
05a9b46a
JL		 2808 regmap_update_bits(rt5645->regmap,
2809 RT5645_IN1_CTRL2, 0x1000, 0x1000);
8db7f56d
OC		 2810 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1, 0x0004,
2811 0x0004);
05a9b46a
JL		 2812 msleep(100);
2813 regmap_update_bits(rt5645->regmap,
2814 RT5645_IN1_CTRL2, 0x1000, 0x0000);
2815
8db7f56d 2816 msleep(600);
05a9b46a
JL		 2817 regmap_read(rt5645->regmap, RT5645_IN1_CTRL3, &val);
2818 val &= 0x7;
f3fa1bbd
OC		 2819 dev_dbg(codec->dev, "val = %d\n", val);
2820
6e747d53
BL		 2821 if (val == 1 || val == 2) {
2822 rt5645->jack_type = SND_JACK_HEADSET;
2823 if (rt5645->en_button_func) {
6e747d53
BL		 2824 rt5645_enable_push_button_irq(codec, true);
2825 }
2826 } else {
b14c9174
NB		 2827 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
2828 snd_soc_dapm_sync(dapm);
6e747d53
BL		 2829 rt5645->jack_type = SND_JACK_HEADPHONE;
2830 }
2831
8db7f56d
OC		 2832 snd_soc_update_bits(codec, RT5645_CHARGE_PUMP, 0x0300, 0x0200);
2833 snd_soc_write(codec, RT5645_DEPOP_M1, 0x001d);
2834 snd_soc_write(codec, RT5645_DEPOP_M1, 0x0001);
6e747d53
BL		 2835 } else { /* jack out */
2836 rt5645->jack_type = 0;
a4e3c5fa 2837
8db7f56d
OC		 2838 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2, 0x1000,
2839 0x1000);
2840 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1, 0x0004,
2841 0x0000);
2842
6e747d53
BL		 2843 if (rt5645->en_button_func)
2844 rt5645_enable_push_button_irq(codec, false);
a4e3c5fa
NB		 2845
2846 if (rt5645->pdata.jd_mode == 0)
2847 snd_soc_dapm_disable_pin(dapm, "LDO2");
2848 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
2849 snd_soc_dapm_sync(dapm);
f3fa1bbd
OC		 2850 }
2851
6e747d53 2852 return rt5645->jack_type;
f3fa1bbd
OC		 2853}
2854
f312bc59
NB		 2855static int rt5645_button_detect(struct snd_soc_codec *codec)
2856{
2857 int btn_type, val;
2858
2859 val = snd_soc_read(codec, RT5650_4BTN_IL_CMD1);
2860 pr_debug("val=0x%x\n", val);
2861 btn_type = val & 0xfff0;
2862 snd_soc_write(codec, RT5650_4BTN_IL_CMD1, val);
2863
2864 return btn_type;
2865}
2866
345b0f50 2867static irqreturn_t rt5645_irq(int irq, void *data);
d5660422 2868
f3fa1bbd 2869int rt5645_set_jack_detect(struct snd_soc_codec *codec,
6e747d53
BL		 2870 struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack,
2871 struct snd_soc_jack *btn_jack)
f3fa1bbd
OC		 2872{
2873 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2874
471f208a
BL		 2875 rt5645->hp_jack = hp_jack;
2876 rt5645->mic_jack = mic_jack;
6e747d53
BL		 2877 rt5645->btn_jack = btn_jack;
2878 if (rt5645->btn_jack && rt5645->codec_type == CODEC_TYPE_RT5650) {
2879 rt5645->en_button_func = true;
2880 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2881 RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ);
2882 regmap_update_bits(rt5645->regmap, RT5645_DEPOP_M1,
2883 RT5645_HP_CB_MASK, RT5645_HP_CB_PU);
2884 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL1,
2885 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL);
2886 }
345b0f50 2887 rt5645_irq(0, rt5645);
f3fa1bbd
OC		 2888
2889 return 0;
2890}
2891EXPORT_SYMBOL_GPL(rt5645_set_jack_detect);
2892
cd6e82b8
OC		 2893static void rt5645_jack_detect_work(struct work_struct *work)
2894{
2895 struct rt5645_priv *rt5645 =
2896 container_of(work, struct rt5645_priv, jack_detect_work.work);
6e747d53
BL		 2897 int val, btn_type, gpio_state = 0, report = 0;
2898
f2a5ded3 2899 if (!rt5645->codec)
f136dce4 2900 return;
f2a5ded3 2901
6e747d53
BL		 2902 switch (rt5645->pdata.jd_mode) {
2903 case 0: /* Not using rt5645 JD */
0b0cefc8
OC		 2904 if (rt5645->gpiod_hp_det) {
2905 gpio_state = gpiod_get_value(rt5645->gpiod_hp_det);
2906 dev_dbg(rt5645->codec->dev, "gpio_state = %d\n",
2907 gpio_state);
2908 report = rt5645_jack_detect(rt5645->codec, gpio_state);
6e747d53
BL		 2909 }
2910 snd_soc_jack_report(rt5645->hp_jack,
2911 report, SND_JACK_HEADPHONE);
2912 snd_soc_jack_report(rt5645->mic_jack,
2913 report, SND_JACK_MICROPHONE);
f312bc59 2914 return;
6e747d53
BL		 2915 case 1: /* 2 port */
2916 val = snd_soc_read(rt5645->codec, RT5645_A_JD_CTRL1) & 0x0070;
2917 break;
2918 default: /* 1 port */
2919 val = snd_soc_read(rt5645->codec, RT5645_A_JD_CTRL1) & 0x0020;
2920 break;
2921
2922 }
2923
2924 switch (val) {
2925 /* jack in */
2926 case 0x30: /* 2 port */
2927 case 0x0: /* 1 port or 2 port */
2928 if (rt5645->jack_type == 0) {
2929 report = rt5645_jack_detect(rt5645->codec, 1);
2930 /* for push button and jack out */
2931 break;
2932 }
2933 btn_type = 0;
2934 if (snd_soc_read(rt5645->codec, RT5645_INT_IRQ_ST) & 0x4) {
2935 /* button pressed */
2936 report = SND_JACK_HEADSET;
2937 btn_type = rt5645_button_detect(rt5645->codec);
2938 /* rt5650 can report three kinds of button behavior,
2939 one click, double click and hold. However,
2940 currently we will report button pressed/released
2941 event. So all the three button behaviors are
2942 treated as button pressed. */
2943 switch (btn_type) {
2944 case 0x8000:
2945 case 0x4000:
2946 case 0x2000:
2947 report |= SND_JACK_BTN_0;
2948 break;
2949 case 0x1000:
2950 case 0x0800:
2951 case 0x0400:
2952 report |= SND_JACK_BTN_1;
2953 break;
2954 case 0x0200:
2955 case 0x0100:
2956 case 0x0080:
2957 report |= SND_JACK_BTN_2;
2958 break;
2959 case 0x0040:
2960 case 0x0020:
2961 case 0x0010:
2962 report |= SND_JACK_BTN_3;
2963 break;
2964 case 0x0000: /* unpressed */
2965 break;
2966 default:
2967 dev_err(rt5645->codec->dev,
2968 "Unexpected button code 0x%04x\n",
2969 btn_type);
2970 break;
2971 }
2972 }
2973 if (btn_type == 0)/* button release */
2974 report = rt5645->jack_type;
2975
2976 break;
2977 /* jack out */
2978 case 0x70: /* 2 port */
2979 case 0x10: /* 2 port */
2980 case 0x20: /* 1 port */
2981 report = 0;
2982 snd_soc_update_bits(rt5645->codec,
2983 RT5645_INT_IRQ_ST, 0x1, 0x0);
2984 rt5645_jack_detect(rt5645->codec, 0);
2985 break;
2986 default:
2987 break;
2988 }
2989
2990 snd_soc_jack_report(rt5645->hp_jack, report, SND_JACK_HEADPHONE);
2991 snd_soc_jack_report(rt5645->mic_jack, report, SND_JACK_MICROPHONE);
2992 if (rt5645->en_button_func)
2993 snd_soc_jack_report(rt5645->btn_jack,
e0b5d906
BL		 2994 report, SND_JACK_BTN_0 | SND_JACK_BTN_1 |
2995 SND_JACK_BTN_2 | SND_JACK_BTN_3);
f312bc59 2996}
6e747d53 2997
f312bc59
NB		 2998static irqreturn_t rt5645_irq(int irq, void *data)
2999{
3000 struct rt5645_priv *rt5645 = data;
3001
3002 queue_delayed_work(system_power_efficient_wq,
3003 &rt5645->jack_detect_work, msecs_to_jiffies(250));
3004
3005 return IRQ_HANDLED;
6e747d53
BL		 3006}
3007
1319b2f6
OC		 3008static int rt5645_probe(struct snd_soc_codec *codec)
3009{
e2ada818 3010 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
1319b2f6
OC		 3011 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
3012
3013 rt5645->codec = codec;
3014
5c4ca99d
BL		 3015 switch (rt5645->codec_type) {
3016 case CODEC_TYPE_RT5645:
f2a76385 3017 snd_soc_dapm_new_controls(dapm,
83c09290
BL		 3018 rt5645_specific_dapm_widgets,
3019 ARRAY_SIZE(rt5645_specific_dapm_widgets));
e2ada818 3020 snd_soc_dapm_add_routes(dapm,
5c4ca99d
BL		 3021 rt5645_specific_dapm_routes,
3022 ARRAY_SIZE(rt5645_specific_dapm_routes));
3023 break;
3024 case CODEC_TYPE_RT5650:
e2ada818 3025 snd_soc_dapm_new_controls(dapm,
5c4ca99d
BL		 3026 rt5650_specific_dapm_widgets,
3027 ARRAY_SIZE(rt5650_specific_dapm_widgets));
e2ada818 3028 snd_soc_dapm_add_routes(dapm,
5c4ca99d
BL		 3029 rt5650_specific_dapm_routes,
3030 ARRAY_SIZE(rt5650_specific_dapm_routes));
3031 break;
3032 }
3033
bd1204cb 3034 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF);
1319b2f6 3035
bb656add 3036 /* for JD function */
ac4fc3ee 3037 if (rt5645->pdata.jd_mode) {
e2ada818
LPC		 3038 snd_soc_dapm_force_enable_pin(dapm, "JD Power");
3039 snd_soc_dapm_force_enable_pin(dapm, "LDO2");
3040 snd_soc_dapm_sync(dapm);
bb656add
BL		 3041 }
3042
1319b2f6
OC		 3043 return 0;
3044}
3045
3046static int rt5645_remove(struct snd_soc_codec *codec)
3047{
3048 rt5645_reset(codec);
3049 return 0;
3050}
3051
3052#ifdef CONFIG_PM
3053static int rt5645_suspend(struct snd_soc_codec *codec)
3054{
3055 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
3056
3057 regcache_cache_only(rt5645->regmap, true);
3058 regcache_mark_dirty(rt5645->regmap);
3059
3060 return 0;
3061}
3062
3063static int rt5645_resume(struct snd_soc_codec *codec)
3064{
3065 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
3066
3067 regcache_cache_only(rt5645->regmap, false);
0f776efd 3068 regcache_sync(rt5645->regmap);
1319b2f6
OC		 3069
3070 return 0;
3071}
3072#else
3073#define rt5645_suspend NULL
3074#define rt5645_resume NULL
3075#endif
3076
3077#define RT5645_STEREO_RATES SNDRV_PCM_RATE_8000_96000
3078#define RT5645_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
3079 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
3080
9e22f782 3081static struct snd_soc_dai_ops rt5645_aif_dai_ops = {
1319b2f6
OC		 3082 .hw_params = rt5645_hw_params,
3083 .set_fmt = rt5645_set_dai_fmt,
3084 .set_sysclk = rt5645_set_dai_sysclk,
3085 .set_tdm_slot = rt5645_set_tdm_slot,
3086 .set_pll = rt5645_set_dai_pll,
3087};
3088
9e22f782 3089static struct snd_soc_dai_driver rt5645_dai[] = {
1319b2f6
OC		 3090 {
3091 .name = "rt5645-aif1",
3092 .id = RT5645_AIF1,
3093 .playback = {
3094 .stream_name = "AIF1 Playback",
3095 .channels_min = 1,
3096 .channels_max = 2,
3097 .rates = RT5645_STEREO_RATES,
3098 .formats = RT5645_FORMATS,
3099 },
3100 .capture = {
3101 .stream_name = "AIF1 Capture",
3102 .channels_min = 1,
3103 .channels_max = 2,
3104 .rates = RT5645_STEREO_RATES,
3105 .formats = RT5645_FORMATS,
3106 },
3107 .ops = &rt5645_aif_dai_ops,
3108 },
3109 {
3110 .name = "rt5645-aif2",
3111 .id = RT5645_AIF2,
3112 .playback = {
3113 .stream_name = "AIF2 Playback",
3114 .channels_min = 1,
3115 .channels_max = 2,
3116 .rates = RT5645_STEREO_RATES,
3117 .formats = RT5645_FORMATS,
3118 },
3119 .capture = {
3120 .stream_name = "AIF2 Capture",
3121 .channels_min = 1,
3122 .channels_max = 2,
3123 .rates = RT5645_STEREO_RATES,
3124 .formats = RT5645_FORMATS,
3125 },
3126 .ops = &rt5645_aif_dai_ops,
3127 },
3128};
3129
3130static struct snd_soc_codec_driver soc_codec_dev_rt5645 = {
3131 .probe = rt5645_probe,
3132 .remove = rt5645_remove,
3133 .suspend = rt5645_suspend,
3134 .resume = rt5645_resume,
3135 .set_bias_level = rt5645_set_bias_level,
3136 .idle_bias_off = true,
3137 .controls = rt5645_snd_controls,
3138 .num_controls = ARRAY_SIZE(rt5645_snd_controls),
3139 .dapm_widgets = rt5645_dapm_widgets,
3140 .num_dapm_widgets = ARRAY_SIZE(rt5645_dapm_widgets),
3141 .dapm_routes = rt5645_dapm_routes,
3142 .num_dapm_routes = ARRAY_SIZE(rt5645_dapm_routes),
3143};
3144
3145static const struct regmap_config rt5645_regmap = {
3146 .reg_bits = 8,
3147 .val_bits = 16,
afefc128 3148 .use_single_rw = true,
1319b2f6
OC		 3149 .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) *
3150 RT5645_PR_SPACING),
3151 .volatile_reg = rt5645_volatile_register,
3152 .readable_reg = rt5645_readable_register,
3153
3154 .cache_type = REGCACHE_RBTREE,
3155 .reg_defaults = rt5645_reg,
3156 .num_reg_defaults = ARRAY_SIZE(rt5645_reg),
3157 .ranges = rt5645_ranges,
3158 .num_ranges = ARRAY_SIZE(rt5645_ranges),
3159};
3160
3161static const struct i2c_device_id rt5645_i2c_id[] = {
3162 { "rt5645", 0 },
5c4ca99d 3163 { "rt5650", 0 },
1319b2f6
OC		 3164 { }
3165};
3166MODULE_DEVICE_TABLE(i2c, rt5645_i2c_id);
3167
3168c201
FY		 3168#ifdef CONFIG_ACPI
3169static struct acpi_device_id rt5645_acpi_match[] = {
3170 { "10EC5645", 0 },
3171 { "10EC5650", 0 },
3172 {},
3173};
3174MODULE_DEVICE_TABLE(acpi, rt5645_acpi_match);
3175#endif
3176
78c34fd4
FY		 3177static struct rt5645_platform_data *rt5645_pdata;
3178
3179static struct rt5645_platform_data strago_platform_data = {
ac4fc3ee 3180 .dmic1_data_pin = RT5645_DMIC1_DISABLE,
78c34fd4 3181 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P,
78c34fd4
FY		 3182 .jd_mode = 3,
3183};
3184
3185static int strago_quirk_cb(const struct dmi_system_id *id)
3186{
3187 rt5645_pdata = &strago_platform_data;
3188
3189 return 1;
3190}
3191
0bc7d10c 3192static const struct dmi_system_id dmi_platform_intel_braswell[] = {
78c34fd4
FY		 3193 {
3194 .ident = "Intel Strago",
3195 .callback = strago_quirk_cb,
3196 .matches = {
3197 DMI_MATCH(DMI_PRODUCT_NAME, "Strago"),
3198 },
3199 },
3200 { }
3201};
3202
48edaa4b
OC		 3203static int rt5645_parse_dt(struct rt5645_priv *rt5645, struct device *dev)
3204{
3205 rt5645->pdata.in2_diff = device_property_read_bool(dev,
3206 "realtek,in2-differential");
3207 device_property_read_u32(dev,
3208 "realtek,dmic1-data-pin", &rt5645->pdata.dmic1_data_pin);
3209 device_property_read_u32(dev,
3210 "realtek,dmic2-data-pin", &rt5645->pdata.dmic2_data_pin);
3211 device_property_read_u32(dev,
3212 "realtek,jd-mode", &rt5645->pdata.jd_mode);
3213
3214 return 0;
3215}
3216
1319b2f6
OC		 3217static int rt5645_i2c_probe(struct i2c_client *i2c,
3218 const struct i2c_device_id *id)
3219{
3220 struct rt5645_platform_data *pdata = dev_get_platdata(&i2c->dev);
3221 struct rt5645_priv *rt5645;
9fc114c5 3222 int ret, i;
1319b2f6
OC		 3223 unsigned int val;
3224
3225 rt5645 = devm_kzalloc(&i2c->dev, sizeof(struct rt5645_priv),
3226 GFP_KERNEL);
3227 if (rt5645 == NULL)
3228 return -ENOMEM;
3229
f3fa1bbd 3230 rt5645->i2c = i2c;
1319b2f6
OC		 3231 i2c_set_clientdata(i2c, rt5645);
3232
48edaa4b 3233 if (pdata)
1319b2f6 3234 rt5645->pdata = *pdata;
48edaa4b
OC		 3235 else if (dmi_check_system(dmi_platform_intel_braswell))
3236 rt5645->pdata = *rt5645_pdata;
3237 else
3238 rt5645_parse_dt(rt5645, &i2c->dev);
1319b2f6 3239
25c8888a
AL		 3240 rt5645->gpiod_hp_det = devm_gpiod_get_optional(&i2c->dev, "hp-detect",
3241 GPIOD_IN);
0b0cefc8
OC		 3242
3243 if (IS_ERR(rt5645->gpiod_hp_det)) {
0b0cefc8 3244 dev_err(&i2c->dev, "failed to initialize gpiod\n");
25c8888a 3245 return PTR_ERR(rt5645->gpiod_hp_det);
0b0cefc8
OC		 3246 }
3247
1319b2f6
OC		 3248 rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5645_regmap);
3249 if (IS_ERR(rt5645->regmap)) {
3250 ret = PTR_ERR(rt5645->regmap);
3251 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
3252 ret);
3253 return ret;
3254 }
3255
9fc114c5
KC		 3256 for (i = 0; i < ARRAY_SIZE(rt5645->supplies); i++)
3257 rt5645->supplies[i].supply = rt5645_supply_names[i];
3258
3259 ret = devm_regulator_bulk_get(&i2c->dev,
3260 ARRAY_SIZE(rt5645->supplies),
3261 rt5645->supplies);
3262 if (ret) {
3263 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
3264 return ret;
3265 }
3266
3267 ret = regulator_bulk_enable(ARRAY_SIZE(rt5645->supplies),
3268 rt5645->supplies);
3269 if (ret) {
3270 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
3271 return ret;
3272 }
3273
1319b2f6 3274 regmap_read(rt5645->regmap, RT5645_VENDOR_ID2, &val);
5c4ca99d
BL		 3275
3276 switch (val) {
3277 case RT5645_DEVICE_ID:
3278 rt5645->codec_type = CODEC_TYPE_RT5645;
3279 break;
3280 case RT5650_DEVICE_ID:
3281 rt5645->codec_type = CODEC_TYPE_RT5650;
3282 break;
3283 default:
1319b2f6 3284 dev_err(&i2c->dev,
8f68e80f 3285 "Device with ID register %#x is not rt5645 or rt5650\n",
5c4ca99d 3286 val);
9fc114c5
KC		 3287 ret = -ENODEV;
3288 goto err_enable;
1319b2f6
OC		 3289 }
3290
3291 regmap_write(rt5645->regmap, RT5645_RESET, 0);
3292
3293 ret = regmap_register_patch(rt5645->regmap, init_list,
3294 ARRAY_SIZE(init_list));
3295 if (ret != 0)
3296 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
3297
5c4ca99d
BL		 3298 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
3299 ret = regmap_register_patch(rt5645->regmap, rt5650_init_list,
3300 ARRAY_SIZE(rt5650_init_list));
3301 if (ret != 0)
3302 dev_warn(&i2c->dev, "Apply rt5650 patch failed: %d\n",
3303 ret);
3304 }
3305
1319b2f6
OC		 3306 if (rt5645->pdata.in2_diff)
3307 regmap_update_bits(rt5645->regmap, RT5645_IN2_CTRL,
3308 RT5645_IN_DF2, RT5645_IN_DF2);
3309
ac4fc3ee 3310 if (rt5645->pdata.dmic1_data_pin || rt5645->pdata.dmic2_data_pin) {
1319b2f6
OC		 3311 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3312 RT5645_GP2_PIN_MASK, RT5645_GP2_PIN_DMIC1_SCL);
ac4fc3ee
BL		 3313 }
3314 switch (rt5645->pdata.dmic1_data_pin) {
3315 case RT5645_DMIC_DATA_IN2N:
3316 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3317 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_IN2N);
3318 break;
1319b2f6 3319
ac4fc3ee
BL		 3320 case RT5645_DMIC_DATA_GPIO5:
3321 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3322 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO5);
3323 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3324 RT5645_GP5_PIN_MASK, RT5645_GP5_PIN_DMIC1_SDA);
3325 break;
1319b2f6 3326
ac4fc3ee
BL		 3327 case RT5645_DMIC_DATA_GPIO11:
3328 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3329 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO11);
3330 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3331 RT5645_GP11_PIN_MASK,
3332 RT5645_GP11_PIN_DMIC1_SDA);
3333 break;
1319b2f6 3334
ac4fc3ee
BL		 3335 default:
3336 break;
3337 }
1319b2f6 3338
ac4fc3ee
BL		 3339 switch (rt5645->pdata.dmic2_data_pin) {
3340 case RT5645_DMIC_DATA_IN2P:
3341 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3342 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_IN2P);
3343 break;
1319b2f6 3344
ac4fc3ee
BL		 3345 case RT5645_DMIC_DATA_GPIO6:
3346 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3347 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO6);
3348 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3349 RT5645_GP6_PIN_MASK, RT5645_GP6_PIN_DMIC2_SDA);
3350 break;
1319b2f6 3351
ac4fc3ee
BL		 3352 case RT5645_DMIC_DATA_GPIO10:
3353 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3354 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO10);
3355 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3356 RT5645_GP10_PIN_MASK,
3357 RT5645_GP10_PIN_DMIC2_SDA);
3358 break;
1319b2f6 3359
ac4fc3ee
BL		 3360 case RT5645_DMIC_DATA_GPIO12:
3361 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3362 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO12);
3363 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3364 RT5645_GP12_PIN_MASK,
3365 RT5645_GP12_PIN_DMIC2_SDA);
3366 break;
1319b2f6 3367
ac4fc3ee
BL		 3368 default:
3369 break;
1319b2f6
OC		 3370 }
3371
ac4fc3ee 3372 if (rt5645->pdata.jd_mode) {
bb656add 3373 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
ac4fc3ee
BL		 3374 RT5645_IRQ_CLK_GATE_CTRL,
3375 RT5645_IRQ_CLK_GATE_CTRL);
bb656add 3376 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
ac4fc3ee 3377 RT5645_IRQ_CLK_INT, RT5645_IRQ_CLK_INT);
2d4e2d02
BL		 3378 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
3379 RT5645_IRQ_JD_1_1_EN, RT5645_IRQ_JD_1_1_EN);
3380 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
3381 RT5645_JD_PSV_MODE, RT5645_JD_PSV_MODE);
3382 regmap_update_bits(rt5645->regmap, RT5645_HPO_MIXER,
3383 RT5645_IRQ_PSV_MODE, RT5645_IRQ_PSV_MODE);
3384 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
3385 RT5645_MIC2_OVCD_EN, RT5645_MIC2_OVCD_EN);
3386 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3387 RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ);
3388 switch (rt5645->pdata.jd_mode) {
3389 case 1:
3390 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
3391 RT5645_JD1_MODE_MASK,
3392 RT5645_JD1_MODE_0);
3393 break;
3394 case 2:
3395 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
3396 RT5645_JD1_MODE_MASK,
3397 RT5645_JD1_MODE_1);
3398 break;
3399 case 3:
3400 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
3401 RT5645_JD1_MODE_MASK,
3402 RT5645_JD1_MODE_2);
3403 break;
3404 default:
3405 break;
3406 }
3407 }
3408
7ea3470a
NB		 3409 INIT_DELAYED_WORK(&rt5645->jack_detect_work, rt5645_jack_detect_work);
3410
f3fa1bbd
OC		 3411 if (rt5645->i2c->irq) {
3412 ret = request_threaded_irq(rt5645->i2c->irq, NULL, rt5645_irq,
3413 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
3414 | IRQF_ONESHOT, "rt5645", rt5645);
5168c547 3415 if (ret) {
f3fa1bbd 3416 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
9fc114c5 3417 goto err_enable;
5168c547 3418 }
f3fa1bbd
OC		 3419 }
3420
5168c547
KC		 3421 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5645,
3422 rt5645_dai, ARRAY_SIZE(rt5645_dai));
3423 if (ret)
3424 goto err_irq;
3425
3426 return 0;
3427
3428err_irq:
3429 if (rt5645->i2c->irq)
3430 free_irq(rt5645->i2c->irq, rt5645);
9fc114c5
KC		 3431err_enable:
3432 regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), rt5645->supplies);
5168c547 3433 return ret;
1319b2f6
OC		 3434}
3435
3436static int rt5645_i2c_remove(struct i2c_client *i2c)
3437{
f3fa1bbd
OC		 3438 struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c);
3439
3440 if (i2c->irq)
3441 free_irq(i2c->irq, rt5645);
3442
cd6e82b8
OC		 3443 cancel_delayed_work_sync(&rt5645->jack_detect_work);
3444
1319b2f6 3445 snd_soc_unregister_codec(&i2c->dev);
9fc114c5 3446 regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), rt5645->supplies);
1319b2f6
OC		 3447
3448 return 0;
3449}
3450
9e22f782 3451static struct i2c_driver rt5645_i2c_driver = {
1319b2f6
OC		 3452 .driver = {
3453 .name = "rt5645",
3454 .owner = THIS_MODULE,
3168c201 3455 .acpi_match_table = ACPI_PTR(rt5645_acpi_match),
1319b2f6
OC		 3456 },
3457 .probe = rt5645_i2c_probe,
3458 .remove = rt5645_i2c_remove,
3459 .id_table = rt5645_i2c_id,
3460};
3461module_i2c_driver(rt5645_i2c_driver);
3462
3463MODULE_DESCRIPTION("ASoC RT5645 driver");
3464MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
3465MODULE_LICENSE("GPL v2");
Michael's Linux tree.