]>
Commit | Line | Data |
---|---|---|
310355c1 VB |
1 | /* |
2 | * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor | |
3 | * | |
d6b52039 | 4 | * Author: Vladimir Barinov, <vbarinov@embeddedalley.com> |
310355c1 VB |
5 | * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com> |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/init.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/device.h> | |
5a0e3ad6 | 15 | #include <linux/slab.h> |
310355c1 VB |
16 | #include <linux/delay.h> |
17 | #include <linux/io.h> | |
18 | #include <linux/clk.h> | |
19 | ||
20 | #include <sound/core.h> | |
21 | #include <sound/pcm.h> | |
22 | #include <sound/pcm_params.h> | |
23 | #include <sound/initval.h> | |
24 | #include <sound/soc.h> | |
25 | ||
ff7d04b1 MB |
26 | #include <mach/asp.h> |
27 | ||
310355c1 VB |
28 | #include "davinci-pcm.h" |
29 | ||
a62114cb DB |
30 | |
31 | /* | |
32 | * NOTE: terminology here is confusing. | |
33 | * | |
34 | * - This driver supports the "Audio Serial Port" (ASP), | |
35 | * found on dm6446, dm355, and other DaVinci chips. | |
36 | * | |
37 | * - But it labels it a "Multi-channel Buffered Serial Port" | |
38 | * (McBSP) as on older chips like the dm642 ... which was | |
39 | * backward-compatible, possibly explaining that confusion. | |
40 | * | |
41 | * - OMAP chips have a controller called McBSP, which is | |
42 | * incompatible with the DaVinci flavor of McBSP. | |
43 | * | |
44 | * - Newer DaVinci chips have a controller called McASP, | |
45 | * incompatible with ASP and with either McBSP. | |
46 | * | |
47 | * In short: this uses ASP to implement I2S, not McBSP. | |
48 | * And it won't be the only DaVinci implemention of I2S. | |
49 | */ | |
310355c1 VB |
50 | #define DAVINCI_MCBSP_DRR_REG 0x00 |
51 | #define DAVINCI_MCBSP_DXR_REG 0x04 | |
52 | #define DAVINCI_MCBSP_SPCR_REG 0x08 | |
53 | #define DAVINCI_MCBSP_RCR_REG 0x0c | |
54 | #define DAVINCI_MCBSP_XCR_REG 0x10 | |
55 | #define DAVINCI_MCBSP_SRGR_REG 0x14 | |
56 | #define DAVINCI_MCBSP_PCR_REG 0x24 | |
57 | ||
58 | #define DAVINCI_MCBSP_SPCR_RRST (1 << 0) | |
59 | #define DAVINCI_MCBSP_SPCR_RINTM(v) ((v) << 4) | |
60 | #define DAVINCI_MCBSP_SPCR_XRST (1 << 16) | |
61 | #define DAVINCI_MCBSP_SPCR_XINTM(v) ((v) << 20) | |
62 | #define DAVINCI_MCBSP_SPCR_GRST (1 << 22) | |
63 | #define DAVINCI_MCBSP_SPCR_FRST (1 << 23) | |
64 | #define DAVINCI_MCBSP_SPCR_FREE (1 << 25) | |
65 | ||
66 | #define DAVINCI_MCBSP_RCR_RWDLEN1(v) ((v) << 5) | |
67 | #define DAVINCI_MCBSP_RCR_RFRLEN1(v) ((v) << 8) | |
68 | #define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v) << 16) | |
f5cfa954 | 69 | #define DAVINCI_MCBSP_RCR_RFIG (1 << 18) |
310355c1 VB |
70 | #define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v) << 21) |
71 | ||
72 | #define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v) << 5) | |
73 | #define DAVINCI_MCBSP_XCR_XFRLEN1(v) ((v) << 8) | |
74 | #define DAVINCI_MCBSP_XCR_XDATDLY(v) ((v) << 16) | |
75 | #define DAVINCI_MCBSP_XCR_XFIG (1 << 18) | |
76 | #define DAVINCI_MCBSP_XCR_XWDLEN2(v) ((v) << 21) | |
77 | ||
78 | #define DAVINCI_MCBSP_SRGR_FWID(v) ((v) << 8) | |
79 | #define DAVINCI_MCBSP_SRGR_FPER(v) ((v) << 16) | |
80 | #define DAVINCI_MCBSP_SRGR_FSGM (1 << 28) | |
81 | ||
82 | #define DAVINCI_MCBSP_PCR_CLKRP (1 << 0) | |
83 | #define DAVINCI_MCBSP_PCR_CLKXP (1 << 1) | |
84 | #define DAVINCI_MCBSP_PCR_FSRP (1 << 2) | |
85 | #define DAVINCI_MCBSP_PCR_FSXP (1 << 3) | |
b402dff8 | 86 | #define DAVINCI_MCBSP_PCR_SCLKME (1 << 7) |
310355c1 VB |
87 | #define DAVINCI_MCBSP_PCR_CLKRM (1 << 8) |
88 | #define DAVINCI_MCBSP_PCR_CLKXM (1 << 9) | |
89 | #define DAVINCI_MCBSP_PCR_FSRM (1 << 10) | |
90 | #define DAVINCI_MCBSP_PCR_FSXM (1 << 11) | |
91 | ||
310355c1 VB |
92 | enum { |
93 | DAVINCI_MCBSP_WORD_8 = 0, | |
94 | DAVINCI_MCBSP_WORD_12, | |
95 | DAVINCI_MCBSP_WORD_16, | |
96 | DAVINCI_MCBSP_WORD_20, | |
97 | DAVINCI_MCBSP_WORD_24, | |
98 | DAVINCI_MCBSP_WORD_32, | |
99 | }; | |
100 | ||
0d6c9774 TK |
101 | static const unsigned char data_type[SNDRV_PCM_FORMAT_S32_LE + 1] = { |
102 | [SNDRV_PCM_FORMAT_S8] = 1, | |
103 | [SNDRV_PCM_FORMAT_S16_LE] = 2, | |
104 | [SNDRV_PCM_FORMAT_S32_LE] = 4, | |
105 | }; | |
106 | ||
107 | static const unsigned char asp_word_length[SNDRV_PCM_FORMAT_S32_LE + 1] = { | |
108 | [SNDRV_PCM_FORMAT_S8] = DAVINCI_MCBSP_WORD_8, | |
109 | [SNDRV_PCM_FORMAT_S16_LE] = DAVINCI_MCBSP_WORD_16, | |
110 | [SNDRV_PCM_FORMAT_S32_LE] = DAVINCI_MCBSP_WORD_32, | |
111 | }; | |
112 | ||
113 | static const unsigned char double_fmt[SNDRV_PCM_FORMAT_S32_LE + 1] = { | |
114 | [SNDRV_PCM_FORMAT_S8] = SNDRV_PCM_FORMAT_S16_LE, | |
115 | [SNDRV_PCM_FORMAT_S16_LE] = SNDRV_PCM_FORMAT_S32_LE, | |
116 | }; | |
117 | ||
310355c1 | 118 | struct davinci_mcbsp_dev { |
92e2a6f6 | 119 | struct davinci_pcm_dma_params dma_params[2]; |
310355c1 | 120 | void __iomem *base; |
f5cfa954 TK |
121 | #define MOD_DSP_A 0 |
122 | #define MOD_DSP_B 1 | |
123 | int mode; | |
c392bec7 | 124 | u32 pcr; |
310355c1 | 125 | struct clk *clk; |
0d6c9774 TK |
126 | /* |
127 | * Combining both channels into 1 element will at least double the | |
128 | * amount of time between servicing the dma channel, increase | |
129 | * effiency, and reduce the chance of overrun/underrun. But, | |
130 | * it will result in the left & right channels being swapped. | |
131 | * | |
132 | * If relabeling the left and right channels is not possible, | |
133 | * you may want to let the codec know to swap them back. | |
134 | * | |
135 | * It may allow x10 the amount of time to service dma requests, | |
136 | * if the codec is master and is using an unnecessarily fast bit clock | |
137 | * (ie. tlvaic23b), independent of the sample rate. So, having an | |
138 | * entire frame at once means it can be serviced at the sample rate | |
139 | * instead of the bit clock rate. | |
140 | * | |
141 | * In the now unlikely case that an underrun still | |
142 | * occurs, both the left and right samples will be repeated | |
143 | * so that no pops are heard, and the left and right channels | |
144 | * won't end up being swapped because of the underrun. | |
145 | */ | |
146 | unsigned enable_channel_combine:1; | |
310355c1 VB |
147 | }; |
148 | ||
149 | static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev, | |
150 | int reg, u32 val) | |
151 | { | |
152 | __raw_writel(val, dev->base + reg); | |
153 | } | |
154 | ||
155 | static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg) | |
156 | { | |
157 | return __raw_readl(dev->base + reg); | |
158 | } | |
159 | ||
c392bec7 TK |
160 | static void toggle_clock(struct davinci_mcbsp_dev *dev, int playback) |
161 | { | |
162 | u32 m = playback ? DAVINCI_MCBSP_PCR_CLKXP : DAVINCI_MCBSP_PCR_CLKRP; | |
163 | /* The clock needs to toggle to complete reset. | |
164 | * So, fake it by toggling the clk polarity. | |
165 | */ | |
166 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr ^ m); | |
167 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr); | |
168 | } | |
169 | ||
f9af37cc TK |
170 | static void davinci_mcbsp_start(struct davinci_mcbsp_dev *dev, |
171 | struct snd_pcm_substream *substream) | |
310355c1 VB |
172 | { |
173 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
fb0ef645 | 174 | struct snd_soc_device *socdev = rtd->socdev; |
87689d56 | 175 | struct snd_soc_platform *platform = socdev->card->platform; |
c392bec7 | 176 | int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); |
35cf6358 | 177 | u32 spcr; |
c392bec7 | 178 | u32 mask = playback ? DAVINCI_MCBSP_SPCR_XRST : DAVINCI_MCBSP_SPCR_RRST; |
35cf6358 | 179 | spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
c392bec7 TK |
180 | if (spcr & mask) { |
181 | /* start off disabled */ | |
182 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, | |
183 | spcr & ~mask); | |
184 | toggle_clock(dev, playback); | |
185 | } | |
1bef4499 TK |
186 | if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM | |
187 | DAVINCI_MCBSP_PCR_CLKXM | DAVINCI_MCBSP_PCR_CLKRM)) { | |
188 | /* Start the sample generator */ | |
189 | spcr |= DAVINCI_MCBSP_SPCR_GRST; | |
190 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); | |
191 | } | |
fb0ef645 | 192 | |
1bef4499 | 193 | if (playback) { |
fb0ef645 NM |
194 | /* Stop the DMA to avoid data loss */ |
195 | /* while the transmitter is out of reset to handle XSYNCERR */ | |
196 | if (platform->pcm_ops->trigger) { | |
eba575c3 | 197 | int ret = platform->pcm_ops->trigger(substream, |
fb0ef645 NM |
198 | SNDRV_PCM_TRIGGER_STOP); |
199 | if (ret < 0) | |
200 | printk(KERN_DEBUG "Playback DMA stop failed\n"); | |
201 | } | |
202 | ||
203 | /* Enable the transmitter */ | |
35cf6358 TK |
204 | spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
205 | spcr |= DAVINCI_MCBSP_SPCR_XRST; | |
206 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); | |
fb0ef645 NM |
207 | |
208 | /* wait for any unexpected frame sync error to occur */ | |
209 | udelay(100); | |
210 | ||
211 | /* Disable the transmitter to clear any outstanding XSYNCERR */ | |
35cf6358 TK |
212 | spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
213 | spcr &= ~DAVINCI_MCBSP_SPCR_XRST; | |
214 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); | |
c392bec7 | 215 | toggle_clock(dev, playback); |
fb0ef645 NM |
216 | |
217 | /* Restart the DMA */ | |
218 | if (platform->pcm_ops->trigger) { | |
eba575c3 | 219 | int ret = platform->pcm_ops->trigger(substream, |
fb0ef645 NM |
220 | SNDRV_PCM_TRIGGER_START); |
221 | if (ret < 0) | |
222 | printk(KERN_DEBUG "Playback DMA start failed\n"); | |
223 | } | |
fb0ef645 NM |
224 | } |
225 | ||
1bef4499 | 226 | /* Enable transmitter or receiver */ |
35cf6358 | 227 | spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
1bef4499 TK |
228 | spcr |= mask; |
229 | ||
230 | if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM)) { | |
231 | /* Start frame sync */ | |
232 | spcr |= DAVINCI_MCBSP_SPCR_FRST; | |
233 | } | |
35cf6358 | 234 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); |
310355c1 VB |
235 | } |
236 | ||
f9af37cc | 237 | static void davinci_mcbsp_stop(struct davinci_mcbsp_dev *dev, int playback) |
310355c1 | 238 | { |
35cf6358 | 239 | u32 spcr; |
310355c1 VB |
240 | |
241 | /* Reset transmitter/receiver and sample rate/frame sync generators */ | |
35cf6358 TK |
242 | spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
243 | spcr &= ~(DAVINCI_MCBSP_SPCR_GRST | DAVINCI_MCBSP_SPCR_FRST); | |
c392bec7 | 244 | spcr &= playback ? ~DAVINCI_MCBSP_SPCR_XRST : ~DAVINCI_MCBSP_SPCR_RRST; |
35cf6358 | 245 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); |
c392bec7 | 246 | toggle_clock(dev, playback); |
310355c1 VB |
247 | } |
248 | ||
21903c1c TK |
249 | #define DEFAULT_BITPERSAMPLE 16 |
250 | ||
9cb132d7 | 251 | static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, |
310355c1 VB |
252 | unsigned int fmt) |
253 | { | |
254 | struct davinci_mcbsp_dev *dev = cpu_dai->private_data; | |
21903c1c TK |
255 | unsigned int pcr; |
256 | unsigned int srgr; | |
21903c1c TK |
257 | srgr = DAVINCI_MCBSP_SRGR_FSGM | |
258 | DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) | | |
259 | DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1); | |
310355c1 | 260 | |
f5cfa954 | 261 | /* set master/slave audio interface */ |
310355c1 VB |
262 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
263 | case SND_SOC_DAIFMT_CBS_CFS: | |
21903c1c TK |
264 | /* cpu is master */ |
265 | pcr = DAVINCI_MCBSP_PCR_FSXM | | |
266 | DAVINCI_MCBSP_PCR_FSRM | | |
267 | DAVINCI_MCBSP_PCR_CLKXM | | |
268 | DAVINCI_MCBSP_PCR_CLKRM; | |
310355c1 | 269 | break; |
b402dff8 HV |
270 | case SND_SOC_DAIFMT_CBM_CFS: |
271 | /* McBSP CLKR pin is the input for the Sample Rate Generator. | |
272 | * McBSP FSR and FSX are driven by the Sample Rate Generator. */ | |
21903c1c TK |
273 | pcr = DAVINCI_MCBSP_PCR_SCLKME | |
274 | DAVINCI_MCBSP_PCR_FSXM | | |
275 | DAVINCI_MCBSP_PCR_FSRM; | |
b402dff8 | 276 | break; |
310355c1 | 277 | case SND_SOC_DAIFMT_CBM_CFM: |
21903c1c TK |
278 | /* codec is master */ |
279 | pcr = 0; | |
310355c1 VB |
280 | break; |
281 | default: | |
21903c1c | 282 | printk(KERN_ERR "%s:bad master\n", __func__); |
310355c1 VB |
283 | return -EINVAL; |
284 | } | |
285 | ||
f5cfa954 | 286 | /* interface format */ |
69ab820c | 287 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
69ab820c | 288 | case SND_SOC_DAIFMT_I2S: |
07d8d9dc TK |
289 | /* Davinci doesn't support TRUE I2S, but some codecs will have |
290 | * the left and right channels contiguous. This allows | |
291 | * dsp_a mode to be used with an inverted normal frame clk. | |
292 | * If your codec is master and does not have contiguous | |
293 | * channels, then you will have sound on only one channel. | |
294 | * Try using a different mode, or codec as slave. | |
295 | * | |
296 | * The TLV320AIC33 is an example of a codec where this works. | |
297 | * It has a variable bit clock frequency allowing it to have | |
298 | * valid data on every bit clock. | |
299 | * | |
300 | * The TLV320AIC23 is an example of a codec where this does not | |
301 | * work. It has a fixed bit clock frequency with progressively | |
302 | * more empty bit clock slots between channels as the sample | |
303 | * rate is lowered. | |
304 | */ | |
305 | fmt ^= SND_SOC_DAIFMT_NB_IF; | |
306 | case SND_SOC_DAIFMT_DSP_A: | |
f5cfa954 TK |
307 | dev->mode = MOD_DSP_A; |
308 | break; | |
309 | case SND_SOC_DAIFMT_DSP_B: | |
310 | dev->mode = MOD_DSP_B; | |
69ab820c TK |
311 | break; |
312 | default: | |
313 | printk(KERN_ERR "%s:bad format\n", __func__); | |
314 | return -EINVAL; | |
315 | } | |
316 | ||
310355c1 | 317 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
9e031624 | 318 | case SND_SOC_DAIFMT_NB_NF: |
664b4af8 TK |
319 | /* CLKRP Receive clock polarity, |
320 | * 1 - sampled on rising edge of CLKR | |
321 | * valid on rising edge | |
322 | * CLKXP Transmit clock polarity, | |
323 | * 1 - clocked on falling edge of CLKX | |
324 | * valid on rising edge | |
325 | * FSRP Receive frame sync pol, 0 - active high | |
326 | * FSXP Transmit frame sync pol, 0 - active high | |
327 | */ | |
21903c1c | 328 | pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP); |
310355c1 | 329 | break; |
9e031624 | 330 | case SND_SOC_DAIFMT_IB_IF: |
664b4af8 TK |
331 | /* CLKRP Receive clock polarity, |
332 | * 0 - sampled on falling edge of CLKR | |
333 | * valid on falling edge | |
334 | * CLKXP Transmit clock polarity, | |
335 | * 0 - clocked on rising edge of CLKX | |
336 | * valid on falling edge | |
337 | * FSRP Receive frame sync pol, 1 - active low | |
338 | * FSXP Transmit frame sync pol, 1 - active low | |
339 | */ | |
21903c1c | 340 | pcr |= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP); |
310355c1 | 341 | break; |
9e031624 | 342 | case SND_SOC_DAIFMT_NB_IF: |
664b4af8 TK |
343 | /* CLKRP Receive clock polarity, |
344 | * 1 - sampled on rising edge of CLKR | |
345 | * valid on rising edge | |
346 | * CLKXP Transmit clock polarity, | |
347 | * 1 - clocked on falling edge of CLKX | |
348 | * valid on rising edge | |
349 | * FSRP Receive frame sync pol, 1 - active low | |
350 | * FSXP Transmit frame sync pol, 1 - active low | |
351 | */ | |
21903c1c TK |
352 | pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP | |
353 | DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP); | |
310355c1 | 354 | break; |
9e031624 | 355 | case SND_SOC_DAIFMT_IB_NF: |
664b4af8 TK |
356 | /* CLKRP Receive clock polarity, |
357 | * 0 - sampled on falling edge of CLKR | |
358 | * valid on falling edge | |
359 | * CLKXP Transmit clock polarity, | |
360 | * 0 - clocked on rising edge of CLKX | |
361 | * valid on falling edge | |
362 | * FSRP Receive frame sync pol, 0 - active high | |
363 | * FSXP Transmit frame sync pol, 0 - active high | |
364 | */ | |
310355c1 VB |
365 | break; |
366 | default: | |
367 | return -EINVAL; | |
368 | } | |
21903c1c | 369 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr); |
c392bec7 | 370 | dev->pcr = pcr; |
21903c1c | 371 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, pcr); |
310355c1 VB |
372 | return 0; |
373 | } | |
374 | ||
375 | static int davinci_i2s_hw_params(struct snd_pcm_substream *substream, | |
dee89c4d MB |
376 | struct snd_pcm_hw_params *params, |
377 | struct snd_soc_dai *dai) | |
310355c1 | 378 | { |
9bb74150 | 379 | struct davinci_mcbsp_dev *dev = dai->private_data; |
81ac55aa | 380 | struct davinci_pcm_dma_params *dma_params = |
92e2a6f6 | 381 | &dev->dma_params[substream->stream]; |
310355c1 VB |
382 | struct snd_interval *i = NULL; |
383 | int mcbsp_word_length; | |
35cf6358 TK |
384 | unsigned int rcr, xcr, srgr; |
385 | u32 spcr; | |
0d6c9774 TK |
386 | snd_pcm_format_t fmt; |
387 | unsigned element_cnt = 1; | |
310355c1 VB |
388 | |
389 | /* general line settings */ | |
35cf6358 | 390 | spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
cb6e2063 | 391 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { |
35cf6358 TK |
392 | spcr |= DAVINCI_MCBSP_SPCR_RINTM(3) | DAVINCI_MCBSP_SPCR_FREE; |
393 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); | |
cb6e2063 | 394 | } else { |
35cf6358 TK |
395 | spcr |= DAVINCI_MCBSP_SPCR_XINTM(3) | DAVINCI_MCBSP_SPCR_FREE; |
396 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); | |
cb6e2063 | 397 | } |
310355c1 VB |
398 | |
399 | i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS); | |
35cf6358 TK |
400 | srgr = DAVINCI_MCBSP_SRGR_FSGM; |
401 | srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1); | |
310355c1 VB |
402 | |
403 | i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS); | |
35cf6358 TK |
404 | srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1); |
405 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr); | |
310355c1 | 406 | |
f5cfa954 TK |
407 | rcr = DAVINCI_MCBSP_RCR_RFIG; |
408 | xcr = DAVINCI_MCBSP_XCR_XFIG; | |
409 | if (dev->mode == MOD_DSP_B) { | |
410 | rcr |= DAVINCI_MCBSP_RCR_RDATDLY(0); | |
411 | xcr |= DAVINCI_MCBSP_XCR_XDATDLY(0); | |
412 | } else { | |
413 | rcr |= DAVINCI_MCBSP_RCR_RDATDLY(1); | |
414 | xcr |= DAVINCI_MCBSP_XCR_XDATDLY(1); | |
415 | } | |
310355c1 | 416 | /* Determine xfer data type */ |
0d6c9774 TK |
417 | fmt = params_format(params); |
418 | if ((fmt > SNDRV_PCM_FORMAT_S32_LE) || !data_type[fmt]) { | |
9b6e12e4 | 419 | printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n"); |
310355c1 VB |
420 | return -EINVAL; |
421 | } | |
422 | ||
0d6c9774 TK |
423 | if (params_channels(params) == 2) { |
424 | element_cnt = 2; | |
425 | if (double_fmt[fmt] && dev->enable_channel_combine) { | |
426 | element_cnt = 1; | |
427 | fmt = double_fmt[fmt]; | |
428 | } | |
429 | } | |
430 | dma_params->acnt = dma_params->data_type = data_type[fmt]; | |
4fa9c1a5 | 431 | dma_params->fifo_level = 0; |
0d6c9774 TK |
432 | mcbsp_word_length = asp_word_length[fmt]; |
433 | rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(element_cnt - 1); | |
434 | xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(element_cnt - 1); | |
310355c1 | 435 | |
f5cfa954 TK |
436 | rcr |= DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) | |
437 | DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length); | |
438 | xcr |= DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) | | |
439 | DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length); | |
310355c1 | 440 | |
f5cfa954 TK |
441 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
442 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr); | |
443 | else | |
444 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr); | |
310355c1 VB |
445 | return 0; |
446 | } | |
447 | ||
af0adf3e TK |
448 | static int davinci_i2s_prepare(struct snd_pcm_substream *substream, |
449 | struct snd_soc_dai *dai) | |
450 | { | |
9bb74150 | 451 | struct davinci_mcbsp_dev *dev = dai->private_data; |
af0adf3e TK |
452 | int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); |
453 | davinci_mcbsp_stop(dev, playback); | |
454 | if ((dev->pcr & DAVINCI_MCBSP_PCR_FSXM) == 0) { | |
455 | /* codec is master */ | |
456 | davinci_mcbsp_start(dev, substream); | |
457 | } | |
458 | return 0; | |
459 | } | |
460 | ||
dee89c4d MB |
461 | static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd, |
462 | struct snd_soc_dai *dai) | |
310355c1 | 463 | { |
9bb74150 | 464 | struct davinci_mcbsp_dev *dev = dai->private_data; |
310355c1 | 465 | int ret = 0; |
f9af37cc | 466 | int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); |
af0adf3e TK |
467 | if ((dev->pcr & DAVINCI_MCBSP_PCR_FSXM) == 0) |
468 | return 0; /* return if codec is master */ | |
310355c1 VB |
469 | |
470 | switch (cmd) { | |
471 | case SNDRV_PCM_TRIGGER_START: | |
472 | case SNDRV_PCM_TRIGGER_RESUME: | |
473 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
f9af37cc | 474 | davinci_mcbsp_start(dev, substream); |
310355c1 VB |
475 | break; |
476 | case SNDRV_PCM_TRIGGER_STOP: | |
477 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
478 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
f9af37cc | 479 | davinci_mcbsp_stop(dev, playback); |
310355c1 VB |
480 | break; |
481 | default: | |
482 | ret = -EINVAL; | |
483 | } | |
310355c1 VB |
484 | return ret; |
485 | } | |
486 | ||
af0adf3e TK |
487 | static void davinci_i2s_shutdown(struct snd_pcm_substream *substream, |
488 | struct snd_soc_dai *dai) | |
489 | { | |
9bb74150 | 490 | struct davinci_mcbsp_dev *dev = dai->private_data; |
af0adf3e TK |
491 | int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); |
492 | davinci_mcbsp_stop(dev, playback); | |
493 | } | |
494 | ||
5204d496 C |
495 | #define DAVINCI_I2S_RATES SNDRV_PCM_RATE_8000_96000 |
496 | ||
497 | static struct snd_soc_dai_ops davinci_i2s_dai_ops = { | |
3f405b46 MB |
498 | .shutdown = davinci_i2s_shutdown, |
499 | .prepare = davinci_i2s_prepare, | |
5204d496 C |
500 | .trigger = davinci_i2s_trigger, |
501 | .hw_params = davinci_i2s_hw_params, | |
502 | .set_fmt = davinci_i2s_set_dai_fmt, | |
503 | ||
504 | }; | |
505 | ||
506 | struct snd_soc_dai davinci_i2s_dai = { | |
507 | .name = "davinci-i2s", | |
508 | .id = 0, | |
509 | .playback = { | |
510 | .channels_min = 2, | |
511 | .channels_max = 2, | |
512 | .rates = DAVINCI_I2S_RATES, | |
513 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
514 | .capture = { | |
515 | .channels_min = 2, | |
516 | .channels_max = 2, | |
517 | .rates = DAVINCI_I2S_RATES, | |
518 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
519 | .ops = &davinci_i2s_dai_ops, | |
520 | ||
521 | }; | |
522 | EXPORT_SYMBOL_GPL(davinci_i2s_dai); | |
523 | ||
524 | static int davinci_i2s_probe(struct platform_device *pdev) | |
310355c1 | 525 | { |
5204d496 | 526 | struct snd_platform_data *pdata = pdev->dev.platform_data; |
310355c1 | 527 | struct davinci_mcbsp_dev *dev; |
5204d496 | 528 | struct resource *mem, *ioarea, *res; |
310355c1 VB |
529 | int ret; |
530 | ||
531 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
532 | if (!mem) { | |
533 | dev_err(&pdev->dev, "no mem resource?\n"); | |
534 | return -ENODEV; | |
535 | } | |
536 | ||
537 | ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1, | |
538 | pdev->name); | |
539 | if (!ioarea) { | |
540 | dev_err(&pdev->dev, "McBSP region already claimed\n"); | |
541 | return -EBUSY; | |
542 | } | |
543 | ||
544 | dev = kzalloc(sizeof(struct davinci_mcbsp_dev), GFP_KERNEL); | |
545 | if (!dev) { | |
546 | ret = -ENOMEM; | |
547 | goto err_release_region; | |
548 | } | |
1e224f32 | 549 | if (pdata) { |
0d6c9774 | 550 | dev->enable_channel_combine = pdata->enable_channel_combine; |
1e224f32 TK |
551 | dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].sram_size = |
552 | pdata->sram_size_playback; | |
553 | dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].sram_size = | |
554 | pdata->sram_size_capture; | |
555 | } | |
3e46a447 | 556 | dev->clk = clk_get(&pdev->dev, NULL); |
310355c1 VB |
557 | if (IS_ERR(dev->clk)) { |
558 | ret = -ENODEV; | |
559 | goto err_free_mem; | |
560 | } | |
561 | clk_enable(dev->clk); | |
562 | ||
563 | dev->base = (void __iomem *)IO_ADDRESS(mem->start); | |
310355c1 | 564 | |
92e2a6f6 | 565 | dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].dma_addr = |
310355c1 VB |
566 | (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DXR_REG); |
567 | ||
92e2a6f6 | 568 | dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].dma_addr = |
310355c1 VB |
569 | (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DRR_REG); |
570 | ||
5204d496 C |
571 | /* first TX, then RX */ |
572 | res = platform_get_resource(pdev, IORESOURCE_DMA, 0); | |
573 | if (!res) { | |
574 | dev_err(&pdev->dev, "no DMA resource\n"); | |
efd13be0 | 575 | ret = -ENXIO; |
5204d496 C |
576 | goto err_free_mem; |
577 | } | |
92e2a6f6 | 578 | dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].channel = res->start; |
5204d496 C |
579 | |
580 | res = platform_get_resource(pdev, IORESOURCE_DMA, 1); | |
581 | if (!res) { | |
582 | dev_err(&pdev->dev, "no DMA resource\n"); | |
efd13be0 | 583 | ret = -ENXIO; |
5204d496 C |
584 | goto err_free_mem; |
585 | } | |
92e2a6f6 | 586 | dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].channel = res->start; |
5204d496 C |
587 | |
588 | davinci_i2s_dai.private_data = dev; | |
57512c64 | 589 | davinci_i2s_dai.dma_data = dev->dma_params; |
5204d496 C |
590 | ret = snd_soc_register_dai(&davinci_i2s_dai); |
591 | if (ret != 0) | |
592 | goto err_free_mem; | |
593 | ||
310355c1 VB |
594 | return 0; |
595 | ||
596 | err_free_mem: | |
597 | kfree(dev); | |
598 | err_release_region: | |
599 | release_mem_region(mem->start, (mem->end - mem->start) + 1); | |
600 | ||
601 | return ret; | |
602 | } | |
603 | ||
5204d496 | 604 | static int davinci_i2s_remove(struct platform_device *pdev) |
310355c1 | 605 | { |
5204d496 | 606 | struct davinci_mcbsp_dev *dev = davinci_i2s_dai.private_data; |
310355c1 VB |
607 | struct resource *mem; |
608 | ||
5204d496 | 609 | snd_soc_unregister_dai(&davinci_i2s_dai); |
310355c1 VB |
610 | clk_disable(dev->clk); |
611 | clk_put(dev->clk); | |
612 | dev->clk = NULL; | |
310355c1 | 613 | kfree(dev); |
310355c1 VB |
614 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
615 | release_mem_region(mem->start, (mem->end - mem->start) + 1); | |
310355c1 | 616 | |
5204d496 C |
617 | return 0; |
618 | } | |
6335d055 | 619 | |
5204d496 C |
620 | static struct platform_driver davinci_mcbsp_driver = { |
621 | .probe = davinci_i2s_probe, | |
622 | .remove = davinci_i2s_remove, | |
623 | .driver = { | |
624 | .name = "davinci-asp", | |
625 | .owner = THIS_MODULE, | |
626 | }, | |
310355c1 | 627 | }; |
310355c1 | 628 | |
c9b3a40f | 629 | static int __init davinci_i2s_init(void) |
3f4b783c | 630 | { |
5204d496 | 631 | return platform_driver_register(&davinci_mcbsp_driver); |
3f4b783c MB |
632 | } |
633 | module_init(davinci_i2s_init); | |
634 | ||
635 | static void __exit davinci_i2s_exit(void) | |
636 | { | |
5204d496 | 637 | platform_driver_unregister(&davinci_mcbsp_driver); |
3f4b783c MB |
638 | } |
639 | module_exit(davinci_i2s_exit); | |
640 | ||
310355c1 VB |
641 | MODULE_AUTHOR("Vladimir Barinov"); |
642 | MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface"); | |
643 | MODULE_LICENSE("GPL"); |