[thirdparty/linux.git] / sound / soc / intel / skylake / skl.h

/*
 *  skl.h - HD Audio skylake defintions.
 *
 *  Copyright (C) 2015 Intel Corp
 *  Author: Jeeja KP <jeeja.kp@intel.com>
 *  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; version 2 of the License.
 *
 *  This program is distributed in the hope that it will be useful, but
 *  WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 *  General Public License for more details.
 *
 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 *
 */

#ifndef __SOUND_SOC_SKL_H
#define __SOUND_SOC_SKL_H

#include <sound/hda_register.h>
#include <sound/hdaudio_ext.h>
#include "skl-nhlt.h"

#define SKL_SUSPEND_DELAY 2000

/* Vendor Specific Registers */
#define AZX_REG_VS_EM1			0x1000
#define AZX_REG_VS_INRC			0x1004
#define AZX_REG_VS_OUTRC		0x1008
#define AZX_REG_VS_FIFOTRK		0x100C
#define AZX_REG_VS_FIFOTRK2		0x1010
#define AZX_REG_VS_EM2			0x1030
#define AZX_REG_VS_EM3L			0x1038
#define AZX_REG_VS_EM3U			0x103C
#define AZX_REG_VS_EM4L			0x1040
#define AZX_REG_VS_EM4U			0x1044
#define AZX_REG_VS_LTRC			0x1048
#define AZX_REG_VS_D0I3C		0x104A
#define AZX_REG_VS_PCE			0x104B
#define AZX_REG_VS_L2MAGC		0x1050
#define AZX_REG_VS_L2LAHPT		0x1054
#define AZX_REG_VS_SDXDPIB_XBASE	0x1084
#define AZX_REG_VS_SDXDPIB_XINTERVAL	0x20
#define AZX_REG_VS_SDXEFIFOS_XBASE	0x1094
#define AZX_REG_VS_SDXEFIFOS_XINTERVAL	0x20

#define AZX_PCIREG_PGCTL		0x44
#define AZX_PGCTL_LSRMD_MASK		(1 << 4)
#define AZX_PCIREG_CGCTL		0x48
#define AZX_CGCTL_MISCBDCGE_MASK	(1 << 6)
/* D0I3C Register fields */
#define AZX_REG_VS_D0I3C_CIP      0x1 /* Command in progress */
#define AZX_REG_VS_D0I3C_I3       0x4 /* D0i3 enable */

struct skl_dsp_resource {
	u32 max_mcps;
	u32 max_mem;
	u32 mcps;
	u32 mem;
};

struct skl {
	struct hdac_ext_bus ebus;
	struct pci_dev *pci;

	unsigned int init_failed:1; /* delayed init failed */
	struct platform_device *dmic_dev;
	struct platform_device *i2s_dev;
	struct snd_soc_platform *platform;

	struct nhlt_acpi_table *nhlt; /* nhlt ptr */
	struct skl_sst *skl_sst; /* sst skl ctx */

	struct skl_dsp_resource resource;
	struct list_head ppl_list;
	struct list_head bind_list;

	const char *fw_name;
	char tplg_name[64];
	unsigned short pci_id;
	const struct firmware *tplg;

	int supend_active;
};

#define skl_to_ebus(s)	(&(s)->ebus)
#define ebus_to_skl(sbus) \
	container_of(sbus, struct skl, sbus)

/* to pass dai dma data */
struct skl_dma_params {
	u32 format;
	u8 stream_tag;
};

/* to pass dmic data */
struct skl_machine_pdata {
	u32 dmic_num;
};

struct skl_dsp_ops {
	int id;
	struct skl_dsp_loader_ops (*loader_ops)(void);
	int (*init)(struct device *dev, void __iomem *mmio_base,
			int irq, const char *fw_name,
			struct skl_dsp_loader_ops loader_ops,
			struct skl_sst **skl_sst);
	int (*init_fw)(struct device *dev, struct skl_sst *ctx);
	void (*cleanup)(struct device *dev, struct skl_sst *ctx);
};

int skl_platform_unregister(struct device *dev);
int skl_platform_register(struct device *dev);

struct nhlt_acpi_table *skl_nhlt_init(struct device *dev);
void skl_nhlt_free(struct nhlt_acpi_table *addr);
struct nhlt_specific_cfg *skl_get_ep_blob(struct skl *skl, u32 instance,
					u8 link_type, u8 s_fmt, u8 no_ch,
					u32 s_rate, u8 dirn, u8 dev_type);

int skl_get_dmic_geo(struct skl *skl);
int skl_nhlt_update_topology_bin(struct skl *skl);
int skl_init_dsp(struct skl *skl);
int skl_free_dsp(struct skl *skl);
int skl_suspend_late_dsp(struct skl *skl);
int skl_suspend_dsp(struct skl *skl);
int skl_resume_dsp(struct skl *skl);
void skl_cleanup_resources(struct skl *skl);
const struct skl_dsp_ops *skl_get_dsp_ops(int pci_id);
void skl_update_d0i3c(struct device *dev, bool enable);
int skl_nhlt_create_sysfs(struct skl *skl);
void skl_nhlt_remove_sysfs(struct skl *skl);

#endif /* __SOUND_SOC_SKL_H */
Commit	Line	Data
a40e693c JK	1	/*
	2	* skl.h - HD Audio skylake defintions.
	3	*
	4	* Copyright (C) 2015 Intel Corp
	5	* Author: Jeeja KP <jeeja.kp@intel.com>
	6	* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; version 2 of the License.
	11	*
	12	* This program is distributed in the hope that it will be useful, but
	13	* WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* General Public License for more details.
	16	*
	17	* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
	18	*
	19	*/
	20
	21	#ifndef __SOUND_SOC_SKL_H
	22	#define __SOUND_SOC_SKL_H
	23
	24	#include <sound/hda_register.h>
	25	#include <sound/hdaudio_ext.h>
473eb87a	26	#include "skl-nhlt.h"
a40e693c JK	27
	28	#define SKL_SUSPEND_DELAY 2000
	29
	30	/* Vendor Specific Registers */
	31	#define AZX_REG_VS_EM1 0x1000
	32	#define AZX_REG_VS_INRC 0x1004
	33	#define AZX_REG_VS_OUTRC 0x1008
	34	#define AZX_REG_VS_FIFOTRK 0x100C
	35	#define AZX_REG_VS_FIFOTRK2 0x1010
	36	#define AZX_REG_VS_EM2 0x1030
	37	#define AZX_REG_VS_EM3L 0x1038
	38	#define AZX_REG_VS_EM3U 0x103C
	39	#define AZX_REG_VS_EM4L 0x1040
	40	#define AZX_REG_VS_EM4U 0x1044
	41	#define AZX_REG_VS_LTRC 0x1048
	42	#define AZX_REG_VS_D0I3C 0x104A
	43	#define AZX_REG_VS_PCE 0x104B
	44	#define AZX_REG_VS_L2MAGC 0x1050
	45	#define AZX_REG_VS_L2LAHPT 0x1054
	46	#define AZX_REG_VS_SDXDPIB_XBASE 0x1084
	47	#define AZX_REG_VS_SDXDPIB_XINTERVAL 0x20
	48	#define AZX_REG_VS_SDXEFIFOS_XBASE 0x1094
	49	#define AZX_REG_VS_SDXEFIFOS_XINTERVAL 0x20
	50
51a01b8c D	51	#define AZX_PCIREG_PGCTL 0x44
51a01b8c D	52	#define AZX_PGCTL_LSRMD_MASK (1 << 4)
0c8ba9d2 J	53	#define AZX_PCIREG_CGCTL 0x48
0c8ba9d2 J	54	#define AZX_CGCTL_MISCBDCGE_MASK (1 << 6)
a26a3f53 PS	55	/* D0I3C Register fields */
	56	#define AZX_REG_VS_D0I3C_CIP 0x1 /* Command in progress */
	57	#define AZX_REG_VS_D0I3C_I3 0x4 /* D0i3 enable */
0c8ba9d2	58
e4e2d2f4 JK	59	struct skl_dsp_resource {
	60	u32 max_mcps;
	61	u32 max_mem;
	62	u32 mcps;
	63	u32 mem;
	64	};
	65
a40e693c JK	66	struct skl {
	67	struct hdac_ext_bus ebus;
	68	struct pci_dev *pci;
	69
	70	unsigned int init_failed:1; /* delayed init failed */
	71	struct platform_device *dmic_dev;
cc18c5fd	72	struct platform_device *i2s_dev;
fe3f4442	73	struct snd_soc_platform *platform;
473eb87a	74
c286b3f9	75	struct nhlt_acpi_table nhlt; / nhlt ptr */
d255b095	76	struct skl_sst skl_sst; / sst skl ctx */
e4e2d2f4 JK	77
	78	struct skl_dsp_resource resource;
	79	struct list_head ppl_list;
b8c722dd	80	struct list_head bind_list;
aecf6fd8 VK	81
aecf6fd8 VK	82	const char *fw_name;
4b235c43 VK	83	char tplg_name[64];
4b235c43 VK	84	unsigned short pci_id;
d8018361	85	const struct firmware *tplg;
4557c305 JK	86
4557c305 JK	87	int supend_active;
a40e693c JK	88	};
	89
	90	#define skl_to_ebus(s) (&(s)->ebus)
	91	#define ebus_to_skl(sbus) \
	92	container_of(sbus, struct skl, sbus)
	93
	94	/* to pass dai dma data */
	95	struct skl_dma_params {
	96	u32 format;
	97	u8 stream_tag;
	98	};
	99
f65cf7d6 YZ	100	/* to pass dmic data */
	101	struct skl_machine_pdata {
	102	u32 dmic_num;
	103	};
	104
bc23ca35 JK	105	struct skl_dsp_ops {
	106	int id;
	107	struct skl_dsp_loader_ops (*loader_ops)(void);
	108	int (init)(struct device dev, void __iomem *mmio_base,
	109	int irq, const char *fw_name,
	110	struct skl_dsp_loader_ops loader_ops,
	111	struct skl_sst **skl_sst);
78cdbbda	112	int (init_fw)(struct device dev, struct skl_sst *ctx);
bc23ca35 JK	113	void (cleanup)(struct device dev, struct skl_sst *ctx);
	114	};
	115
a40e693c JK	116	int skl_platform_unregister(struct device *dev);
	117	int skl_platform_register(struct device *dev);
	118
c286b3f9 JK	119	struct nhlt_acpi_table skl_nhlt_init(struct device dev);
c286b3f9 JK	120	void skl_nhlt_free(struct nhlt_acpi_table *addr);
473eb87a	121	struct nhlt_specific_cfg skl_get_ep_blob(struct skl skl, u32 instance,
db2f586b SV	122	u8 link_type, u8 s_fmt, u8 no_ch,
db2f586b SV	123	u32 s_rate, u8 dirn, u8 dev_type);
d255b095	124
f65cf7d6	125	int skl_get_dmic_geo(struct skl *skl);
4b235c43	126	int skl_nhlt_update_topology_bin(struct skl *skl);
d255b095	127	int skl_init_dsp(struct skl *skl);
bc23ca35	128	int skl_free_dsp(struct skl *skl);
8b4a133c	129	int skl_suspend_late_dsp(struct skl *skl);
d255b095 JK	130	int skl_suspend_dsp(struct skl *skl);
d255b095 JK	131	int skl_resume_dsp(struct skl *skl);
fe3f4442	132	void skl_cleanup_resources(struct skl *skl);
73a67581	133	const struct skl_dsp_ops *skl_get_dsp_ops(int pci_id);
a26a3f53	134	void skl_update_d0i3c(struct device *dev, bool enable);
0cf5a171 SP	135	int skl_nhlt_create_sysfs(struct skl *skl);
0cf5a171 SP	136	void skl_nhlt_remove_sysfs(struct skl *skl);
a26a3f53	137
a40e693c	138	#endif /* __SOUND_SOC_SKL_H */