[thirdparty/linux.git] / sound / soc / samsung / s3c-i2s-v2.c

// SPDX-License-Identifier: GPL-2.0+
//
// ALSA Soc Audio Layer - I2S core for newer Samsung SoCs.
//
// Copyright (c) 2006 Wolfson Microelectronics PLC.
//	Graeme Gregory graeme.gregory@wolfsonmicro.com
//	linux@wolfsonmicro.com
//
// Copyright (c) 2008, 2007, 2004-2005 Simtec Electronics
//	http://armlinux.simtec.co.uk/
//	Ben Dooks <ben@simtec.co.uk>

#include <linux/module.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/io.h>

#include <sound/soc.h>
#include <sound/pcm_params.h>

#include "regs-i2s-v2.h"
#include "s3c-i2s-v2.h"

#undef S3C_IIS_V2_SUPPORTED

#if defined(CONFIG_CPU_S3C2412) \
	|| defined(CONFIG_ARCH_S3C64XX) || defined(CONFIG_CPU_S5PV210)
#define S3C_IIS_V2_SUPPORTED
#endif

#ifndef S3C_IIS_V2_SUPPORTED
#error Unsupported CPU model
#endif

#define S3C2412_I2S_DEBUG_CON 0

static inline struct s3c_i2sv2_info *to_info(struct snd_soc_dai *cpu_dai)
{
	return snd_soc_dai_get_drvdata(cpu_dai);
}

#define bit_set(v, b) (((v) & (b)) ? 1 : 0)

#if S3C2412_I2S_DEBUG_CON
static void dbg_showcon(const char *fn, u32 con)
{
	printk(KERN_DEBUG "%s: LRI=%d, TXFEMPT=%d, RXFEMPT=%d, TXFFULL=%d, RXFFULL=%d\n", fn,
	       bit_set(con, S3C2412_IISCON_LRINDEX),
	       bit_set(con, S3C2412_IISCON_TXFIFO_EMPTY),
	       bit_set(con, S3C2412_IISCON_RXFIFO_EMPTY),
	       bit_set(con, S3C2412_IISCON_TXFIFO_FULL),
	       bit_set(con, S3C2412_IISCON_RXFIFO_FULL));

	printk(KERN_DEBUG "%s: PAUSE: TXDMA=%d, RXDMA=%d, TXCH=%d, RXCH=%d\n",
	       fn,
	       bit_set(con, S3C2412_IISCON_TXDMA_PAUSE),
	       bit_set(con, S3C2412_IISCON_RXDMA_PAUSE),
	       bit_set(con, S3C2412_IISCON_TXCH_PAUSE),
	       bit_set(con, S3C2412_IISCON_RXCH_PAUSE));
	printk(KERN_DEBUG "%s: ACTIVE: TXDMA=%d, RXDMA=%d, IIS=%d\n", fn,
	       bit_set(con, S3C2412_IISCON_TXDMA_ACTIVE),
	       bit_set(con, S3C2412_IISCON_RXDMA_ACTIVE),
	       bit_set(con, S3C2412_IISCON_IIS_ACTIVE));
}
#else
static inline void dbg_showcon(const char *fn, u32 con)
{
}
#endif

/* Turn on or off the transmission path. */
static void s3c2412_snd_txctrl(struct s3c_i2sv2_info *i2s, int on)
{
	void __iomem *regs = i2s->regs;
	u32 fic, con, mod;

	pr_debug("%s(%d)\n", __func__, on);

	fic = readl(regs + S3C2412_IISFIC);
	con = readl(regs + S3C2412_IISCON);
	mod = readl(regs + S3C2412_IISMOD);

	pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);

	if (on) {
		con |= S3C2412_IISCON_TXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE;
		con &= ~S3C2412_IISCON_TXDMA_PAUSE;
		con &= ~S3C2412_IISCON_TXCH_PAUSE;

		switch (mod & S3C2412_IISMOD_MODE_MASK) {
		case S3C2412_IISMOD_MODE_TXONLY:
		case S3C2412_IISMOD_MODE_TXRX:
			/* do nothing, we are in the right mode */
			break;

		case S3C2412_IISMOD_MODE_RXONLY:
			mod &= ~S3C2412_IISMOD_MODE_MASK;
			mod |= S3C2412_IISMOD_MODE_TXRX;
			break;

		default:
			dev_err(i2s->dev, "TXEN: Invalid MODE %x in IISMOD\n",
				mod & S3C2412_IISMOD_MODE_MASK);
			break;
		}

		writel(con, regs + S3C2412_IISCON);
		writel(mod, regs + S3C2412_IISMOD);
	} else {
		/* Note, we do not have any indication that the FIFO problems
		 * tha the S3C2410/2440 had apply here, so we should be able
		 * to disable the DMA and TX without resetting the FIFOS.
		 */

		con |=  S3C2412_IISCON_TXDMA_PAUSE;
		con |=  S3C2412_IISCON_TXCH_PAUSE;
		con &= ~S3C2412_IISCON_TXDMA_ACTIVE;

		switch (mod & S3C2412_IISMOD_MODE_MASK) {
		case S3C2412_IISMOD_MODE_TXRX:
			mod &= ~S3C2412_IISMOD_MODE_MASK;
			mod |= S3C2412_IISMOD_MODE_RXONLY;
			break;

		case S3C2412_IISMOD_MODE_TXONLY:
			mod &= ~S3C2412_IISMOD_MODE_MASK;
			con &= ~S3C2412_IISCON_IIS_ACTIVE;
			break;

		default:
			dev_err(i2s->dev, "TXDIS: Invalid MODE %x in IISMOD\n",
				mod & S3C2412_IISMOD_MODE_MASK);
			break;
		}

		writel(mod, regs + S3C2412_IISMOD);
		writel(con, regs + S3C2412_IISCON);
	}

	fic = readl(regs + S3C2412_IISFIC);
	dbg_showcon(__func__, con);
	pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
}

static void s3c2412_snd_rxctrl(struct s3c_i2sv2_info *i2s, int on)
{
	void __iomem *regs = i2s->regs;
	u32 fic, con, mod;

	pr_debug("%s(%d)\n", __func__, on);

	fic = readl(regs + S3C2412_IISFIC);
	con = readl(regs + S3C2412_IISCON);
	mod = readl(regs + S3C2412_IISMOD);

	pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);

	if (on) {
		con |= S3C2412_IISCON_RXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE;
		con &= ~S3C2412_IISCON_RXDMA_PAUSE;
		con &= ~S3C2412_IISCON_RXCH_PAUSE;

		switch (mod & S3C2412_IISMOD_MODE_MASK) {
		case S3C2412_IISMOD_MODE_TXRX:
		case S3C2412_IISMOD_MODE_RXONLY:
			/* do nothing, we are in the right mode */
			break;

		case S3C2412_IISMOD_MODE_TXONLY:
			mod &= ~S3C2412_IISMOD_MODE_MASK;
			mod |= S3C2412_IISMOD_MODE_TXRX;
			break;

		default:
			dev_err(i2s->dev, "RXEN: Invalid MODE %x in IISMOD\n",
				mod & S3C2412_IISMOD_MODE_MASK);
		}

		writel(mod, regs + S3C2412_IISMOD);
		writel(con, regs + S3C2412_IISCON);
	} else {
		/* See txctrl notes on FIFOs. */

		con &= ~S3C2412_IISCON_RXDMA_ACTIVE;
		con |=  S3C2412_IISCON_RXDMA_PAUSE;
		con |=  S3C2412_IISCON_RXCH_PAUSE;

		switch (mod & S3C2412_IISMOD_MODE_MASK) {
		case S3C2412_IISMOD_MODE_RXONLY:
			con &= ~S3C2412_IISCON_IIS_ACTIVE;
			mod &= ~S3C2412_IISMOD_MODE_MASK;
			break;

		case S3C2412_IISMOD_MODE_TXRX:
			mod &= ~S3C2412_IISMOD_MODE_MASK;
			mod |= S3C2412_IISMOD_MODE_TXONLY;
			break;

		default:
			dev_err(i2s->dev, "RXDIS: Invalid MODE %x in IISMOD\n",
				mod & S3C2412_IISMOD_MODE_MASK);
		}

		writel(con, regs + S3C2412_IISCON);
		writel(mod, regs + S3C2412_IISMOD);
	}

	fic = readl(regs + S3C2412_IISFIC);
	pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
}

#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)

/*
 * Wait for the LR signal to allow synchronisation to the L/R clock
 * from the codec. May only be needed for slave mode.
 */
static int s3c2412_snd_lrsync(struct s3c_i2sv2_info *i2s)
{
	u32 iiscon;
	unsigned long loops = msecs_to_loops(5);

	pr_debug("Entered %s\n", __func__);

	while (--loops) {
		iiscon = readl(i2s->regs + S3C2412_IISCON);
		if (iiscon & S3C2412_IISCON_LRINDEX)
			break;

		cpu_relax();
	}

	if (!loops) {
		printk(KERN_ERR "%s: timeout\n", __func__);
		return -ETIMEDOUT;
	}

	return 0;
}

/*
 * Set S3C2412 I2S DAI format
 */
static int s3c2412_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
			       unsigned int fmt)
{
	struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
	u32 iismod;

	pr_debug("Entered %s\n", __func__);

	iismod = readl(i2s->regs + S3C2412_IISMOD);
	pr_debug("hw_params r: IISMOD: %x \n", iismod);

	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBM_CFM:
		i2s->master = 0;
		iismod |= S3C2412_IISMOD_SLAVE;
		break;
	case SND_SOC_DAIFMT_CBS_CFS:
		i2s->master = 1;
		iismod &= ~S3C2412_IISMOD_SLAVE;
		break;
	default:
		pr_err("unknown master/slave format\n");
		return -EINVAL;
	}

	iismod &= ~S3C2412_IISMOD_SDF_MASK;

	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_RIGHT_J:
		iismod |= S3C2412_IISMOD_LR_RLOW;
		iismod |= S3C2412_IISMOD_SDF_MSB;
		break;
	case SND_SOC_DAIFMT_LEFT_J:
		iismod |= S3C2412_IISMOD_LR_RLOW;
		iismod |= S3C2412_IISMOD_SDF_LSB;
		break;
	case SND_SOC_DAIFMT_I2S:
		iismod &= ~S3C2412_IISMOD_LR_RLOW;
		iismod |= S3C2412_IISMOD_SDF_IIS;
		break;
	default:
		pr_err("Unknown data format\n");
		return -EINVAL;
	}

	writel(iismod, i2s->regs + S3C2412_IISMOD);
	pr_debug("hw_params w: IISMOD: %x \n", iismod);
	return 0;
}

static int s3c_i2sv2_hw_params(struct snd_pcm_substream *substream,
				 struct snd_pcm_hw_params *params,
				 struct snd_soc_dai *dai)
{
	struct s3c_i2sv2_info *i2s = to_info(dai);
	struct snd_dmaengine_dai_dma_data *dma_data;
	u32 iismod;

	pr_debug("Entered %s\n", __func__);

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		dma_data = i2s->dma_playback;
	else
		dma_data = i2s->dma_capture;

	snd_soc_dai_set_dma_data(dai, substream, dma_data);

	/* Working copies of register */
	iismod = readl(i2s->regs + S3C2412_IISMOD);
	pr_debug("%s: r: IISMOD: %x\n", __func__, iismod);

	iismod &= ~S3C64XX_IISMOD_BLC_MASK;
	/* Sample size */
	switch (params_width(params)) {
	case 8:
		iismod |= S3C64XX_IISMOD_BLC_8BIT;
		break;
	case 16:
		break;
	case 24:
		iismod |= S3C64XX_IISMOD_BLC_24BIT;
		break;
	}

	writel(iismod, i2s->regs + S3C2412_IISMOD);
	pr_debug("%s: w: IISMOD: %x\n", __func__, iismod);

	return 0;
}

static int s3c_i2sv2_set_sysclk(struct snd_soc_dai *cpu_dai,
				  int clk_id, unsigned int freq, int dir)
{
	struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
	u32 iismod = readl(i2s->regs + S3C2412_IISMOD);

	pr_debug("Entered %s\n", __func__);
	pr_debug("%s r: IISMOD: %x\n", __func__, iismod);

	switch (clk_id) {
	case S3C_I2SV2_CLKSRC_PCLK:
		iismod &= ~S3C2412_IISMOD_IMS_SYSMUX;
		break;

	case S3C_I2SV2_CLKSRC_AUDIOBUS:
		iismod |= S3C2412_IISMOD_IMS_SYSMUX;
		break;

	case S3C_I2SV2_CLKSRC_CDCLK:
		/* Error if controller doesn't have the CDCLKCON bit */
		if (!(i2s->feature & S3C_FEATURE_CDCLKCON))
			return -EINVAL;

		switch (dir) {
		case SND_SOC_CLOCK_IN:
			iismod |= S3C64XX_IISMOD_CDCLKCON;
			break;
		case SND_SOC_CLOCK_OUT:
			iismod &= ~S3C64XX_IISMOD_CDCLKCON;
			break;
		default:
			return -EINVAL;
		}
		break;

	default:
		return -EINVAL;
	}

	writel(iismod, i2s->regs + S3C2412_IISMOD);
	pr_debug("%s w: IISMOD: %x\n", __func__, iismod);

	return 0;
}

static int s3c2412_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
			       struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct s3c_i2sv2_info *i2s = to_info(asoc_rtd_to_cpu(rtd, 0));
	int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
	unsigned long irqs;
	int ret = 0;

	pr_debug("Entered %s\n", __func__);

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
		/* On start, ensure that the FIFOs are cleared and reset. */

		writel(capture ? S3C2412_IISFIC_RXFLUSH : S3C2412_IISFIC_TXFLUSH,
		       i2s->regs + S3C2412_IISFIC);

		/* clear again, just in case */
		writel(0x0, i2s->regs + S3C2412_IISFIC);

	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		if (!i2s->master) {
			ret = s3c2412_snd_lrsync(i2s);
			if (ret)
				goto exit_err;
		}

		local_irq_save(irqs);

		if (capture)
			s3c2412_snd_rxctrl(i2s, 1);
		else
			s3c2412_snd_txctrl(i2s, 1);

		local_irq_restore(irqs);

		break;

	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		local_irq_save(irqs);

		if (capture)
			s3c2412_snd_rxctrl(i2s, 0);
		else
			s3c2412_snd_txctrl(i2s, 0);

		local_irq_restore(irqs);
		break;
	default:
		ret = -EINVAL;
		break;
	}

exit_err:
	return ret;
}

/*
 * Set S3C2412 Clock dividers
 */
static int s3c2412_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai,
				  int div_id, int div)
{
	struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
	u32 reg;

	pr_debug("%s(%p, %d, %d)\n", __func__, cpu_dai, div_id, div);

	switch (div_id) {
	case S3C_I2SV2_DIV_BCLK:
		switch (div) {
		case 16:
			div = S3C2412_IISMOD_BCLK_16FS;
			break;

		case 32:
			div = S3C2412_IISMOD_BCLK_32FS;
			break;

		case 24:
			div = S3C2412_IISMOD_BCLK_24FS;
			break;

		case 48:
			div = S3C2412_IISMOD_BCLK_48FS;
			break;

		default:
			return -EINVAL;
		}

		reg = readl(i2s->regs + S3C2412_IISMOD);
		reg &= ~S3C2412_IISMOD_BCLK_MASK;
		writel(reg | div, i2s->regs + S3C2412_IISMOD);

		pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
		break;

	case S3C_I2SV2_DIV_RCLK:
		switch (div) {
		case 256:
			div = S3C2412_IISMOD_RCLK_256FS;
			break;

		case 384:
			div = S3C2412_IISMOD_RCLK_384FS;
			break;

		case 512:
			div = S3C2412_IISMOD_RCLK_512FS;
			break;

		case 768:
			div = S3C2412_IISMOD_RCLK_768FS;
			break;

		default:
			return -EINVAL;
		}

		reg = readl(i2s->regs + S3C2412_IISMOD);
		reg &= ~S3C2412_IISMOD_RCLK_MASK;
		writel(reg | div, i2s->regs + S3C2412_IISMOD);
		pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
		break;

	case S3C_I2SV2_DIV_PRESCALER:
		if (div >= 0) {
			writel((div << 8) | S3C2412_IISPSR_PSREN,
			       i2s->regs + S3C2412_IISPSR);
		} else {
			writel(0x0, i2s->regs + S3C2412_IISPSR);
		}
		pr_debug("%s: PSR=%08x\n", __func__, readl(i2s->regs + S3C2412_IISPSR));
		break;

	default:
		return -EINVAL;
	}

	return 0;
}

static snd_pcm_sframes_t s3c2412_i2s_delay(struct snd_pcm_substream *substream,
					   struct snd_soc_dai *dai)
{
	struct s3c_i2sv2_info *i2s = to_info(dai);
	u32 reg = readl(i2s->regs + S3C2412_IISFIC);
	snd_pcm_sframes_t delay;

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		delay = S3C2412_IISFIC_TXCOUNT(reg);
	else
		delay = S3C2412_IISFIC_RXCOUNT(reg);

	return delay;
}

struct clk *s3c_i2sv2_get_clock(struct snd_soc_dai *cpu_dai)
{
	struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
	u32 iismod = readl(i2s->regs + S3C2412_IISMOD);

	if (iismod & S3C2412_IISMOD_IMS_SYSMUX)
		return i2s->iis_cclk;
	else
		return i2s->iis_pclk;
}
EXPORT_SYMBOL_GPL(s3c_i2sv2_get_clock);

/* default table of all avaialable root fs divisors */
static unsigned int iis_fs_tab[] = { 256, 512, 384, 768 };

int s3c_i2sv2_iis_calc_rate(struct s3c_i2sv2_rate_calc *info,
			    unsigned int *fstab,
			    unsigned int rate, struct clk *clk)
{
	unsigned long clkrate = clk_get_rate(clk);
	unsigned int div;
	unsigned int fsclk;
	unsigned int actual;
	unsigned int fs;
	unsigned int fsdiv;
	signed int deviation = 0;
	unsigned int best_fs = 0;
	unsigned int best_div = 0;
	unsigned int best_rate = 0;
	unsigned int best_deviation = INT_MAX;

	pr_debug("Input clock rate %ldHz\n", clkrate);

	if (fstab == NULL)
		fstab = iis_fs_tab;

	for (fs = 0; fs < ARRAY_SIZE(iis_fs_tab); fs++) {
		fsdiv = iis_fs_tab[fs];

		fsclk = clkrate / fsdiv;
		div = fsclk / rate;

		if ((fsclk % rate) > (rate / 2))
			div++;

		if (div <= 1)
			continue;

		actual = clkrate / (fsdiv * div);
		deviation = actual - rate;

		printk(KERN_DEBUG "%ufs: div %u => result %u, deviation %d\n",
		       fsdiv, div, actual, deviation);

		deviation = abs(deviation);

		if (deviation < best_deviation) {
			best_fs = fsdiv;
			best_div = div;
			best_rate = actual;
			best_deviation = deviation;
		}

		if (deviation == 0)
			break;
	}

	printk(KERN_DEBUG "best: fs=%u, div=%u, rate=%u\n",
	       best_fs, best_div, best_rate);

	info->fs_div = best_fs;
	info->clk_div = best_div;

	return 0;
}
EXPORT_SYMBOL_GPL(s3c_i2sv2_iis_calc_rate);

int s3c_i2sv2_probe(struct snd_soc_dai *dai,
		    struct s3c_i2sv2_info *i2s,
		    unsigned long base)
{
	struct device *dev = dai->dev;
	unsigned int iismod;

	i2s->dev = dev;

	/* record our i2s structure for later use in the callbacks */
	snd_soc_dai_set_drvdata(dai, i2s);

	i2s->iis_pclk = clk_get(dev, "iis");
	if (IS_ERR(i2s->iis_pclk)) {
		dev_err(dev, "failed to get iis_clock\n");
		return -ENOENT;
	}

	clk_prepare_enable(i2s->iis_pclk);

	/* Mark ourselves as in TXRX mode so we can run through our cleanup
	 * process without warnings. */
	iismod = readl(i2s->regs + S3C2412_IISMOD);
	iismod |= S3C2412_IISMOD_MODE_TXRX;
	writel(iismod, i2s->regs + S3C2412_IISMOD);
	s3c2412_snd_txctrl(i2s, 0);
	s3c2412_snd_rxctrl(i2s, 0);

	return 0;
}
EXPORT_SYMBOL_GPL(s3c_i2sv2_probe);

void s3c_i2sv2_cleanup(struct snd_soc_dai *dai,
		      struct s3c_i2sv2_info *i2s)
{
	clk_disable_unprepare(i2s->iis_pclk);
	clk_put(i2s->iis_pclk);
	i2s->iis_pclk = NULL;
}
EXPORT_SYMBOL_GPL(s3c_i2sv2_cleanup);

int s3c_i2sv2_register_component(struct device *dev, int id,
			   const struct snd_soc_component_driver *cmp_drv,
			   struct snd_soc_dai_driver *dai_drv)
{
	struct snd_soc_dai_ops *ops = (struct snd_soc_dai_ops *)dai_drv->ops;

	ops->trigger = s3c2412_i2s_trigger;
	if (!ops->hw_params)
		ops->hw_params = s3c_i2sv2_hw_params;
	ops->set_fmt = s3c2412_i2s_set_fmt;
	ops->set_clkdiv = s3c2412_i2s_set_clkdiv;
	ops->set_sysclk = s3c_i2sv2_set_sysclk;

	/* Allow overriding by (for example) IISv4 */
	if (!ops->delay)
		ops->delay = s3c2412_i2s_delay;

	return devm_snd_soc_register_component(dev, cmp_drv, dai_drv, 1);
}
EXPORT_SYMBOL_GPL(s3c_i2sv2_register_component);

MODULE_LICENSE("GPL");
Commit	Line	Data
08ac76d0 SN	1	// SPDX-License-Identifier: GPL-2.0+
	2	//
	3	// ALSA Soc Audio Layer - I2S core for newer Samsung SoCs.
	4	//
	5	// Copyright (c) 2006 Wolfson Microelectronics PLC.
	6	// Graeme Gregory graeme.gregory@wolfsonmicro.com
	7	// linux@wolfsonmicro.com
	8	//
	9	// Copyright (c) 2008, 2007, 2004-2005 Simtec Electronics
	10	// http://armlinux.simtec.co.uk/
	11	// Ben Dooks <ben@simtec.co.uk>
dc85447b	12
f3a54a28	13	#include <linux/module.h>
dc85447b BD	14	#include <linux/delay.h>
dc85447b BD	15	#include <linux/clk.h>
dc85447b BD	16	#include <linux/io.h>
dc85447b BD	17
dc85447b	18	#include <sound/soc.h>
0378b6ac	19	#include <sound/pcm_params.h>
dc85447b	20
d07e7ce9	21	#include "regs-i2s-v2.h"
dc85447b BD	22	#include "s3c-i2s-v2.h"
dc85447b BD	23
8a0f62b8 MB	24	#undef S3C_IIS_V2_SUPPORTED
8a0f62b8 MB	25
2d397c51	26	#if defined(CONFIG_CPU_S3C2412) \
7472a2f2	27	\|\| defined(CONFIG_ARCH_S3C64XX) \|\| defined(CONFIG_CPU_S5PV210)
8a0f62b8 MB	28	#define S3C_IIS_V2_SUPPORTED
	29	#endif
	30
	31	#ifndef S3C_IIS_V2_SUPPORTED
	32	#error Unsupported CPU model
	33	#endif
	34
dc85447b	35	#define S3C2412_I2S_DEBUG_CON 0
dc85447b BD	36
	37	static inline struct s3c_i2sv2_info to_info(struct snd_soc_dai cpu_dai)
	38	{
f0fba2ad	39	return snd_soc_dai_get_drvdata(cpu_dai);
dc85447b BD	40	}
	41
	42	#define bit_set(v, b) (((v) & (b)) ? 1 : 0)
	43
	44	#if S3C2412_I2S_DEBUG_CON
	45	static void dbg_showcon(const char *fn, u32 con)
	46	{
	47	printk(KERN_DEBUG "%s: LRI=%d, TXFEMPT=%d, RXFEMPT=%d, TXFFULL=%d, RXFFULL=%d\n", fn,
	48	bit_set(con, S3C2412_IISCON_LRINDEX),
	49	bit_set(con, S3C2412_IISCON_TXFIFO_EMPTY),
	50	bit_set(con, S3C2412_IISCON_RXFIFO_EMPTY),
	51	bit_set(con, S3C2412_IISCON_TXFIFO_FULL),
	52	bit_set(con, S3C2412_IISCON_RXFIFO_FULL));
	53
	54	printk(KERN_DEBUG "%s: PAUSE: TXDMA=%d, RXDMA=%d, TXCH=%d, RXCH=%d\n",
	55	fn,
	56	bit_set(con, S3C2412_IISCON_TXDMA_PAUSE),
	57	bit_set(con, S3C2412_IISCON_RXDMA_PAUSE),
	58	bit_set(con, S3C2412_IISCON_TXCH_PAUSE),
	59	bit_set(con, S3C2412_IISCON_RXCH_PAUSE));
	60	printk(KERN_DEBUG "%s: ACTIVE: TXDMA=%d, RXDMA=%d, IIS=%d\n", fn,
	61	bit_set(con, S3C2412_IISCON_TXDMA_ACTIVE),
	62	bit_set(con, S3C2412_IISCON_RXDMA_ACTIVE),
	63	bit_set(con, S3C2412_IISCON_IIS_ACTIVE));
	64	}
	65	#else
	66	static inline void dbg_showcon(const char *fn, u32 con)
	67	{
	68	}
	69	#endif
	70
dc85447b	71	/* Turn on or off the transmission path. */
abbc8246	72	static void s3c2412_snd_txctrl(struct s3c_i2sv2_info *i2s, int on)
dc85447b BD	73	{
	74	void __iomem *regs = i2s->regs;
	75	u32 fic, con, mod;
	76
ee7d4767	77	pr_debug("%s(%d)\n", __func__, on);
dc85447b BD	78
	79	fic = readl(regs + S3C2412_IISFIC);
	80	con = readl(regs + S3C2412_IISCON);
	81	mod = readl(regs + S3C2412_IISMOD);
	82
ee7d4767	83	pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b BD	84
	85	if (on) {
	86	con \|= S3C2412_IISCON_TXDMA_ACTIVE \| S3C2412_IISCON_IIS_ACTIVE;
	87	con &= ~S3C2412_IISCON_TXDMA_PAUSE;
	88	con &= ~S3C2412_IISCON_TXCH_PAUSE;
	89
	90	switch (mod & S3C2412_IISMOD_MODE_MASK) {
	91	case S3C2412_IISMOD_MODE_TXONLY:
	92	case S3C2412_IISMOD_MODE_TXRX:
	93	/* do nothing, we are in the right mode */
	94	break;
	95
	96	case S3C2412_IISMOD_MODE_RXONLY:
	97	mod &= ~S3C2412_IISMOD_MODE_MASK;
	98	mod \|= S3C2412_IISMOD_MODE_TXRX;
	99	break;
	100
	101	default:
abbc8246 MB	102	dev_err(i2s->dev, "TXEN: Invalid MODE %x in IISMOD\n",
	103	mod & S3C2412_IISMOD_MODE_MASK);
	104	break;
dc85447b BD	105	}
	106
	107	writel(con, regs + S3C2412_IISCON);
	108	writel(mod, regs + S3C2412_IISMOD);
	109	} else {
	110	/* Note, we do not have any indication that the FIFO problems
	111	* tha the S3C2410/2440 had apply here, so we should be able
	112	* to disable the DMA and TX without resetting the FIFOS.
	113	*/
	114
	115	con \|= S3C2412_IISCON_TXDMA_PAUSE;
	116	con \|= S3C2412_IISCON_TXCH_PAUSE;
	117	con &= ~S3C2412_IISCON_TXDMA_ACTIVE;
	118
	119	switch (mod & S3C2412_IISMOD_MODE_MASK) {
	120	case S3C2412_IISMOD_MODE_TXRX:
	121	mod &= ~S3C2412_IISMOD_MODE_MASK;
	122	mod \|= S3C2412_IISMOD_MODE_RXONLY;
	123	break;
	124
	125	case S3C2412_IISMOD_MODE_TXONLY:
	126	mod &= ~S3C2412_IISMOD_MODE_MASK;
	127	con &= ~S3C2412_IISCON_IIS_ACTIVE;
	128	break;
	129
	130	default:
abbc8246 MB	131	dev_err(i2s->dev, "TXDIS: Invalid MODE %x in IISMOD\n",
	132	mod & S3C2412_IISMOD_MODE_MASK);
	133	break;
dc85447b BD	134	}
	135
	136	writel(mod, regs + S3C2412_IISMOD);
	137	writel(con, regs + S3C2412_IISCON);
	138	}
	139
	140	fic = readl(regs + S3C2412_IISFIC);
	141	dbg_showcon(__func__, con);
ee7d4767	142	pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b	143	}
dc85447b	144
abbc8246	145	static void s3c2412_snd_rxctrl(struct s3c_i2sv2_info *i2s, int on)
dc85447b BD	146	{
	147	void __iomem *regs = i2s->regs;
	148	u32 fic, con, mod;
	149
ee7d4767	150	pr_debug("%s(%d)\n", __func__, on);
dc85447b BD	151
	152	fic = readl(regs + S3C2412_IISFIC);
	153	con = readl(regs + S3C2412_IISCON);
	154	mod = readl(regs + S3C2412_IISMOD);
	155
ee7d4767	156	pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b BD	157
	158	if (on) {
	159	con \|= S3C2412_IISCON_RXDMA_ACTIVE \| S3C2412_IISCON_IIS_ACTIVE;
	160	con &= ~S3C2412_IISCON_RXDMA_PAUSE;
	161	con &= ~S3C2412_IISCON_RXCH_PAUSE;
	162
	163	switch (mod & S3C2412_IISMOD_MODE_MASK) {
	164	case S3C2412_IISMOD_MODE_TXRX:
	165	case S3C2412_IISMOD_MODE_RXONLY:
	166	/* do nothing, we are in the right mode */
	167	break;
	168
	169	case S3C2412_IISMOD_MODE_TXONLY:
	170	mod &= ~S3C2412_IISMOD_MODE_MASK;
	171	mod \|= S3C2412_IISMOD_MODE_TXRX;
	172	break;
	173
	174	default:
abbc8246 MB	175	dev_err(i2s->dev, "RXEN: Invalid MODE %x in IISMOD\n",
abbc8246 MB	176	mod & S3C2412_IISMOD_MODE_MASK);
dc85447b BD	177	}
	178
	179	writel(mod, regs + S3C2412_IISMOD);
	180	writel(con, regs + S3C2412_IISCON);
	181	} else {
	182	/* See txctrl notes on FIFOs. */
	183
	184	con &= ~S3C2412_IISCON_RXDMA_ACTIVE;
	185	con \|= S3C2412_IISCON_RXDMA_PAUSE;
	186	con \|= S3C2412_IISCON_RXCH_PAUSE;
	187
	188	switch (mod & S3C2412_IISMOD_MODE_MASK) {
	189	case S3C2412_IISMOD_MODE_RXONLY:
	190	con &= ~S3C2412_IISCON_IIS_ACTIVE;
	191	mod &= ~S3C2412_IISMOD_MODE_MASK;
	192	break;
	193
	194	case S3C2412_IISMOD_MODE_TXRX:
	195	mod &= ~S3C2412_IISMOD_MODE_MASK;
	196	mod \|= S3C2412_IISMOD_MODE_TXONLY;
	197	break;
	198
	199	default:
abbc8246 MB	200	dev_err(i2s->dev, "RXDIS: Invalid MODE %x in IISMOD\n",
abbc8246 MB	201	mod & S3C2412_IISMOD_MODE_MASK);
dc85447b BD	202	}
	203
	204	writel(con, regs + S3C2412_IISCON);
	205	writel(mod, regs + S3C2412_IISMOD);
	206	}
	207
	208	fic = readl(regs + S3C2412_IISFIC);
ee7d4767	209	pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
dc85447b	210	}
dc85447b	211
fa68e002 J	212	#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
fa68e002 J	213
dc85447b BD	214	/*
	215	* Wait for the LR signal to allow synchronisation to the L/R clock
	216	* from the codec. May only be needed for slave mode.
	217	*/
	218	static int s3c2412_snd_lrsync(struct s3c_i2sv2_info *i2s)
	219	{
	220	u32 iiscon;
fa68e002	221	unsigned long loops = msecs_to_loops(5);
dc85447b	222
ee7d4767	223	pr_debug("Entered %s\n", __func__);
dc85447b	224
fa68e002	225	while (--loops) {
dc85447b BD	226	iiscon = readl(i2s->regs + S3C2412_IISCON);
	227	if (iiscon & S3C2412_IISCON_LRINDEX)
	228	break;
	229
fa68e002 J	230	cpu_relax();
	231	}
	232
	233	if (!loops) {
	234	printk(KERN_ERR "%s: timeout\n", __func__);
	235	return -ETIMEDOUT;
dc85447b BD	236	}
	237
	238	return 0;
	239	}
	240
	241	/*
	242	* Set S3C2412 I2S DAI format
	243	*/
	244	static int s3c2412_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
	245	unsigned int fmt)
	246	{
	247	struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
	248	u32 iismod;
	249
ee7d4767	250	pr_debug("Entered %s\n", __func__);
dc85447b BD	251
dc85447b BD	252	iismod = readl(i2s->regs + S3C2412_IISMOD);
ee7d4767	253	pr_debug("hw_params r: IISMOD: %x \n", iismod);
dc85447b	254
dc85447b BD	255	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	256	case SND_SOC_DAIFMT_CBM_CFM:
	257	i2s->master = 0;
ce76f9fd	258	iismod \|= S3C2412_IISMOD_SLAVE;
dc85447b BD	259	break;
	260	case SND_SOC_DAIFMT_CBS_CFS:
	261	i2s->master = 1;
ce76f9fd	262	iismod &= ~S3C2412_IISMOD_SLAVE;
dc85447b BD	263	break;
dc85447b BD	264	default:
48b418d7	265	pr_err("unknown master/slave format\n");
dc85447b BD	266	return -EINVAL;
	267	}
	268
	269	iismod &= ~S3C2412_IISMOD_SDF_MASK;
	270
	271	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	272	case SND_SOC_DAIFMT_RIGHT_J:
fd5ad654	273	iismod \|= S3C2412_IISMOD_LR_RLOW;
dc85447b BD	274	iismod \|= S3C2412_IISMOD_SDF_MSB;
	275	break;
	276	case SND_SOC_DAIFMT_LEFT_J:
fd5ad654	277	iismod \|= S3C2412_IISMOD_LR_RLOW;
dc85447b BD	278	iismod \|= S3C2412_IISMOD_SDF_LSB;
	279	break;
	280	case SND_SOC_DAIFMT_I2S:
fd5ad654	281	iismod &= ~S3C2412_IISMOD_LR_RLOW;
dc85447b BD	282	iismod \|= S3C2412_IISMOD_SDF_IIS;
	283	break;
	284	default:
38e43c81	285	pr_err("Unknown data format\n");
dc85447b BD	286	return -EINVAL;
	287	}
	288
	289	writel(iismod, i2s->regs + S3C2412_IISMOD);
ee7d4767	290	pr_debug("hw_params w: IISMOD: %x \n", iismod);
dc85447b BD	291	return 0;
	292	}
	293
9c9b1257	294	static int s3c_i2sv2_hw_params(struct snd_pcm_substream *substream,
dc85447b	295	struct snd_pcm_hw_params *params,
f0fba2ad	296	struct snd_soc_dai *dai)
dc85447b	297	{
f0fba2ad	298	struct s3c_i2sv2_info *i2s = to_info(dai);
ea37bd4d	299	struct snd_dmaengine_dai_dma_data *dma_data;
dc85447b BD	300	u32 iismod;
dc85447b BD	301
ee7d4767	302	pr_debug("Entered %s\n", __func__);
dc85447b BD	303
dc85447b BD	304	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
fd23b7de	305	dma_data = i2s->dma_playback;
dc85447b	306	else
fd23b7de DM	307	dma_data = i2s->dma_capture;
fd23b7de DM	308
f0fba2ad	309	snd_soc_dai_set_dma_data(dai, substream, dma_data);
dc85447b BD	310
	311	/* Working copies of register */
	312	iismod = readl(i2s->regs + S3C2412_IISMOD);
ee7d4767	313	pr_debug("%s: r: IISMOD: %x\n", __func__, iismod);
dc85447b	314
bf328826	315	iismod &= ~S3C64XX_IISMOD_BLC_MASK;
553b1dd5	316	/* Sample size */
88ce1465 TB	317	switch (params_width(params)) {
88ce1465 TB	318	case 8:
bf328826	319	iismod \|= S3C64XX_IISMOD_BLC_8BIT;
553b1dd5	320	break;
88ce1465	321	case 16:
553b1dd5	322	break;
88ce1465	323	case 24:
bf328826	324	iismod \|= S3C64XX_IISMOD_BLC_24BIT;
553b1dd5 MB	325	break;
553b1dd5 MB	326	}
dc85447b BD	327
dc85447b BD	328	writel(iismod, i2s->regs + S3C2412_IISMOD);
ee7d4767	329	pr_debug("%s: w: IISMOD: %x\n", __func__, iismod);
8a7c2518 JB	330
	331	return 0;
	332	}
	333
	334	static int s3c_i2sv2_set_sysclk(struct snd_soc_dai *cpu_dai,
	335	int clk_id, unsigned int freq, int dir)
	336	{
	337	struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
	338	u32 iismod = readl(i2s->regs + S3C2412_IISMOD);
	339
	340	pr_debug("Entered %s\n", __func__);
	341	pr_debug("%s r: IISMOD: %x\n", __func__, iismod);
	342
	343	switch (clk_id) {
	344	case S3C_I2SV2_CLKSRC_PCLK:
	345	iismod &= ~S3C2412_IISMOD_IMS_SYSMUX;
	346	break;
	347
	348	case S3C_I2SV2_CLKSRC_AUDIOBUS:
	349	iismod \|= S3C2412_IISMOD_IMS_SYSMUX;
	350	break;
	351
	352	case S3C_I2SV2_CLKSRC_CDCLK:
	353	/* Error if controller doesn't have the CDCLKCON bit */
	354	if (!(i2s->feature & S3C_FEATURE_CDCLKCON))
	355	return -EINVAL;
	356
	357	switch (dir) {
	358	case SND_SOC_CLOCK_IN:
	359	iismod \|= S3C64XX_IISMOD_CDCLKCON;
	360	break;
	361	case SND_SOC_CLOCK_OUT:
	362	iismod &= ~S3C64XX_IISMOD_CDCLKCON;
	363	break;
	364	default:
	365	return -EINVAL;
	366	}
	367	break;
	368
	369	default:
	370	return -EINVAL;
	371	}
	372
	373	writel(iismod, i2s->regs + S3C2412_IISMOD);
	374	pr_debug("%s w: IISMOD: %x\n", __func__, iismod);
	375
dc85447b BD	376	return 0;
	377	}
	378
	379	static int s3c2412_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
	380	struct snd_soc_dai *dai)
	381	{
	382	struct snd_soc_pcm_runtime *rtd = substream->private_data;
7de6b6bc	383	struct s3c_i2sv2_info *i2s = to_info(asoc_rtd_to_cpu(rtd, 0));
dc85447b BD	384	int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
	385	unsigned long irqs;
	386	int ret = 0;
	387
ee7d4767	388	pr_debug("Entered %s\n", __func__);
dc85447b BD	389
	390	switch (cmd) {
	391	case SNDRV_PCM_TRIGGER_START:
	392	/* On start, ensure that the FIFOs are cleared and reset. */
	393
	394	writel(capture ? S3C2412_IISFIC_RXFLUSH : S3C2412_IISFIC_TXFLUSH,
	395	i2s->regs + S3C2412_IISFIC);
	396
	397	/* clear again, just in case */
	398	writel(0x0, i2s->regs + S3C2412_IISFIC);
	399
	400	case SNDRV_PCM_TRIGGER_RESUME:
	401	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	402	if (!i2s->master) {
	403	ret = s3c2412_snd_lrsync(i2s);
	404	if (ret)
	405	goto exit_err;
	406	}
	407
	408	local_irq_save(irqs);
	409
	410	if (capture)
	411	s3c2412_snd_rxctrl(i2s, 1);
	412	else
	413	s3c2412_snd_txctrl(i2s, 1);
	414
	415	local_irq_restore(irqs);
faf907c7	416
dc85447b BD	417	break;
	418
	419	case SNDRV_PCM_TRIGGER_STOP:
	420	case SNDRV_PCM_TRIGGER_SUSPEND:
	421	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	422	local_irq_save(irqs);
	423
	424	if (capture)
	425	s3c2412_snd_rxctrl(i2s, 0);
	426	else
	427	s3c2412_snd_txctrl(i2s, 0);
	428
	429	local_irq_restore(irqs);
	430	break;
	431	default:
	432	ret = -EINVAL;
	433	break;
	434	}
	435
	436	exit_err:
	437	return ret;
	438	}
	439
	440	/*
	441	* Set S3C2412 Clock dividers
	442	*/
	443	static int s3c2412_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai,
	444	int div_id, int div)
	445	{
	446	struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
	447	u32 reg;
	448
ee7d4767	449	pr_debug("%s(%p, %d, %d)\n", __func__, cpu_dai, div_id, div);
dc85447b BD	450
	451	switch (div_id) {
	452	case S3C_I2SV2_DIV_BCLK:
51c6ab13 JB	453	switch (div) {
	454	case 16:
	455	div = S3C2412_IISMOD_BCLK_16FS;
	456	break;
fd5ad654	457
51c6ab13 JB	458	case 32:
	459	div = S3C2412_IISMOD_BCLK_32FS;
	460	break;
fd5ad654	461
51c6ab13 JB	462	case 24:
	463	div = S3C2412_IISMOD_BCLK_24FS;
	464	break;
fd5ad654	465
51c6ab13 JB	466	case 48:
	467	div = S3C2412_IISMOD_BCLK_48FS;
	468	break;
fd5ad654	469
51c6ab13 JB	470	default:
51c6ab13 JB	471	return -EINVAL;
fd5ad654 J	472	}
fd5ad654 J	473
dc85447b BD	474	reg = readl(i2s->regs + S3C2412_IISMOD);
	475	reg &= ~S3C2412_IISMOD_BCLK_MASK;
	476	writel(reg \| div, i2s->regs + S3C2412_IISMOD);
	477
ee7d4767	478	pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
dc85447b BD	479	break;
	480
	481	case S3C_I2SV2_DIV_RCLK:
51c6ab13 JB	482	switch (div) {
	483	case 256:
	484	div = S3C2412_IISMOD_RCLK_256FS;
	485	break;
dc85447b	486
51c6ab13 JB	487	case 384:
	488	div = S3C2412_IISMOD_RCLK_384FS;
	489	break;
dc85447b	490
51c6ab13 JB	491	case 512:
	492	div = S3C2412_IISMOD_RCLK_512FS;
	493	break;
dc85447b	494
51c6ab13 JB	495	case 768:
	496	div = S3C2412_IISMOD_RCLK_768FS;
	497	break;
dc85447b	498
51c6ab13 JB	499	default:
51c6ab13 JB	500	return -EINVAL;
dc85447b BD	501	}
	502
	503	reg = readl(i2s->regs + S3C2412_IISMOD);
	504	reg &= ~S3C2412_IISMOD_RCLK_MASK;
	505	writel(reg \| div, i2s->regs + S3C2412_IISMOD);
ee7d4767	506	pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
dc85447b BD	507	break;
	508
	509	case S3C_I2SV2_DIV_PRESCALER:
	510	if (div >= 0) {
	511	writel((div << 8) \| S3C2412_IISPSR_PSREN,
	512	i2s->regs + S3C2412_IISPSR);
	513	} else {
	514	writel(0x0, i2s->regs + S3C2412_IISPSR);
	515	}
ee7d4767	516	pr_debug("%s: PSR=%08x\n", __func__, readl(i2s->regs + S3C2412_IISPSR));
dc85447b BD	517	break;
	518
	519	default:
	520	return -EINVAL;
	521	}
	522
	523	return 0;
	524	}
	525
1ca75780 MB	526	static snd_pcm_sframes_t s3c2412_i2s_delay(struct snd_pcm_substream *substream,
	527	struct snd_soc_dai *dai)
	528	{
	529	struct s3c_i2sv2_info *i2s = to_info(dai);
	530	u32 reg = readl(i2s->regs + S3C2412_IISFIC);
	531	snd_pcm_sframes_t delay;
	532
	533	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	534	delay = S3C2412_IISFIC_TXCOUNT(reg);
	535	else
	536	delay = S3C2412_IISFIC_RXCOUNT(reg);
	537
	538	return delay;
	539	}
	540
57282427 JB	541	struct clk s3c_i2sv2_get_clock(struct snd_soc_dai cpu_dai)
	542	{
	543	struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
	544	u32 iismod = readl(i2s->regs + S3C2412_IISMOD);
	545
	546	if (iismod & S3C2412_IISMOD_IMS_SYSMUX)
	547	return i2s->iis_cclk;
	548	else
	549	return i2s->iis_pclk;
	550	}
	551	EXPORT_SYMBOL_GPL(s3c_i2sv2_get_clock);
	552
dc85447b BD	553	/* default table of all avaialable root fs divisors */
	554	static unsigned int iis_fs_tab[] = { 256, 512, 384, 768 };
	555
1d2b7ae9 BD	556	int s3c_i2sv2_iis_calc_rate(struct s3c_i2sv2_rate_calc *info,
	557	unsigned int *fstab,
	558	unsigned int rate, struct clk *clk)
dc85447b BD	559	{
	560	unsigned long clkrate = clk_get_rate(clk);
	561	unsigned int div;
	562	unsigned int fsclk;
	563	unsigned int actual;
	564	unsigned int fs;
	565	unsigned int fsdiv;
	566	signed int deviation = 0;
	567	unsigned int best_fs = 0;
	568	unsigned int best_div = 0;
	569	unsigned int best_rate = 0;
	570	unsigned int best_deviation = INT_MAX;
	571
af3ea7bd MB	572	pr_debug("Input clock rate %ldHz\n", clkrate);
af3ea7bd MB	573
dc85447b BD	574	if (fstab == NULL)
	575	fstab = iis_fs_tab;
	576
	577	for (fs = 0; fs < ARRAY_SIZE(iis_fs_tab); fs++) {
	578	fsdiv = iis_fs_tab[fs];
	579
	580	fsclk = clkrate / fsdiv;
	581	div = fsclk / rate;
	582
	583	if ((fsclk % rate) > (rate / 2))
	584	div++;
	585
	586	if (div <= 1)
	587	continue;
	588
	589	actual = clkrate / (fsdiv * div);
	590	deviation = actual - rate;
	591
449bd54d	592	printk(KERN_DEBUG "%ufs: div %u => result %u, deviation %d\n",
dc85447b BD	593	fsdiv, div, actual, deviation);
	594
	595	deviation = abs(deviation);
	596
	597	if (deviation < best_deviation) {
	598	best_fs = fsdiv;
	599	best_div = div;
	600	best_rate = actual;
	601	best_deviation = deviation;
	602	}
	603
	604	if (deviation == 0)
	605	break;
	606	}
	607
449bd54d	608	printk(KERN_DEBUG "best: fs=%u, div=%u, rate=%u\n",
dc85447b BD	609	best_fs, best_div, best_rate);
	610
	611	info->fs_div = best_fs;
	612	info->clk_div = best_div;
	613
	614	return 0;
	615	}
1d2b7ae9	616	EXPORT_SYMBOL_GPL(s3c_i2sv2_iis_calc_rate);
dc85447b	617
f0fba2ad	618	int s3c_i2sv2_probe(struct snd_soc_dai *dai,
dc85447b BD	619	struct s3c_i2sv2_info *i2s,
	620	unsigned long base)
	621	{
f0fba2ad	622	struct device *dev = dai->dev;
07736d48	623	unsigned int iismod;
dc85447b BD	624
	625	i2s->dev = dev;
	626
	627	/* record our i2s structure for later use in the callbacks */
f0fba2ad	628	snd_soc_dai_set_drvdata(dai, i2s);
c86bde54	629
dc85447b	630	i2s->iis_pclk = clk_get(dev, "iis");
fd5ad654	631	if (IS_ERR(i2s->iis_pclk)) {
b52a5195	632	dev_err(dev, "failed to get iis_clock\n");
dc85447b BD	633	return -ENOENT;
	634	}
	635
81ea6cc7	636	clk_prepare_enable(i2s->iis_pclk);
dc85447b	637
07736d48 MB	638	/* Mark ourselves as in TXRX mode so we can run through our cleanup
	639	* process without warnings. */
	640	iismod = readl(i2s->regs + S3C2412_IISMOD);
	641	iismod \|= S3C2412_IISMOD_MODE_TXRX;
	642	writel(iismod, i2s->regs + S3C2412_IISMOD);
dc85447b BD	643	s3c2412_snd_txctrl(i2s, 0);
	644	s3c2412_snd_rxctrl(i2s, 0);
	645
	646	return 0;
	647	}
dc85447b BD	648	EXPORT_SYMBOL_GPL(s3c_i2sv2_probe);
dc85447b BD	649
6f187f7e KK	650	void s3c_i2sv2_cleanup(struct snd_soc_dai *dai,
	651	struct s3c_i2sv2_info *i2s)
	652	{
	653	clk_disable_unprepare(i2s->iis_pclk);
	654	clk_put(i2s->iis_pclk);
	655	i2s->iis_pclk = NULL;
	656	}
	657	EXPORT_SYMBOL_GPL(s3c_i2sv2_cleanup);
	658
eca3b01d	659	int s3c_i2sv2_register_component(struct device *dev, int id,
ba4bc32e	660	const struct snd_soc_component_driver *cmp_drv,
eca3b01d	661	struct snd_soc_dai_driver *dai_drv)
dc85447b	662	{
87b132bc	663	struct snd_soc_dai_ops ops = (struct snd_soc_dai_ops )dai_drv->ops;
3715c6aa BD	664
3715c6aa BD	665	ops->trigger = s3c2412_i2s_trigger;
9c9b1257 JB	666	if (!ops->hw_params)
9c9b1257 JB	667	ops->hw_params = s3c_i2sv2_hw_params;
3715c6aa BD	668	ops->set_fmt = s3c2412_i2s_set_fmt;
3715c6aa BD	669	ops->set_clkdiv = s3c2412_i2s_set_clkdiv;
8a7c2518	670	ops->set_sysclk = s3c_i2sv2_set_sysclk;
dc85447b	671
1ca75780 MB	672	/* Allow overriding by (for example) IISv4 */
1ca75780 MB	673	if (!ops->delay)
08226614	674	ops->delay = s3c2412_i2s_delay;
1ca75780	675
7253e354	676	return devm_snd_soc_register_component(dev, cmp_drv, dai_drv, 1);
dc85447b	677	}
eca3b01d	678	EXPORT_SYMBOL_GPL(s3c_i2sv2_register_component);
a396e32e MB	679
a396e32e MB	680	MODULE_LICENSE("GPL");