[thirdparty/u-boot.git] / src / arm / nxp / imx / mba6ulx.dtsi

// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
 * Copyright 2018-2022 TQ-Systems GmbH
 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
 */

/ {
	model = "TQ-Systems MBA6ULx Baseboard";

	aliases {
		mmc0 = &usdhc2;
		mmc1 = &usdhc1;
		rtc0 = &rtc0;
		rtc1 = &snvs_rtc;
	};

	chosen {
		stdout-path = &uart1;
	};

	backlight: backlight {
		compatible = "pwm-backlight";
		power-supply = <&reg_mba6ul_3v3>;
		enable-gpios = <&expander_out0 4 GPIO_ACTIVE_HIGH>;
		status = "disabled";
	};

	beeper: beeper {
		compatible = "gpio-beeper";
		gpios = <&expander_out1 6 GPIO_ACTIVE_HIGH>;
	};

	gpio_buttons: gpio-keys {
		compatible = "gpio-keys";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_buttons>;

		button-1 {
			label = "s14";
			linux,code = <KEY_1>;
			gpios = <&expander_in0 0 GPIO_ACTIVE_LOW>;
			wakeup-source;
		};

		button-2 {
			label = "s6";
			linux,code = <KEY_2>;
			gpios = <&expander_in0 1 GPIO_ACTIVE_LOW>;
			wakeup-source;
		};

		button-3 {
			label = "s7";
			linux,code = <KEY_3>;
			gpios = <&expander_in0 2 GPIO_ACTIVE_LOW>;
			wakeup-source;
		};

		power-button {
			label = "POWER";
			linux,code = <KEY_POWER>;
			gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
			wakeup-source;
		};
	};

	gpio-leds {
		compatible = "gpio-leds";
		status = "okay";

		led1 {
			label = "led1";
			gpios = <&expander_out1 4 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "default-on";
		};

		led2 {
			label = "led2";
			gpios = <&expander_out1 5 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "heartbeat";
		};
	};

	reg_lcd_pwr: regulator-lcd-pwr {
		compatible = "regulator-fixed";
		regulator-name = "lcd-pwr";
		gpio = <&expander_out0 1 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		status = "disabled";
	};

	reg_mba6ul_3v3: regulator-mba6ul-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "supply-mba6ul-3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	reg_mba6ul_5v0: regulator-mba6ul-5v0 {
		compatible = "regulator-fixed";
		regulator-name = "supply-mba6ul-5v0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-always-on;
	};

	reg_mpcie: regulator-mpcie-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "mpcie-3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&expander_out0 2 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		regulator-always-on;
		startup-delay-us = <500000>;
		vin-supply = <&reg_mba6ul_3v3>;
	};

	reg_otg2vbus_5v0: regulator-otg2-vbus-5v0 {
		compatible = "regulator-fixed";
		gpio = <&expander_out1 0 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		regulator-name = "otg2-vbus-supply-5v0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&reg_mpcie>;
	};

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		linux,cma {
			compatible = "shared-dma-pool";
			reusable;
			size = <0x6000000>;
			linux,cma-default;
		};
	};

	sound {
		compatible = "fsl,imx-audio-tlv320aic32x4";
		model = "imx-audio-tlv320aic32x4";
		ssi-controller = <&sai1>;
		audio-codec = <&tlv320aic32x4>;
		audio-asrc = <&asrc>;
	};
};

&can1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	xceiver-supply = <&reg_mba6ul_3v3>;
	status = "okay";
};

&can2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan2>;
	xceiver-supply = <&reg_mba6ul_3v3>;
	status = "okay";
};

&clks {
	assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
	assigned-clock-rates = <768000000>;
};

&ecspi2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi2>;
	num-cs = <1>;
	status = "okay";
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet1>;
	phy-mode = "rmii";
	phy-handle = <&ethphy0>;
	phy-supply = <&reg_mba6ul_3v3>;
	phy-reset-gpios = <&expander_out1 1 GPIO_ACTIVE_LOW>;
	phy-reset-duration = <25>;
	phy-reset-post-delay = <1>;
	status = "okay";
};

&fec2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_mdc>;
	phy-mode = "rmii";
	phy-handle = <&ethphy1>;
	phy-supply = <&reg_mba6ul_3v3>;
	phy-reset-gpios = <&expander_out1 2 GPIO_ACTIVE_LOW>;
	phy-reset-duration = <25>;
	phy-reset-post-delay = <1>;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			clocks = <&clks IMX6UL_CLK_ENET_REF>;
			reg = <0>;
			max-speed = <100>;
		};

		ethphy1: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			clocks = <&clks IMX6UL_CLK_ENET2_REF_125M>;
			reg = <1>;
			max-speed = <100>;
		};
	};
};

&i2c4 {
	tlv320aic32x4: audio-codec@18 {
		compatible = "ti,tlv320aic32x4";
		reg = <0x18>;
		clocks = <&clks IMX6UL_CLK_SAI1>;
		clock-names = "mclk";
		ldoin-supply = <&reg_mba6ul_3v3>;
		iov-supply = <&reg_mba6ul_3v3>;
	};

	jc42: temperature-sensor@19 {
		compatible = "nxp,se97b", "jedec,jc-42.4-temp";
		reg = <0x19>;
	};

	expander_out0: gpio-expander@20 {
		compatible = "nxp,pca9554";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
		vcc-supply = <&reg_mba6ul_3v3>;
	};

	expander_in0: gpio-expander@21 {
		compatible = "nxp,pca9554";
		reg = <0x21>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_expander_in0>;
		interrupt-parent = <&gpio4>;
		interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
		interrupt-controller;
		#interrupt-cells = <2>;
		gpio-controller;
		#gpio-cells = <2>;
		vcc-supply = <&reg_mba6ul_3v3>;

		enet1_int-hog {
			gpio-hog;
			gpios = <6 0>;
			input;
		};

		enet2_int-hog {
			gpio-hog;
			gpios = <7 0>;
			input;
		};
	};

	expander_out1: gpio-expander@22 {
		compatible = "nxp,pca9554";
		reg = <0x22>;
		gpio-controller;
		#gpio-cells = <2>;
		vcc-supply = <&reg_mba6ul_3v3>;
	};

	analog_touch: touchscreen@41 {
		compatible = "st,stmpe811";
		reg = <0x41>;
		interrupts = <21 IRQ_TYPE_EDGE_FALLING>;
		interrupt-parent = <&gpio4>;
		status = "disabled";

		touchscreen {
			compatible = "st,stmpe-ts";
			st,adc-freq = <1>;      /* 3.25 MHz ADC clock speed */
			st,ave-ctrl = <3>;      /* 8 sample average control */
			st,fraction-z = <7>;    /* 7 length fractional part in z */
			/*
			 * 50 mA typical 80 mA max touchscreen drivers
			 * current limit value
			 */
			st,i-drive = <1>;
			st,mod-12b = <1>;       /* 12-bit ADC */
			st,ref-sel = <0>;       /* internal ADC reference */
			st,sample-time = <4>;   /* ADC converstion time: 80 clocks */
			st,settling = <3>;      /* 1 ms panel driver settling time */
			st,touch-det-delay = <5>; /* 5 ms touch detect interrupt delay */
		};
	};

	/* NXP SE97BTP with temperature sensor + eeprom */
	se97b: eeprom@51 {
		compatible = "nxp,se97b", "atmel,24c02";
		reg = <0x51>;
		pagesize = <16>;
		vcc-supply = <&reg_mba6ul_3v3>;
	};
};

&pwm2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm2>;
	status = "okay";
};

&sai1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai1>;
	assigned-clocks = <&clks IMX6UL_CLK_SAI1_SEL>,
			  <&clks IMX6UL_CLK_SAI1>;
	assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
	assigned-clock-rates = <0>, <24000000>;
	fsl,sai-mclk-direction-output;
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	status = "okay";
};

&uart6 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart6>;
	/* for DTE mode, add below change */
	/* fsl,dte-mode; */
	/* pinctrl-0 = <&pinctrl_uart6dte>; */
	uart-has-rtscts;
	linux,rs485-enabled-at-boot-time;
	rs485-rts-active-low;
	rs485-rx-during-tx;
	status = "okay";
};

/* otg-port */
&usbotg1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb_otg1>;
	power-active-high;
	over-current-active-low;
	/* we implement only dual role but not a fully featured OTG */
	hnp-disable;
	srp-disable;
	adp-disable;
	dr_mode = "otg";
	status = "okay";
};

/* 7-port usb hub */
/* id, pwr, oc pins not connected */
&usbotg2 {
	disable-over-current;
	vbus-supply = <&reg_otg2vbus_5v0>;
	dr_mode = "host";
	status = "okay";
};

&usdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc1>;
	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
	bus-width = <4>;
	vmmc-supply = <&reg_mba6ul_3v3>;
	vqmmc-supply = <&reg_vccsd>;
	no-1-8-v;
	no-mmc;
	no-sdio;
	status = "okay";
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog1>;
	fsl,ext-reset-output;
	status = "okay";
};

&iomuxc {
	pinctrl_buttons: buttonsgrp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO03__GPIO1_IO03	0x100b0
		>;
	};

	pinctrl_ecspi2: ecspi2grp {
		fsl,pins = <
			MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK	0x1b020
			MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO	0x1b020
			MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI	0x1b020
			MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0	0x1b020
		>;
	};

	pinctrl_enet1: enet1grp {
		fsl,pins = <
			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0
			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b0a8
		>;
	};

	pinctrl_enet2: enet2grp {
		fsl,pins = <
			MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
			MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
			MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
			MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
			MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0a0
			MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0a0
			MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
			MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b0a8
		>;
	};

	pinctrl_enet2_mdc: enet2mdcgrp {
		fsl,pins = <
			/* mdio */
			MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
			MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
		>;
	};

	pinctrl_expander_in0: expanderin0grp {
		fsl,pins = <
			MX6UL_PAD_CSI_DATA02__GPIO4_IO23	0x1b0b1
		>;
	};

	pinctrl_flexcan1: flexcan1grp {
		fsl,pins = <
			MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX	0x1b020
			MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX	0x1b020
		>;
	};

	pinctrl_flexcan2: flexcan2grp {
		fsl,pins = <
			MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX	0x1b020
			MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX	0x1b020
		>;
	};

	pinctrl_pwm2: pwm2grp {
		fsl,pins = <
			/* 100 k PD, DSE 120 OHM, SPEED LO */
			MX6UL_PAD_GPIO1_IO09__PWM2_OUT		0x00003050
		>;
	};

	pinctrl_sai1: sai1grp {
		fsl,pins = <
			MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK	0x1b0b1
			MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC	0x1b0b1
			MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA	0x1f0b8
			MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA	0x110b0
			MX6UL_PAD_CSI_DATA01__SAI1_MCLK		0x1b0b1
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX	0x1b0b1
			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX	0x1b0b1
		>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins = <
			MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX	0x1b0b1
			MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX	0x1b0b1
		>;
	};

	pinctrl_uart6: uart6grp {
		fsl,pins = <
			MX6UL_PAD_CSI_MCLK__UART6_DCE_TX	0x1b0b1
			MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX	0x1b0b1
			MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS	0x1b0b1
			MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS	0x1b0b1
		>;
	};

	pinctrl_uart6dte: uart6dte {
		fsl,pins = <
			MX6UL_PAD_CSI_PIXCLK__UART6_DTE_TX	0x1b0b1
			MX6UL_PAD_CSI_MCLK__UART6_DTE_RX	0x1b0b1
			MX6UL_PAD_CSI_HSYNC__UART6_DTE_RTS	0x1b0b1
			MX6UL_PAD_CSI_VSYNC__UART6_DTE_CTS	0x1b0b1
		>;
	};

	pinctrl_usb_otg1: usbotg1grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID	0x00017059
			MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC	0x0001b0b0
			MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR	0x0001b099
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x00017069
			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x00017059
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x00017059
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x00017059
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x00017059
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x00017059
			/* WP */
			MX6UL_PAD_UART1_CTS_B__GPIO1_IO18	0x0001b099
			/* CD */
			MX6UL_PAD_UART1_RTS_B__GPIO1_IO19	0x0001b099
		>;
	};

	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
		fsl,pins = <
			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x00017069
			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x000170b9
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x000170b9
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x000170b9
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x000170b9
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x000170b9
			/* WP */
			MX6UL_PAD_UART1_CTS_B__GPIO1_IO18	0x0001b099
			/* CD */
			MX6UL_PAD_UART1_RTS_B__GPIO1_IO19	0x0001b099
		>;
	};

	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
		fsl,pins = <
			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x00017069
			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x000170f9
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x000170f9
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x000170f9
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x000170f9
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x000170f9
			/* WP */
			MX6UL_PAD_UART1_CTS_B__GPIO1_IO18	0x0001b099
			/* CD */
			MX6UL_PAD_UART1_RTS_B__GPIO1_IO19	0x0001b099
		>;
	};

	pinctrl_wdog1: wdog1grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B	0x0001b099
		>;
	};
};
Commit	Line	Data
53633a89 TR	1	// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
	2	/*
	3	* Copyright 2018-2022 TQ-Systems GmbH
	4	* Author: Markus Niebel <Markus.Niebel@tq-group.com>
	5	*/
	6
	7	/ {
	8	model = "TQ-Systems MBA6ULx Baseboard";
	9
	10	aliases {
	11	mmc0 = &usdhc2;
	12	mmc1 = &usdhc1;
	13	rtc0 = &rtc0;
	14	rtc1 = &snvs_rtc;
	15	};
	16
	17	chosen {
	18	stdout-path = &uart1;
	19	};
	20
	21	backlight: backlight {
	22	compatible = "pwm-backlight";
	23	power-supply = <&reg_mba6ul_3v3>;
	24	enable-gpios = <&expander_out0 4 GPIO_ACTIVE_HIGH>;
	25	status = "disabled";
	26	};
	27
	28	beeper: beeper {
	29	compatible = "gpio-beeper";
	30	gpios = <&expander_out1 6 GPIO_ACTIVE_HIGH>;
	31	};
	32
	33	gpio_buttons: gpio-keys {
	34	compatible = "gpio-keys";
	35	pinctrl-names = "default";
	36	pinctrl-0 = <&pinctrl_buttons>;
	37
	38	button-1 {
	39	label = "s14";
	40	linux,code = <KEY_1>;
	41	gpios = <&expander_in0 0 GPIO_ACTIVE_LOW>;
	42	wakeup-source;
	43	};
	44
	45	button-2 {
	46	label = "s6";
	47	linux,code = <KEY_2>;
	48	gpios = <&expander_in0 1 GPIO_ACTIVE_LOW>;
	49	wakeup-source;
	50	};
	51
	52	button-3 {
	53	label = "s7";
	54	linux,code = <KEY_3>;
	55	gpios = <&expander_in0 2 GPIO_ACTIVE_LOW>;
	56	wakeup-source;
	57	};
	58
	59	power-button {
	60	label = "POWER";
	61	linux,code = <KEY_POWER>;
	62	gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
	63	wakeup-source;
	64	};
65	};
66
67	gpio-leds {
68	compatible = "gpio-leds";
69	status = "okay";
70
71	led1 {
72	label = "led1";
73	gpios = <&expander_out1 4 GPIO_ACTIVE_HIGH>;
74	linux,default-trigger = "default-on";
75	};
76
77	led2 {
78	label = "led2";
79	gpios = <&expander_out1 5 GPIO_ACTIVE_HIGH>;
80	linux,default-trigger = "heartbeat";
81	};
82	};
83
84	reg_lcd_pwr: regulator-lcd-pwr {
85	compatible = "regulator-fixed";
86	regulator-name = "lcd-pwr";
87	gpio = <&expander_out0 1 GPIO_ACTIVE_HIGH>;
88	enable-active-high;
89	status = "disabled";
90	};
91
92	reg_mba6ul_3v3: regulator-mba6ul-3v3 {
93	compatible = "regulator-fixed";
94	regulator-name = "supply-mba6ul-3v3";
95	regulator-min-microvolt = <3300000>;
96	regulator-max-microvolt = <3300000>;
97	regulator-always-on;
98	};
99
100	reg_mba6ul_5v0: regulator-mba6ul-5v0 {
101	compatible = "regulator-fixed";
102	regulator-name = "supply-mba6ul-5v0";
103	regulator-min-microvolt = <5000000>;
104	regulator-max-microvolt = <5000000>;
105	regulator-always-on;
106	};
107
108	reg_mpcie: regulator-mpcie-3v3 {
109	compatible = "regulator-fixed";
110	regulator-name = "mpcie-3v3";
111	regulator-min-microvolt = <3300000>;
112	regulator-max-microvolt = <3300000>;
113	gpio = <&expander_out0 2 GPIO_ACTIVE_HIGH>;
114	enable-active-high;
115	regulator-always-on;
116	startup-delay-us = <500000>;
117	vin-supply = <&reg_mba6ul_3v3>;
118	};
119
120	reg_otg2vbus_5v0: regulator-otg2-vbus-5v0 {
121	compatible = "regulator-fixed";
122	gpio = <&expander_out1 0 GPIO_ACTIVE_HIGH>;
123	enable-active-high;
124	regulator-name = "otg2-vbus-supply-5v0";
125	regulator-min-microvolt = <5000000>;
126	regulator-max-microvolt = <5000000>;
127	vin-supply = <&reg_mpcie>;
128	};
129
130	reserved-memory {
131	#address-cells = <1>;
132	#size-cells = <1>;
133	ranges;
134
135	linux,cma {
136	compatible = "shared-dma-pool";
137	reusable;
138	size = <0x6000000>;
139	linux,cma-default;
140	};
141	};
142
143	sound {
144	compatible = "fsl,imx-audio-tlv320aic32x4";
145	model = "imx-audio-tlv320aic32x4";
146	ssi-controller = <&sai1>;
147	audio-codec = <&tlv320aic32x4>;
148	audio-asrc = <&asrc>;
149	};
150	};
151
152	&can1 {
153	pinctrl-names = "default";
154	pinctrl-0 = <&pinctrl_flexcan1>;
155	xceiver-supply = <&reg_mba6ul_3v3>;
156	status = "okay";
157	};
158
159	&can2 {
160	pinctrl-names = "default";
161	pinctrl-0 = <&pinctrl_flexcan2>;
162	xceiver-supply = <&reg_mba6ul_3v3>;
163	status = "okay";
164	};
165
166	&clks {
167	assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
168	assigned-clock-rates = <768000000>;
169	};
170
171	&ecspi2 {
172	pinctrl-names = "default";
173	pinctrl-0 = <&pinctrl_ecspi2>;
174	num-cs = <1>;
175	status = "okay";
176	};
177
178	&fec1 {
179	pinctrl-names = "default";
180	pinctrl-0 = <&pinctrl_enet1>;
181	phy-mode = "rmii";
182	phy-handle = <&ethphy0>;
183	phy-supply = <&reg_mba6ul_3v3>;
184	phy-reset-gpios = <&expander_out1 1 GPIO_ACTIVE_LOW>;
185	phy-reset-duration = <25>;
186	phy-reset-post-delay = <1>;
187	status = "okay";
188	};
189
190	&fec2 {
191	pinctrl-names = "default";
192	pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_mdc>;
193	phy-mode = "rmii";
194	phy-handle = <&ethphy1>;
195	phy-supply = <&reg_mba6ul_3v3>;
196	phy-reset-gpios = <&expander_out1 2 GPIO_ACTIVE_LOW>;
197	phy-reset-duration = <25>;
198	phy-reset-post-delay = <1>;
199	status = "okay";
200
201	mdio {
202	#address-cells = <1>;
203	#size-cells = <0>;
204
205	ethphy0: ethernet-phy@0 {
206	compatible = "ethernet-phy-ieee802.3-c22";
207	clocks = <&clks IMX6UL_CLK_ENET_REF>;
208	reg = <0>;
209	max-speed = <100>;
210	};
211
212	ethphy1: ethernet-phy@1 {
213	compatible = "ethernet-phy-ieee802.3-c22";
214	clocks = <&clks IMX6UL_CLK_ENET2_REF_125M>;
215	reg = <1>;
216	max-speed = <100>;
217	};
218	};
219	};
220
221	&i2c4 {
222	tlv320aic32x4: audio-codec@18 {
223	compatible = "ti,tlv320aic32x4";
224	reg = <0x18>;
225	clocks = <&clks IMX6UL_CLK_SAI1>;
226	clock-names = "mclk";
227	ldoin-supply = <&reg_mba6ul_3v3>;
228	iov-supply = <&reg_mba6ul_3v3>;
229	};
230
231	jc42: temperature-sensor@19 {
232	compatible = "nxp,se97b", "jedec,jc-42.4-temp";
233	reg = <0x19>;
234	};
235
236	expander_out0: gpio-expander@20 {
237	compatible = "nxp,pca9554";
238	reg = <0x20>;
239	gpio-controller;
240	#gpio-cells = <2>;
241	vcc-supply = <&reg_mba6ul_3v3>;
242	};
243
244	expander_in0: gpio-expander@21 {
245	compatible = "nxp,pca9554";
246	reg = <0x21>;
247	pinctrl-names = "default";
248	pinctrl-0 = <&pinctrl_expander_in0>;
249	interrupt-parent = <&gpio4>;
250	interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
251	interrupt-controller;
252	#interrupt-cells = <2>;
253	gpio-controller;
254	#gpio-cells = <2>;
255	vcc-supply = <&reg_mba6ul_3v3>;
256
257	enet1_int-hog {
258	gpio-hog;
259	gpios = <6 0>;
260	input;
261	};
262
263	enet2_int-hog {
264	gpio-hog;
265	gpios = <7 0>;
266	input;
267	};
268	};
269
270	expander_out1: gpio-expander@22 {
271	compatible = "nxp,pca9554";
272	reg = <0x22>;
273	gpio-controller;
274	#gpio-cells = <2>;
275	vcc-supply = <&reg_mba6ul_3v3>;
276	};
277
278	analog_touch: touchscreen@41 {
279	compatible = "st,stmpe811";
280	reg = <0x41>;
281	interrupts = <21 IRQ_TYPE_EDGE_FALLING>;
282	interrupt-parent = <&gpio4>;
283	status = "disabled";
284
285	touchscreen {
286	compatible = "st,stmpe-ts";
287	st,adc-freq = <1>; /* 3.25 MHz ADC clock speed */
288	st,ave-ctrl = <3>; /* 8 sample average control */
289	st,fraction-z = <7>; /* 7 length fractional part in z */
290	/*
291	* 50 mA typical 80 mA max touchscreen drivers
292	* current limit value
293	*/
294	st,i-drive = <1>;
295	st,mod-12b = <1>; /* 12-bit ADC */
296	st,ref-sel = <0>; /* internal ADC reference */
297	st,sample-time = <4>; /* ADC converstion time: 80 clocks */
298	st,settling = <3>; /* 1 ms panel driver settling time */
299	st,touch-det-delay = <5>; /* 5 ms touch detect interrupt delay */
300	};
301	};
302
303	/* NXP SE97BTP with temperature sensor + eeprom */
304	se97b: eeprom@51 {
305	compatible = "nxp,se97b", "atmel,24c02";
306	reg = <0x51>;
307	pagesize = <16>;
308	vcc-supply = <&reg_mba6ul_3v3>;
309	};
310	};
311
312	&pwm2 {
313	pinctrl-names = "default";
314	pinctrl-0 = <&pinctrl_pwm2>;
315	status = "okay";
316	};
317
318	&sai1 {
319	pinctrl-names = "default";
320	pinctrl-0 = <&pinctrl_sai1>;
321	assigned-clocks = <&clks IMX6UL_CLK_SAI1_SEL>,
322	<&clks IMX6UL_CLK_SAI1>;
323	assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
324	assigned-clock-rates = <0>, <24000000>;
325	fsl,sai-mclk-direction-output;
326	status = "okay";
327	};
328
329	&uart1 {
330	pinctrl-names = "default";
331	pinctrl-0 = <&pinctrl_uart1>;
332	status = "okay";
333	};
334
335	&uart3 {
336	pinctrl-names = "default";
337	pinctrl-0 = <&pinctrl_uart3>;
338	status = "okay";
339	};
340
341	&uart6 {
342	pinctrl-names = "default";
343	pinctrl-0 = <&pinctrl_uart6>;
344	/* for DTE mode, add below change */
345	/* fsl,dte-mode; */
346	/* pinctrl-0 = <&pinctrl_uart6dte>; */
347	uart-has-rtscts;
348	linux,rs485-enabled-at-boot-time;
349	rs485-rts-active-low;
350	rs485-rx-during-tx;
351	status = "okay";
352	};
353
354	/* otg-port */
355	&usbotg1 {
356	pinctrl-names = "default";
357	pinctrl-0 = <&pinctrl_usb_otg1>;
358	power-active-high;
359	over-current-active-low;
360	/* we implement only dual role but not a fully featured OTG */
361	hnp-disable;
362	srp-disable;
363	adp-disable;
364	dr_mode = "otg";
365	status = "okay";
366	};
367
368	/* 7-port usb hub */
369	/* id, pwr, oc pins not connected */
370	&usbotg2 {
371	disable-over-current;
372	vbus-supply = <&reg_otg2vbus_5v0>;
373	dr_mode = "host";
374	status = "okay";
375	};
376
377	&usdhc1 {
378	pinctrl-names = "default";
379	pinctrl-0 = <&pinctrl_usdhc1>;
380	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
381	wp-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
382	bus-width = <4>;
383	vmmc-supply = <&reg_mba6ul_3v3>;
384	vqmmc-supply = <&reg_vccsd>;
385	no-1-8-v;
386	no-mmc;
387	no-sdio;
388	status = "okay";
389	};
390
391	&wdog1 {
392	pinctrl-names = "default";
393	pinctrl-0 = <&pinctrl_wdog1>;
394	fsl,ext-reset-output;
395	status = "okay";
396	};
397
398	&iomuxc {
399	pinctrl_buttons: buttonsgrp {
400	fsl,pins = <
401	MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x100b0
402	>;
403	};
404
405	pinctrl_ecspi2: ecspi2grp {
406	fsl,pins = <
407	MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x1b020
408	MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x1b020
409	MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x1b020
410	MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0 0x1b020
411	>;
412	};
413
414	pinctrl_enet1: enet1grp {
415	fsl,pins = <
416	MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
417	MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
418	MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
419	MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
420	MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
421	MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
422	MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
423	MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b0a8
424	>;
425	};
426
427	pinctrl_enet2: enet2grp {
428	fsl,pins = <
429	MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
430	MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
431	MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
432	MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
433	MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0a0
434	MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0a0
435	MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
436	MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b0a8
437	>;
438	};
439
440	pinctrl_enet2_mdc: enet2mdcgrp {
441	fsl,pins = <
442	/* mdio */
443	MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
444	MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
445	>;
446	};
447
448	pinctrl_expander_in0: expanderin0grp {
449	fsl,pins = <
450	MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x1b0b1
451	>;
452	};
453
454	pinctrl_flexcan1: flexcan1grp {
455	fsl,pins = <
456	MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
457	MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
458	>;
459	};
460
461	pinctrl_flexcan2: flexcan2grp {
462	fsl,pins = <
463	MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
464	MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
465	>;
466	};
467
468	pinctrl_pwm2: pwm2grp {
469	fsl,pins = <
93743d24	470	/* 100 k PD, DSE 120 OHM, SPEED LO */
53633a89 TR	471	MX6UL_PAD_GPIO1_IO09__PWM2_OUT 0x00003050
	472	>;
	473	};
	474
	475	pinctrl_sai1: sai1grp {
	476	fsl,pins = <
	477	MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x1b0b1
	478	MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x1b0b1
	479	MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x1f0b8
	480	MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x110b0
	481	MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x1b0b1
	482	>;
	483	};
	484
	485	pinctrl_uart1: uart1grp {
	486	fsl,pins = <
	487	MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
	488	MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
	489	>;
	490	};
	491
	492	pinctrl_uart3: uart3grp {
	493	fsl,pins = <
	494	MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
	495	MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
	496	>;
	497	};
	498
	499	pinctrl_uart6: uart6grp {
	500	fsl,pins = <
	501	MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1
	502	MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1
	503	MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS 0x1b0b1
	504	MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS 0x1b0b1
	505	>;
	506	};
	507
	508	pinctrl_uart6dte: uart6dte {
	509	fsl,pins = <
	510	MX6UL_PAD_CSI_PIXCLK__UART6_DTE_TX 0x1b0b1
	511	MX6UL_PAD_CSI_MCLK__UART6_DTE_RX 0x1b0b1
	512	MX6UL_PAD_CSI_HSYNC__UART6_DTE_RTS 0x1b0b1
	513	MX6UL_PAD_CSI_VSYNC__UART6_DTE_CTS 0x1b0b1
	514	>;
	515	};
	516
	517	pinctrl_usb_otg1: usbotg1grp {
	518	fsl,pins = <
	519	MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x00017059
	520	MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x0001b0b0
	521	MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR 0x0001b099
	522	>;
	523	};
	524
	525	pinctrl_usdhc1: usdhc1grp {
	526	fsl,pins = <
	527	MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069
	528	MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x00017059
	529	MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x00017059
	530	MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x00017059
	531	MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x00017059
	532	MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x00017059
	533	/* WP */
	534	MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0001b099
535	/* CD */
536	MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099
537	>;
538	};
539
540	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
541	fsl,pins = <
542	MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069
543	MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x000170b9
544	MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x000170b9
545	MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x000170b9
546	MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x000170b9
547	MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x000170b9
548	/* WP */
549	MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0001b099
550	/* CD */
551	MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099
552	>;
553	};
554
555	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
556	fsl,pins = <
557	MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069
558	MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x000170f9
559	MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x000170f9
560	MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x000170f9
561	MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x000170f9
562	MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x000170f9
563	/* WP */
564	MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0001b099
565	/* CD */
566	MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099
567	>;
568	};
569
570	pinctrl_wdog1: wdog1grp {
571	fsl,pins = <
572	MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0001b099
573	>;
574	};
575	};