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53633a89 TR |
1 | // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
2 | ||
3 | /* | |
4 | * Device tree file for ZII's SSMB SPU3 board | |
5 | * | |
6 | * SSMB - SPU3 Switch Management Board | |
7 | * SPU - Seat Power Unit | |
8 | * | |
9 | * Copyright (C) 2015, 2016 Zodiac Inflight Innovations | |
10 | * | |
11 | * Based on an original 'vf610-twr.dts' which is Copyright 2015, | |
12 | * Freescale Semiconductor, Inc. | |
13 | */ | |
14 | ||
15 | /dts-v1/; | |
16 | #include "vf610.dtsi" | |
17 | ||
18 | / { | |
19 | model = "ZII VF610 SSMB SPU3 Board"; | |
20 | compatible = "zii,vf610spu3", "zii,vf610dev", "fsl,vf610"; | |
21 | ||
22 | chosen { | |
23 | stdout-path = &uart0; | |
24 | }; | |
25 | ||
26 | memory@80000000 { | |
27 | device_type = "memory"; | |
28 | reg = <0x80000000 0x20000000>; | |
29 | }; | |
30 | ||
31 | gpio-leds { | |
32 | compatible = "gpio-leds"; | |
33 | pinctrl-0 = <&pinctrl_leds_debug>; | |
34 | pinctrl-names = "default"; | |
35 | ||
36 | led-debug { | |
37 | label = "zii:green:debug1"; | |
38 | gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; | |
39 | linux,default-trigger = "heartbeat"; | |
40 | }; | |
41 | }; | |
42 | ||
43 | reg_vcc_3v3_mcu: regulator { | |
44 | compatible = "regulator-fixed"; | |
45 | regulator-name = "vcc_3v3_mcu"; | |
46 | regulator-min-microvolt = <3300000>; | |
47 | regulator-max-microvolt = <3300000>; | |
48 | }; | |
49 | ||
50 | supply-voltage-monitor { | |
51 | compatible = "iio-hwmon"; | |
52 | io-channels = <&adc0 8>, /* 12V_MAIN */ | |
53 | <&adc0 9>, /* +3.3V */ | |
54 | <&adc1 8>, /* VCC_1V5 */ | |
55 | <&adc1 9>; /* VCC_1V2 */ | |
56 | }; | |
57 | }; | |
58 | ||
59 | &adc0 { | |
60 | vref-supply = <®_vcc_3v3_mcu>; | |
61 | status = "okay"; | |
62 | }; | |
63 | ||
64 | &adc1 { | |
65 | vref-supply = <®_vcc_3v3_mcu>; | |
66 | status = "okay"; | |
67 | }; | |
68 | ||
69 | &dspi1 { | |
70 | bus-num = <1>; | |
71 | pinctrl-names = "default"; | |
72 | pinctrl-0 = <&pinctrl_dspi1>; | |
73 | /* | |
74 | * Some SPU3s come with SPI-NOR chip DNPed, so we leave this | |
75 | * node disabled by default and rely on bootloader to enable | |
76 | * it when appropriate. | |
77 | */ | |
78 | status = "disabled"; | |
79 | ||
80 | flash@0 { | |
81 | #address-cells = <1>; | |
82 | #size-cells = <1>; | |
83 | compatible = "m25p128", "jedec,spi-nor"; | |
84 | reg = <0>; | |
85 | spi-max-frequency = <50000000>; | |
86 | ||
87 | partition@0 { | |
88 | label = "m25p128-0"; | |
89 | reg = <0x0 0x01000000>; | |
90 | }; | |
91 | }; | |
92 | }; | |
93 | ||
94 | &edma0 { | |
95 | status = "okay"; | |
96 | }; | |
97 | ||
98 | &edma1 { | |
99 | status = "okay"; | |
100 | }; | |
101 | ||
102 | &esdhc0 { | |
103 | pinctrl-names = "default"; | |
104 | pinctrl-0 = <&pinctrl_esdhc0>; | |
105 | bus-width = <8>; | |
106 | non-removable; | |
107 | no-1-8-v; | |
108 | keep-power-in-suspend; | |
109 | no-sdio; | |
110 | no-sd; | |
111 | status = "okay"; | |
112 | }; | |
113 | ||
114 | &esdhc1 { | |
115 | pinctrl-names = "default"; | |
116 | pinctrl-0 = <&pinctrl_esdhc1>; | |
117 | bus-width = <4>; | |
118 | no-sdio; | |
119 | status = "okay"; | |
120 | }; | |
121 | ||
122 | &fec1 { | |
123 | phy-mode = "rmii"; | |
124 | pinctrl-names = "default"; | |
125 | pinctrl-0 = <&pinctrl_fec1>; | |
126 | status = "okay"; | |
127 | ||
128 | fixed-link { | |
129 | speed = <100>; | |
130 | full-duplex; | |
131 | }; | |
132 | ||
133 | mdio1: mdio { | |
134 | #address-cells = <1>; | |
135 | #size-cells = <0>; | |
136 | clock-frequency = <12500000>; | |
137 | suppress-preamble; | |
138 | status = "okay"; | |
139 | ||
140 | switch0: switch0@0 { | |
141 | compatible = "marvell,mv88e6190"; | |
142 | pinctrl-0 = <&pinctrl_gpio_switch0>; | |
143 | pinctrl-names = "default"; | |
144 | reg = <0>; | |
145 | eeprom-length = <65536>; | |
146 | interrupt-parent = <&gpio3>; | |
147 | interrupts = <2 IRQ_TYPE_LEVEL_LOW>; | |
148 | interrupt-controller; | |
149 | #interrupt-cells = <2>; | |
150 | ||
151 | ports { | |
152 | #address-cells = <1>; | |
153 | #size-cells = <0>; | |
154 | ||
155 | port@0 { | |
156 | reg = <0>; | |
157 | phy-mode = "rmii"; | |
158 | ethernet = <&fec1>; | |
159 | ||
160 | fixed-link { | |
161 | speed = <100>; | |
162 | full-duplex; | |
163 | }; | |
164 | }; | |
165 | ||
166 | port@1 { | |
167 | reg = <1>; | |
168 | label = "eth_cu_1000_1"; | |
169 | }; | |
170 | ||
171 | port@2 { | |
172 | reg = <2>; | |
173 | label = "eth_cu_1000_2"; | |
174 | }; | |
175 | ||
176 | port@3 { | |
177 | reg = <3>; | |
178 | label = "eth_cu_1000_3"; | |
179 | }; | |
180 | ||
181 | port@4 { | |
182 | reg = <4>; | |
183 | label = "eth_cu_1000_4"; | |
184 | }; | |
185 | ||
186 | port@5 { | |
187 | reg = <5>; | |
188 | label = "eth_cu_1000_5"; | |
189 | }; | |
190 | ||
191 | port@6 { | |
192 | reg = <6>; | |
193 | label = "eth_cu_1000_6"; | |
194 | }; | |
195 | }; | |
196 | }; | |
197 | }; | |
198 | }; | |
199 | ||
200 | &i2c0 { | |
201 | clock-frequency = <100000>; | |
202 | pinctrl-names = "default"; | |
203 | pinctrl-0 = <&pinctrl_i2c0>; | |
204 | status = "okay"; | |
205 | ||
206 | gpio6: io-expander@22 { | |
207 | compatible = "nxp,pca9554"; | |
208 | reg = <0x22>; | |
209 | gpio-controller; | |
210 | #gpio-cells = <2>; | |
211 | }; | |
212 | ||
213 | lm75@48 { | |
214 | compatible = "national,lm75"; | |
215 | reg = <0x48>; | |
216 | }; | |
217 | ||
218 | eeprom@50 { | |
219 | compatible = "atmel,24c04"; | |
220 | reg = <0x50>; | |
221 | label = "nameplate"; | |
222 | }; | |
223 | ||
224 | eeprom@52 { | |
225 | compatible = "atmel,24c04"; | |
226 | reg = <0x52>; | |
227 | }; | |
228 | }; | |
229 | ||
230 | &i2c1 { | |
231 | clock-frequency = <100000>; | |
232 | pinctrl-names = "default"; | |
233 | pinctrl-0 = <&pinctrl_i2c1>; | |
234 | status = "okay"; | |
235 | ||
236 | watchdog@38 { | |
237 | compatible = "zii,rave-wdt"; | |
238 | reg = <0x38>; | |
239 | }; | |
240 | }; | |
241 | ||
242 | &snvsrtc { | |
243 | status = "disabled"; | |
244 | }; | |
245 | ||
246 | &uart0 { | |
247 | pinctrl-names = "default"; | |
248 | pinctrl-0 = <&pinctrl_uart0>; | |
249 | status = "okay"; | |
250 | }; | |
251 | ||
252 | &uart1 { | |
253 | pinctrl-names = "default"; | |
254 | pinctrl-0 = <&pinctrl_uart1>; | |
255 | status = "okay"; | |
256 | ||
257 | mcu { | |
258 | compatible = "zii,rave-sp-rdu2"; | |
259 | current-speed = <1000000>; | |
260 | #address-cells = <1>; | |
261 | #size-cells = <1>; | |
262 | ||
263 | watchdog { | |
264 | compatible = "zii,rave-sp-watchdog"; | |
265 | }; | |
266 | ||
267 | eeprom@a3 { | |
268 | compatible = "zii,rave-sp-eeprom"; | |
269 | reg = <0xa3 0x4000>; | |
270 | #address-cells = <1>; | |
271 | #size-cells = <1>; | |
272 | zii,eeprom-name = "main-eeprom"; | |
273 | }; | |
274 | }; | |
275 | }; | |
276 | ||
277 | &wdoga5 { | |
278 | status = "disabled"; | |
279 | }; | |
280 | ||
281 | &iomuxc { | |
282 | pinctrl_dspi1: dspi1grp { | |
283 | fsl,pins = < | |
284 | VF610_PAD_PTD5__DSPI1_CS0 0x1182 | |
285 | VF610_PAD_PTD4__DSPI1_CS1 0x1182 | |
286 | VF610_PAD_PTC6__DSPI1_SIN 0x1181 | |
287 | VF610_PAD_PTC7__DSPI1_SOUT 0x1182 | |
288 | VF610_PAD_PTC8__DSPI1_SCK 0x1182 | |
289 | >; | |
290 | }; | |
291 | ||
292 | pinctrl_esdhc0: esdhc0grp { | |
293 | fsl,pins = < | |
294 | VF610_PAD_PTC0__ESDHC0_CLK 0x31ef | |
295 | VF610_PAD_PTC1__ESDHC0_CMD 0x31ef | |
296 | VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef | |
297 | VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef | |
298 | VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef | |
299 | VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef | |
300 | VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef | |
301 | VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef | |
302 | VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef | |
303 | VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef | |
304 | >; | |
305 | }; | |
306 | ||
307 | pinctrl_esdhc1: esdhc1grp { | |
308 | fsl,pins = < | |
309 | VF610_PAD_PTA24__ESDHC1_CLK 0x31ef | |
310 | VF610_PAD_PTA25__ESDHC1_CMD 0x31ef | |
311 | VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef | |
312 | VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef | |
313 | VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef | |
314 | VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef | |
315 | >; | |
316 | }; | |
317 | ||
318 | pinctrl_fec1: fec1grp { | |
319 | fsl,pins = < | |
320 | VF610_PAD_PTA6__RMII_CLKIN 0x30d1 | |
321 | VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 | |
322 | VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 | |
323 | VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 | |
324 | VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 | |
325 | VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 | |
326 | VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 | |
327 | VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 | |
328 | VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 | |
329 | VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 | |
330 | >; | |
331 | }; | |
332 | ||
333 | pinctrl_gpio_switch0: pinctrl-gpio-switch0 { | |
334 | fsl,pins = < | |
335 | VF610_PAD_PTB28__GPIO_98 0x219d | |
336 | >; | |
337 | }; | |
338 | ||
339 | pinctrl_i2c0: i2c0grp { | |
340 | fsl,pins = < | |
341 | VF610_PAD_PTB14__I2C0_SCL 0x37ff | |
342 | VF610_PAD_PTB15__I2C0_SDA 0x37ff | |
343 | >; | |
344 | }; | |
345 | ||
346 | pinctrl_i2c1: i2c1grp { | |
347 | fsl,pins = < | |
348 | VF610_PAD_PTB16__I2C1_SCL 0x37ff | |
349 | VF610_PAD_PTB17__I2C1_SDA 0x37ff | |
350 | >; | |
351 | }; | |
352 | ||
353 | pinctrl_leds_debug: pinctrl-leds-debug { | |
354 | fsl,pins = < | |
355 | VF610_PAD_PTD3__GPIO_82 0x31c2 | |
356 | >; | |
357 | }; | |
358 | ||
359 | pinctrl_uart0: uart0grp { | |
360 | fsl,pins = < | |
361 | VF610_PAD_PTB10__UART0_TX 0x21a2 | |
362 | VF610_PAD_PTB11__UART0_RX 0x21a1 | |
363 | >; | |
364 | }; | |
365 | ||
366 | pinctrl_uart1: uart1grp { | |
367 | fsl,pins = < | |
368 | VF610_PAD_PTB23__UART1_TX 0x21a2 | |
369 | VF610_PAD_PTB24__UART1_RX 0x21a1 | |
370 | >; | |
371 | }; | |
372 | }; |