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Squashed 'dts/upstream/' changes from aaba2d45dc2a..b35b9bd1d4ee
[thirdparty/u-boot.git] / src / arm / renesas / r8a7740.dtsi
CommitLineData
53633a89
TR		 1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Mobile A1 (R8A77400) SoC
4 *
5 * Copyright (C) 2012 Renesas Solutions Corp.
6 */
7
8#include <dt-bindings/clock/r8a7740-clock.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11
12/ {
13 compatible = "renesas,r8a7740";
14 interrupt-parent = <&gic>;
15 #address-cells = <1>;
16 #size-cells = <1>;
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21 cpu@0 {
22 compatible = "arm,cortex-a9";
23 device_type = "cpu";
24 reg = <0x0>;
25 clock-frequency = <800000000>;
26 power-domains = <&pd_a3sm>;
27 next-level-cache = <&L2>;
28 };
29 };
30
31 gic: interrupt-controller@c2800000 {
32 compatible = "arm,pl390";
33 #interrupt-cells = <3>;
34 interrupt-controller;
35 reg = <0xc2800000 0x1000>,
36 <0xc2000000 0x1000>;
37 };
38
39 L2: cache-controller@f0100000 {
40 compatible = "arm,pl310-cache";
41 reg = <0xf0100000 0x1000>;
42 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
43 power-domains = <&pd_a3sm>;
44 arm,data-latency = <3 3 3>;
45 arm,tag-latency = <2 2 2>;
46 arm,shared-override;
47 cache-unified;
48 cache-level = <2>;
49 };
50
51 dbsc3: memory-controller@fe400000 {
52 compatible = "renesas,dbsc3-r8a7740";
53 reg = <0xfe400000 0x400>;
54 power-domains = <&pd_a4s>;
55 };
56
57 pmu {
58 compatible = "arm,cortex-a9-pmu";
59 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
60 };
61
62 ptm {
63 compatible = "arm,coresight-etm3x";
64 power-domains = <&pd_d4>;
65 };
66
67 ceu0: ceu@fe910000 {
68 reg = <0xfe910000 0x3000>;
69 compatible = "renesas,r8a7740-ceu";
70 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
71 clocks = <&mstp1_clks R8A7740_CLK_CEU20>;
72 power-domains = <&pd_a4r>;
73 status = "disabled";
74 };
75
76 ceu1: ceu@fe914000 {
77 reg = <0xfe914000 0x3000>;
78 compatible = "renesas,r8a7740-ceu";
79 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
80 clocks = <&mstp1_clks R8A7740_CLK_CEU21>;
81 power-domains = <&pd_a4r>;
82 status = "disabled";
83 };
84
85 cmt1: timer@e6138000 {
86 compatible = "renesas,r8a7740-cmt1";
87 reg = <0xe6138000 0x170>;
88 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
89 clocks = <&mstp3_clks R8A7740_CLK_CMT1>;
90 clock-names = "fck";
91 power-domains = <&pd_c5>;
92 status = "disabled";
93 };
94
95 /* irqpin0: IRQ0 - IRQ7 */
96 irqpin0: interrupt-controller@e6900000 {
97 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
98 #interrupt-cells = <2>;
99 interrupt-controller;
100 reg = <0xe6900000 4>,
101 <0xe6900010 4>,
102 <0xe6900020 1>,
103 <0xe6900040 1>,
104 <0xe6900060 1>;
105 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
106 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
107 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
108 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
109 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
110 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
111 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
112 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
113 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
114 power-domains = <&pd_a4s>;
115 };
116
117 /* irqpin1: IRQ8 - IRQ15 */
118 irqpin1: interrupt-controller@e6900004 {
119 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
120 #interrupt-cells = <2>;
121 interrupt-controller;
122 reg = <0xe6900004 4>,
123 <0xe6900014 4>,
124 <0xe6900024 1>,
125 <0xe6900044 1>,
126 <0xe6900064 1>;
127 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
128 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
129 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
130 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
131 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
132 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
133 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
134 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
135 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
136 power-domains = <&pd_a4s>;
137 };
138
139 /* irqpin2: IRQ16 - IRQ23 */
140 irqpin2: interrupt-controller@e6900008 {
141 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
142 #interrupt-cells = <2>;
143 interrupt-controller;
144 reg = <0xe6900008 4>,
145 <0xe6900018 4>,
146 <0xe6900028 1>,
147 <0xe6900048 1>,
148 <0xe6900068 1>;
149 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
151 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
152 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
153 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
154 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
155 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
156 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
157 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
158 power-domains = <&pd_a4s>;
159 };
160
161 /* irqpin3: IRQ24 - IRQ31 */
162 irqpin3: interrupt-controller@e690000c {
163 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
164 #interrupt-cells = <2>;
165 interrupt-controller;
166 reg = <0xe690000c 4>,
167 <0xe690001c 4>,
168 <0xe690002c 1>,
169 <0xe690004c 1>,
170 <0xe690006c 1>;
171 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
173 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
174 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
176 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
177 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
178 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
179 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
180 power-domains = <&pd_a4s>;
181 };
182
183 ether: ethernet@e9a00000 {
184 compatible = "renesas,gether-r8a7740";
185 reg = <0xe9a00000 0x800>,
186 <0xe9a01800 0x800>;
187 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
188 clocks = <&mstp3_clks R8A7740_CLK_GETHER>;
189 power-domains = <&pd_a4s>;
190 phy-mode = "mii";
191 #address-cells = <1>;
192 #size-cells = <0>;
193 status = "disabled";
194 };
195
196 i2c0: i2c@fff20000 {
197 #address-cells = <1>;
198 #size-cells = <0>;
199 compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
200 reg = <0xfff20000 0x425>;
201 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
202 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
203 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
204 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
205 clocks = <&mstp1_clks R8A7740_CLK_IIC0>;
206 power-domains = <&pd_a4r>;
207 status = "disabled";
208 };
209
210 i2c1: i2c@e6c20000 {
211 #address-cells = <1>;
212 #size-cells = <0>;
213 compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
214 reg = <0xe6c20000 0x425>;
215 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&mstp3_clks R8A7740_CLK_IIC1>;
220 power-domains = <&pd_a3sp>;
221 status = "disabled";
222 };
223
224 scifa0: serial@e6c40000 {
225 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
226 reg = <0xe6c40000 0x100>;
227 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
228 clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>;
229 clock-names = "fck";
230 power-domains = <&pd_a3sp>;
231 status = "disabled";
232 };
233
234 scifa1: serial@e6c50000 {
235 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
236 reg = <0xe6c50000 0x100>;
237 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
238 clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>;
239 clock-names = "fck";
240 power-domains = <&pd_a3sp>;
241 status = "disabled";
242 };
243
244 scifa2: serial@e6c60000 {
245 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
246 reg = <0xe6c60000 0x100>;
247 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
248 clocks = <&mstp2_clks R8A7740_CLK_SCIFA2>;
249 clock-names = "fck";
250 power-domains = <&pd_a3sp>;
251 status = "disabled";
252 };
253
254 scifa3: serial@e6c70000 {
255 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
256 reg = <0xe6c70000 0x100>;
257 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
258 clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>;
259 clock-names = "fck";
260 power-domains = <&pd_a3sp>;
261 status = "disabled";
262 };
263
264 scifa4: serial@e6c80000 {
265 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
266 reg = <0xe6c80000 0x100>;
267 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
268 clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>;
269 clock-names = "fck";
270 power-domains = <&pd_a3sp>;
271 status = "disabled";
272 };
273
274 scifa5: serial@e6cb0000 {
275 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
276 reg = <0xe6cb0000 0x100>;
277 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
278 clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>;
279 clock-names = "fck";
280 power-domains = <&pd_a3sp>;
281 status = "disabled";
282 };
283
284 scifa6: serial@e6cc0000 {
285 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
286 reg = <0xe6cc0000 0x100>;
287 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>;
289 clock-names = "fck";
290 power-domains = <&pd_a3sp>;
291 status = "disabled";
292 };
293
294 scifa7: serial@e6cd0000 {
295 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
296 reg = <0xe6cd0000 0x100>;
297 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
298 clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>;
299 clock-names = "fck";
300 power-domains = <&pd_a3sp>;
301 status = "disabled";
302 };
303
304 scifb: serial@e6c30000 {
305 compatible = "renesas,scifb-r8a7740", "renesas,scifb";
306 reg = <0xe6c30000 0x100>;
307 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
308 clocks = <&mstp2_clks R8A7740_CLK_SCIFB>;
309 clock-names = "fck";
310 power-domains = <&pd_a3sp>;
311 status = "disabled";
312 };
313
314 pfc: pinctrl@e6050000 {
315 compatible = "renesas,pfc-r8a7740";
316 reg = <0xe6050000 0x8000>,
317 <0xe605800c 0x20>;
318 gpio-controller;
319 #gpio-cells = <2>;
320 gpio-ranges = <&pfc 0 0 212>;
321 interrupts-extended =
322 <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
323 <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
324 <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
325 <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
326 <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
327 <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
328 <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
329 <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
330 power-domains = <&pd_c5>;
331 };
332
333 tpu: pwm@e6600000 {
334 compatible = "renesas,tpu-r8a7740", "renesas,tpu";
335 reg = <0xe6600000 0x148>;
336 clocks = <&mstp3_clks R8A7740_CLK_TPU0>;
337 power-domains = <&pd_a3sp>;
338 status = "disabled";
339 #pwm-cells = <3>;
340 };
341
342 mmcif0: mmc@e6bd0000 {
343 compatible = "renesas,mmcif-r8a7740", "renesas,sh-mmcif";
344 reg = <0xe6bd0000 0x100>;
345 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
346 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
347 clocks = <&mstp3_clks R8A7740_CLK_MMC>;
348 power-domains = <&pd_a3sp>;
349 status = "disabled";
350 };
351
352 sdhi0: mmc@e6850000 {
353 compatible = "renesas,sdhi-r8a7740";
354 reg = <0xe6850000 0x100>;
355 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
356 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
357 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
358 clocks = <&mstp3_clks R8A7740_CLK_SDHI0>;
359 power-domains = <&pd_a3sp>;
360 cap-sd-highspeed;
361 cap-sdio-irq;
362 status = "disabled";
363 };
364
365 sdhi1: mmc@e6860000 {
366 compatible = "renesas,sdhi-r8a7740";
367 reg = <0xe6860000 0x100>;
368 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
369 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
370 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&mstp3_clks R8A7740_CLK_SDHI1>;
372 power-domains = <&pd_a3sp>;
373 cap-sd-highspeed;
374 cap-sdio-irq;
375 status = "disabled";
376 };
377
378 sdhi2: mmc@e6870000 {
379 compatible = "renesas,sdhi-r8a7740";
380 reg = <0xe6870000 0x100>;
381 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
382 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
383 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
384 clocks = <&mstp4_clks R8A7740_CLK_SDHI2>;
385 power-domains = <&pd_a3sp>;
386 cap-sd-highspeed;
387 cap-sdio-irq;
388 status = "disabled";
389 };
390
391 sh_fsi2: sound@fe1f0000 {
392 #sound-dai-cells = <1>;
393 compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2";
394 reg = <0xfe1f0000 0x400>;
395 interrupts = <GIC_SPI 9 0x4>;
396 clocks = <&mstp3_clks R8A7740_CLK_FSI>;
397 power-domains = <&pd_a4mp>;
398 status = "disabled";
399 };
400
93743d24
TR		 401 lcdc0: lcd-controller@fe940000 {
402 compatible = "renesas,r8a7740-lcdc";
403 reg = <0xfe940000 0x4000>;
404 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
405 clocks = <&mstp1_clks R8A7740_CLK_LCDC0>,
406 <&cpg_clocks R8A7740_CLK_M3>, <&lcdlclk0_clk>,
407 <&vou_clk>;
408 clock-names = "fck", "media", "lclk", "video";
409 power-domains = <&pd_a4lc>;
410 status = "disabled";
411
412 ports {
413 #address-cells = <1>;
414 #size-cells = <0>;
415
416 port@0 {
417 reg = <0>;
418
419 lcdc0_rgb: endpoint {
420 };
421 };
422 };
423 };
424
425 lcdc1: lcd-controller@fe944000 {
426 compatible = "renesas,r8a7740-lcdc";
427 reg = <0xfe944000 0x4000>;
428 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
429 clocks = <&mstp1_clks R8A7740_CLK_LCDC1>,
430 <&cpg_clocks R8A7740_CLK_M3>, <&lcdlclk1_clk>,
431 <&vou_clk>;
432 clock-names = "fck", "media", "lclk", "video";
433 power-domains = <&pd_a4lc>;
434 status = "disabled";
435
436 ports {
437 #address-cells = <1>;
438 #size-cells = <0>;
439
440 port@0 {
441 reg = <0>;
442
443 lcdc1_rgb: endpoint {
444 };
445 };
446
447 port@1 {
448 reg = <1>;
449
450 lcdc1_hdmi: endpoint {
451 };
452 };
453 };
454 };
455
53633a89
TR		 456 tmu0: timer@fff80000 {
457 compatible = "renesas,tmu-r8a7740", "renesas,tmu";
458 reg = <0xfff80000 0x2c>;
459 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
460 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
461 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
462 clocks = <&mstp1_clks R8A7740_CLK_TMU0>;
463 clock-names = "fck";
464 power-domains = <&pd_a4r>;
465
466 #renesas,channels = <3>;
467
468 status = "disabled";
469 };
470
471 tmu1: timer@fff90000 {
472 compatible = "renesas,tmu-r8a7740", "renesas,tmu";
473 reg = <0xfff90000 0x2c>;
474 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
475 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
476 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
477 clocks = <&mstp1_clks R8A7740_CLK_TMU1>;
478 clock-names = "fck";
479 power-domains = <&pd_a4r>;
480
481 #renesas,channels = <3>;
482
483 status = "disabled";
484 };
485
486 clocks {
487 #address-cells = <1>;
488 #size-cells = <1>;
489 ranges;
490
491 /* External root clock */
492 extalr_clk: extalr {
493 compatible = "fixed-clock";
494 #clock-cells = <0>;
495 clock-frequency = <32768>;
496 };
497 extal1_clk: extal1 {
498 compatible = "fixed-clock";
499 #clock-cells = <0>;
500 clock-frequency = <0>;
501 };
502 extal2_clk: extal2 {
503 compatible = "fixed-clock";
504 #clock-cells = <0>;
505 clock-frequency = <0>;
506 };
507 dv_clk: dv {
508 compatible = "fixed-clock";
509 #clock-cells = <0>;
510 clock-frequency = <27000000>;
511 };
512 fmsick_clk: fmsick {
513 compatible = "fixed-clock";
514 #clock-cells = <0>;
515 clock-frequency = <0>;
516 };
517 fmsock_clk: fmsock {
518 compatible = "fixed-clock";
519 #clock-cells = <0>;
520 clock-frequency = <0>;
521 };
522 fsiack_clk: fsiack {
523 compatible = "fixed-clock";
524 #clock-cells = <0>;
525 clock-frequency = <0>;
526 };
527 fsibck_clk: fsibck {
528 compatible = "fixed-clock";
529 #clock-cells = <0>;
530 clock-frequency = <0>;
531 };
93743d24
TR		 532 lcdlclk0_clk: lcdlclk0 {
533 compatible = "fixed-clock";
534 #clock-cells = <0>;
535 clock-frequency = <0>;
536 };
537 lcdlclk1_clk: lcdlclk1 {
538 compatible = "fixed-clock";
539 #clock-cells = <0>;
540 clock-frequency = <0>;
541 };
53633a89
TR		 542
543 /* Special CPG clocks */
544 cpg_clocks: cpg_clocks@e6150000 {
545 compatible = "renesas,r8a7740-cpg-clocks";
546 reg = <0xe6150000 0x10000>;
547 clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>;
548 #clock-cells = <1>;
549 clock-output-names = "system", "pllc0", "pllc1",
550 "pllc2", "r",
551 "usb24s",
552 "i", "zg", "b", "m1", "hp",
553 "hpp", "usbp", "s", "zb", "m3",
554 "cp";
555 };
556
557 /* Variable factor clocks (DIV6) */
558 vclk1_clk: vclk1@e6150008 {
559 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
560 reg = <0xe6150008 4>;
561 clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,
562 <&cpg_clocks R8A7740_CLK_USB24S>,
563 <&extal1_div2_clk>, <&extalr_clk>, <0>,
564 <0>;
565 #clock-cells = <0>;
566 };
567 vclk2_clk: vclk2@e615000c {
568 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
569 reg = <0xe615000c 4>;
570 clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,
571 <&cpg_clocks R8A7740_CLK_USB24S>,
572 <&extal1_div2_clk>, <&extalr_clk>, <0>,
573 <0>;
574 #clock-cells = <0>;
575 };
576 fmsi_clk: fmsi@e6150010 {
577 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
578 reg = <0xe6150010 4>;
579 clocks = <&pllc1_div2_clk>, <&fmsick_clk>, <0>, <0>;
580 #clock-cells = <0>;
581 };
582 fmso_clk: fmso@e6150014 {
583 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
584 reg = <0xe6150014 4>;
585 clocks = <&pllc1_div2_clk>, <&fmsock_clk>, <0>, <0>;
586 #clock-cells = <0>;
587 };
588 fsia_clk: fsia@e6150018 {
589 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
590 reg = <0xe6150018 4>;
591 clocks = <&pllc1_div2_clk>, <&fsiack_clk>, <0>, <0>;
592 #clock-cells = <0>;
593 };
594 sub_clk: sub@e6150080 {
595 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
596 reg = <0xe6150080 4>;
597 clocks = <&pllc1_div2_clk>,
598 <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>;
599 #clock-cells = <0>;
600 };
601 spu_clk: spu@e6150084 {
602 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
603 reg = <0xe6150084 4>;
604 clocks = <&pllc1_div2_clk>,
605 <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>;
606 #clock-cells = <0>;
607 };
608 vou_clk: vou@e6150088 {
609 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
610 reg = <0xe6150088 4>;
611 clocks = <&pllc1_div2_clk>, <&extal1_clk>, <&dv_clk>,
612 <0>;
613 #clock-cells = <0>;
614 };
615 stpro_clk: stpro@e615009c {
616 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
617 reg = <0xe615009c 4>;
618 clocks = <&cpg_clocks R8A7740_CLK_PLLC0>;
619 #clock-cells = <0>;
620 };
621
622 /* Fixed factor clocks */
623 pllc1_div2_clk: pllc1_div2 {
624 compatible = "fixed-factor-clock";
625 clocks = <&cpg_clocks R8A7740_CLK_PLLC1>;
626 #clock-cells = <0>;
627 clock-div = <2>;
628 clock-mult = <1>;
629 };
630 extal1_div2_clk: extal1_div2 {
631 compatible = "fixed-factor-clock";
632 clocks = <&extal1_clk>;
633 #clock-cells = <0>;
634 clock-div = <2>;
635 clock-mult = <1>;
636 };
637
638 /* Gate clocks */
639 subck_clks: subck_clks@e6150080 {
640 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
641 reg = <0xe6150080 4>;
642 clocks = <&sub_clk>, <&sub_clk>;
643 #clock-cells = <1>;
644 clock-indices = <
645 R8A7740_CLK_SUBCK R8A7740_CLK_SUBCK2
646 >;
647 clock-output-names =
648 "subck", "subck2";
649 };
650 mstp1_clks: mstp1_clks@e6150134 {
651 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
652 reg = <0xe6150134 4>, <0xe6150038 4>;
653 clocks = <&cpg_clocks R8A7740_CLK_S>,
654 <&cpg_clocks R8A7740_CLK_S>, <&sub_clk>,
655 <&cpg_clocks R8A7740_CLK_B>,
656 <&cpg_clocks R8A7740_CLK_HPP>, <&sub_clk>,
657 <&cpg_clocks R8A7740_CLK_B>;
658 #clock-cells = <1>;
659 clock-indices = <
660 R8A7740_CLK_CEU21 R8A7740_CLK_CEU20 R8A7740_CLK_TMU0
661 R8A7740_CLK_LCDC1 R8A7740_CLK_IIC0 R8A7740_CLK_TMU1
662 R8A7740_CLK_LCDC0
663 >;
664 clock-output-names =
665 "ceu21", "ceu20", "tmu0", "lcdc1", "iic0",
666 "tmu1", "lcdc0";
667 };
668 mstp2_clks: mstp2_clks@e6150138 {
669 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
670 reg = <0xe6150138 4>, <0xe6150040 4>;
671 clocks = <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>,
672 <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>,
673 <&cpg_clocks R8A7740_CLK_HP>,
674 <&cpg_clocks R8A7740_CLK_HP>,
675 <&cpg_clocks R8A7740_CLK_HP>,
676 <&sub_clk>, <&sub_clk>, <&sub_clk>,
677 <&sub_clk>, <&sub_clk>, <&sub_clk>,
678 <&sub_clk>;
679 #clock-cells = <1>;
680 clock-indices = <
681 R8A7740_CLK_SCIFA6 R8A7740_CLK_INTCA
682 R8A7740_CLK_SCIFA7
683 R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2
684 R8A7740_CLK_DMAC3 R8A7740_CLK_USBDMAC
685 R8A7740_CLK_SCIFA5 R8A7740_CLK_SCIFB
686 R8A7740_CLK_SCIFA0 R8A7740_CLK_SCIFA1
687 R8A7740_CLK_SCIFA2 R8A7740_CLK_SCIFA3
688 R8A7740_CLK_SCIFA4
689 >;
690 clock-output-names =
691 "scifa6", "intca",
692 "scifa7", "dmac1", "dmac2", "dmac3",
693 "usbdmac", "scifa5", "scifb", "scifa0", "scifa1",
694 "scifa2", "scifa3", "scifa4";
695 };
696 mstp3_clks: mstp3_clks@e615013c {
697 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
698 reg = <0xe615013c 4>, <0xe6150048 4>;
699 clocks = <&cpg_clocks R8A7740_CLK_R>,
700 <&cpg_clocks R8A7740_CLK_HP>,
701 <&sub_clk>,
702 <&cpg_clocks R8A7740_CLK_HP>,
703 <&cpg_clocks R8A7740_CLK_HP>,
704 <&cpg_clocks R8A7740_CLK_HP>,
705 <&cpg_clocks R8A7740_CLK_HP>,
706 <&cpg_clocks R8A7740_CLK_HP>,
707 <&cpg_clocks R8A7740_CLK_HP>;
708 #clock-cells = <1>;
709 clock-indices = <
710 R8A7740_CLK_CMT1 R8A7740_CLK_FSI R8A7740_CLK_IIC1
711 R8A7740_CLK_USBF R8A7740_CLK_SDHI0 R8A7740_CLK_SDHI1
712 R8A7740_CLK_MMC R8A7740_CLK_GETHER R8A7740_CLK_TPU0
713 >;
714 clock-output-names =
715 "cmt1", "fsi", "iic1", "usbf", "sdhi0", "sdhi1",
716 "mmc", "gether", "tpu0";
717 };
718 mstp4_clks: mstp4_clks@e6150140 {
719 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
720 reg = <0xe6150140 4>, <0xe615004c 4>;
721 clocks = <&cpg_clocks R8A7740_CLK_HP>,
722 <&cpg_clocks R8A7740_CLK_HP>,
723 <&cpg_clocks R8A7740_CLK_HP>,
724 <&cpg_clocks R8A7740_CLK_HP>;
725 #clock-cells = <1>;
726 clock-indices = <
727 R8A7740_CLK_USBH R8A7740_CLK_SDHI2
728 R8A7740_CLK_USBFUNC R8A7740_CLK_USBPHY
729 >;
730 clock-output-names =
731 "usbhost", "sdhi2", "usbfunc", "usphy";
732 };
733 };
734
735 sysc: system-controller@e6180000 {
736 compatible = "renesas,sysc-r8a7740", "renesas,sysc-rmobile";
737 reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
738
739 pm-domains {
740 pd_c5: c5 {
741 #address-cells = <1>;
742 #size-cells = <0>;
743 #power-domain-cells = <0>;
744
745 pd_a4lc: a4lc@1 {
746 reg = <1>;
747 #power-domain-cells = <0>;
748 };
749
750 pd_a4mp: a4mp@2 {
751 reg = <2>;
752 #power-domain-cells = <0>;
753 };
754
755 pd_d4: d4@3 {
756 reg = <3>;
757 #power-domain-cells = <0>;
758 };
759
760 pd_a4r: a4r@5 {
761 reg = <5>;
762 #address-cells = <1>;
763 #size-cells = <0>;
764 #power-domain-cells = <0>;
765
766 pd_a3rv: a3rv@6 {
767 reg = <6>;
768 #power-domain-cells = <0>;
769 };
770 };
771
772 pd_a4s: a4s@10 {
773 reg = <10>;
774 #address-cells = <1>;
775 #size-cells = <0>;
776 #power-domain-cells = <0>;
777
778 pd_a3sp: a3sp@11 {
779 reg = <11>;
780 #power-domain-cells = <0>;
781 };
782
783 pd_a3sm: a3sm@12 {
784 reg = <12>;
785 #power-domain-cells = <0>;
786 };
787
788 pd_a3sg: a3sg@13 {
789 reg = <13>;
790 #power-domain-cells = <0>;
791 };
792 };
793
794 pd_a4su: a4su@20 {
795 reg = <20>;
796 #power-domain-cells = <0>;
797 };
798 };
799 };
800 };
801};
"Das U-Boot" Source Tree