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53633a89 TR |
1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
2 | /* | |
3 | * Copyright (c) 2013 MundoReader S.L. | |
4 | * Author: Heiko Stuebner <heiko@sntech.de> | |
5 | */ | |
6 | ||
7 | #include <dt-bindings/gpio/gpio.h> | |
8 | #include <dt-bindings/pinctrl/rockchip.h> | |
9 | #include <dt-bindings/clock/rk3066a-cru.h> | |
10 | #include <dt-bindings/power/rk3066-power.h> | |
11 | #include "rk3xxx.dtsi" | |
12 | ||
13 | / { | |
14 | compatible = "rockchip,rk3066a"; | |
15 | ||
93743d24 TR |
16 | aliases { |
17 | gpio4 = &gpio4; | |
18 | gpio6 = &gpio6; | |
19 | }; | |
20 | ||
53633a89 TR |
21 | cpus { |
22 | #address-cells = <1>; | |
23 | #size-cells = <0>; | |
24 | enable-method = "rockchip,rk3066-smp"; | |
25 | ||
26 | cpu0: cpu@0 { | |
27 | device_type = "cpu"; | |
28 | compatible = "arm,cortex-a9"; | |
29 | next-level-cache = <&L2>; | |
30 | reg = <0x0>; | |
31 | operating-points = | |
32 | /* kHz uV */ | |
33 | <1416000 1300000>, | |
34 | <1200000 1175000>, | |
35 | <1008000 1125000>, | |
36 | <816000 1125000>, | |
37 | <600000 1100000>, | |
38 | <504000 1100000>, | |
39 | <312000 1075000>; | |
40 | clock-latency = <40000>; | |
41 | clocks = <&cru ARMCLK>; | |
42 | }; | |
43 | cpu1: cpu@1 { | |
44 | device_type = "cpu"; | |
45 | compatible = "arm,cortex-a9"; | |
46 | next-level-cache = <&L2>; | |
47 | reg = <0x1>; | |
48 | }; | |
49 | }; | |
50 | ||
51 | display-subsystem { | |
52 | compatible = "rockchip,display-subsystem"; | |
53 | ports = <&vop0_out>, <&vop1_out>; | |
54 | }; | |
55 | ||
56 | sram: sram@10080000 { | |
57 | compatible = "mmio-sram"; | |
58 | reg = <0x10080000 0x10000>; | |
59 | #address-cells = <1>; | |
60 | #size-cells = <1>; | |
61 | ranges = <0 0x10080000 0x10000>; | |
62 | ||
63 | smp-sram@0 { | |
64 | compatible = "rockchip,rk3066-smp-sram"; | |
65 | reg = <0x0 0x50>; | |
66 | }; | |
67 | }; | |
68 | ||
69 | vop0: vop@1010c000 { | |
70 | compatible = "rockchip,rk3066-vop"; | |
71 | reg = <0x1010c000 0x19c>; | |
72 | interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; | |
73 | clocks = <&cru ACLK_LCDC0>, | |
74 | <&cru DCLK_LCDC0>, | |
75 | <&cru HCLK_LCDC0>; | |
76 | clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; | |
77 | power-domains = <&power RK3066_PD_VIO>; | |
78 | resets = <&cru SRST_LCDC0_AXI>, | |
79 | <&cru SRST_LCDC0_AHB>, | |
80 | <&cru SRST_LCDC0_DCLK>; | |
81 | reset-names = "axi", "ahb", "dclk"; | |
82 | status = "disabled"; | |
83 | ||
84 | vop0_out: port { | |
85 | #address-cells = <1>; | |
86 | #size-cells = <0>; | |
87 | ||
88 | vop0_out_hdmi: endpoint@0 { | |
89 | reg = <0>; | |
90 | remote-endpoint = <&hdmi_in_vop0>; | |
91 | }; | |
92 | }; | |
93 | }; | |
94 | ||
95 | vop1: vop@1010e000 { | |
96 | compatible = "rockchip,rk3066-vop"; | |
97 | reg = <0x1010e000 0x19c>; | |
98 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; | |
99 | clocks = <&cru ACLK_LCDC1>, | |
100 | <&cru DCLK_LCDC1>, | |
101 | <&cru HCLK_LCDC1>; | |
102 | clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; | |
103 | power-domains = <&power RK3066_PD_VIO>; | |
104 | resets = <&cru SRST_LCDC1_AXI>, | |
105 | <&cru SRST_LCDC1_AHB>, | |
106 | <&cru SRST_LCDC1_DCLK>; | |
107 | reset-names = "axi", "ahb", "dclk"; | |
108 | status = "disabled"; | |
109 | ||
110 | vop1_out: port { | |
111 | #address-cells = <1>; | |
112 | #size-cells = <0>; | |
113 | ||
114 | vop1_out_hdmi: endpoint@0 { | |
115 | reg = <0>; | |
116 | remote-endpoint = <&hdmi_in_vop1>; | |
117 | }; | |
118 | }; | |
119 | }; | |
120 | ||
121 | hdmi: hdmi@10116000 { | |
122 | compatible = "rockchip,rk3066-hdmi"; | |
123 | reg = <0x10116000 0x2000>; | |
124 | interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; | |
125 | clocks = <&cru HCLK_HDMI>; | |
126 | clock-names = "hclk"; | |
127 | pinctrl-names = "default"; | |
128 | pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>; | |
129 | power-domains = <&power RK3066_PD_VIO>; | |
130 | rockchip,grf = <&grf>; | |
131 | status = "disabled"; | |
132 | ||
133 | ports { | |
134 | #address-cells = <1>; | |
135 | #size-cells = <0>; | |
136 | ||
137 | hdmi_in: port@0 { | |
138 | reg = <0>; | |
139 | #address-cells = <1>; | |
140 | #size-cells = <0>; | |
141 | ||
142 | hdmi_in_vop0: endpoint@0 { | |
143 | reg = <0>; | |
144 | remote-endpoint = <&vop0_out_hdmi>; | |
145 | }; | |
146 | ||
147 | hdmi_in_vop1: endpoint@1 { | |
148 | reg = <1>; | |
149 | remote-endpoint = <&vop1_out_hdmi>; | |
150 | }; | |
151 | }; | |
152 | ||
153 | hdmi_out: port@1 { | |
154 | reg = <1>; | |
155 | }; | |
156 | }; | |
157 | }; | |
158 | ||
159 | i2s0: i2s@10118000 { | |
160 | compatible = "rockchip,rk3066-i2s"; | |
161 | reg = <0x10118000 0x2000>; | |
162 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; | |
163 | pinctrl-names = "default"; | |
164 | pinctrl-0 = <&i2s0_bus>; | |
165 | clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>; | |
166 | clock-names = "i2s_clk", "i2s_hclk"; | |
167 | dmas = <&dmac1_s 4>, <&dmac1_s 5>; | |
168 | dma-names = "tx", "rx"; | |
169 | rockchip,playback-channels = <8>; | |
170 | rockchip,capture-channels = <2>; | |
171 | #sound-dai-cells = <0>; | |
172 | status = "disabled"; | |
173 | }; | |
174 | ||
175 | i2s1: i2s@1011a000 { | |
176 | compatible = "rockchip,rk3066-i2s"; | |
177 | reg = <0x1011a000 0x2000>; | |
178 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; | |
179 | pinctrl-names = "default"; | |
180 | pinctrl-0 = <&i2s1_bus>; | |
181 | clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>; | |
182 | clock-names = "i2s_clk", "i2s_hclk"; | |
183 | dmas = <&dmac1_s 6>, <&dmac1_s 7>; | |
184 | dma-names = "tx", "rx"; | |
185 | rockchip,playback-channels = <2>; | |
186 | rockchip,capture-channels = <2>; | |
187 | #sound-dai-cells = <0>; | |
188 | status = "disabled"; | |
189 | }; | |
190 | ||
191 | i2s2: i2s@1011c000 { | |
192 | compatible = "rockchip,rk3066-i2s"; | |
193 | reg = <0x1011c000 0x2000>; | |
194 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | |
195 | pinctrl-names = "default"; | |
196 | pinctrl-0 = <&i2s2_bus>; | |
197 | clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>; | |
198 | clock-names = "i2s_clk", "i2s_hclk"; | |
199 | dmas = <&dmac1_s 9>, <&dmac1_s 10>; | |
200 | dma-names = "tx", "rx"; | |
201 | rockchip,playback-channels = <2>; | |
202 | rockchip,capture-channels = <2>; | |
203 | #sound-dai-cells = <0>; | |
204 | status = "disabled"; | |
205 | }; | |
206 | ||
207 | cru: clock-controller@20000000 { | |
208 | compatible = "rockchip,rk3066a-cru"; | |
209 | reg = <0x20000000 0x1000>; | |
210 | clocks = <&xin24m>; | |
211 | clock-names = "xin24m"; | |
212 | rockchip,grf = <&grf>; | |
213 | #clock-cells = <1>; | |
214 | #reset-cells = <1>; | |
215 | assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>, | |
216 | <&cru ACLK_CPU>, <&cru HCLK_CPU>, | |
217 | <&cru PCLK_CPU>, <&cru ACLK_PERI>, | |
218 | <&cru HCLK_PERI>, <&cru PCLK_PERI>; | |
219 | assigned-clock-rates = <400000000>, <594000000>, | |
220 | <300000000>, <150000000>, | |
221 | <75000000>, <300000000>, | |
222 | <150000000>, <75000000>; | |
223 | }; | |
224 | ||
225 | timer2: timer@2000e000 { | |
226 | compatible = "snps,dw-apb-timer"; | |
227 | reg = <0x2000e000 0x100>; | |
228 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; | |
229 | clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>; | |
230 | clock-names = "timer", "pclk"; | |
231 | }; | |
232 | ||
233 | efuse: efuse@20010000 { | |
234 | compatible = "rockchip,rk3066a-efuse"; | |
235 | reg = <0x20010000 0x4000>; | |
236 | #address-cells = <1>; | |
237 | #size-cells = <1>; | |
238 | clocks = <&cru PCLK_EFUSE>; | |
239 | clock-names = "pclk_efuse"; | |
240 | ||
241 | cpu_leakage: cpu_leakage@17 { | |
242 | reg = <0x17 0x1>; | |
243 | }; | |
244 | }; | |
245 | ||
246 | timer0: timer@20038000 { | |
247 | compatible = "snps,dw-apb-timer"; | |
248 | reg = <0x20038000 0x100>; | |
249 | interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; | |
250 | clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>; | |
251 | clock-names = "timer", "pclk"; | |
252 | }; | |
253 | ||
254 | timer1: timer@2003a000 { | |
255 | compatible = "snps,dw-apb-timer"; | |
256 | reg = <0x2003a000 0x100>; | |
257 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; | |
258 | clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>; | |
259 | clock-names = "timer", "pclk"; | |
260 | }; | |
261 | ||
262 | tsadc: tsadc@20060000 { | |
263 | compatible = "rockchip,rk3066-tsadc"; | |
264 | reg = <0x20060000 0x100>; | |
265 | clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; | |
266 | clock-names = "saradc", "apb_pclk"; | |
267 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; | |
268 | #io-channel-cells = <1>; | |
269 | resets = <&cru SRST_TSADC>; | |
270 | reset-names = "saradc-apb"; | |
271 | status = "disabled"; | |
272 | }; | |
273 | ||
274 | pinctrl: pinctrl { | |
275 | compatible = "rockchip,rk3066a-pinctrl"; | |
276 | rockchip,grf = <&grf>; | |
277 | #address-cells = <1>; | |
278 | #size-cells = <1>; | |
279 | ranges; | |
280 | ||
281 | gpio0: gpio@20034000 { | |
282 | compatible = "rockchip,gpio-bank"; | |
283 | reg = <0x20034000 0x100>; | |
284 | interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; | |
285 | clocks = <&cru PCLK_GPIO0>; | |
286 | ||
287 | gpio-controller; | |
288 | #gpio-cells = <2>; | |
289 | ||
290 | interrupt-controller; | |
291 | #interrupt-cells = <2>; | |
292 | }; | |
293 | ||
294 | gpio1: gpio@2003c000 { | |
295 | compatible = "rockchip,gpio-bank"; | |
296 | reg = <0x2003c000 0x100>; | |
297 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; | |
298 | clocks = <&cru PCLK_GPIO1>; | |
299 | ||
300 | gpio-controller; | |
301 | #gpio-cells = <2>; | |
302 | ||
303 | interrupt-controller; | |
304 | #interrupt-cells = <2>; | |
305 | }; | |
306 | ||
307 | gpio2: gpio@2003e000 { | |
308 | compatible = "rockchip,gpio-bank"; | |
309 | reg = <0x2003e000 0x100>; | |
310 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; | |
311 | clocks = <&cru PCLK_GPIO2>; | |
312 | ||
313 | gpio-controller; | |
314 | #gpio-cells = <2>; | |
315 | ||
316 | interrupt-controller; | |
317 | #interrupt-cells = <2>; | |
318 | }; | |
319 | ||
320 | gpio3: gpio@20080000 { | |
321 | compatible = "rockchip,gpio-bank"; | |
322 | reg = <0x20080000 0x100>; | |
323 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; | |
324 | clocks = <&cru PCLK_GPIO3>; | |
325 | ||
326 | gpio-controller; | |
327 | #gpio-cells = <2>; | |
328 | ||
329 | interrupt-controller; | |
330 | #interrupt-cells = <2>; | |
331 | }; | |
332 | ||
333 | gpio4: gpio@20084000 { | |
334 | compatible = "rockchip,gpio-bank"; | |
335 | reg = <0x20084000 0x100>; | |
336 | interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; | |
337 | clocks = <&cru PCLK_GPIO4>; | |
338 | ||
339 | gpio-controller; | |
340 | #gpio-cells = <2>; | |
341 | ||
342 | interrupt-controller; | |
343 | #interrupt-cells = <2>; | |
344 | }; | |
345 | ||
346 | gpio6: gpio@2000a000 { | |
347 | compatible = "rockchip,gpio-bank"; | |
348 | reg = <0x2000a000 0x100>; | |
349 | interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; | |
350 | clocks = <&cru PCLK_GPIO6>; | |
351 | ||
352 | gpio-controller; | |
353 | #gpio-cells = <2>; | |
354 | ||
355 | interrupt-controller; | |
356 | #interrupt-cells = <2>; | |
357 | }; | |
358 | ||
359 | pcfg_pull_default: pcfg-pull-default { | |
360 | bias-pull-pin-default; | |
361 | }; | |
362 | ||
363 | pcfg_pull_none: pcfg-pull-none { | |
364 | bias-disable; | |
365 | }; | |
366 | ||
367 | emac { | |
368 | emac_xfer: emac-xfer { | |
369 | rockchip,pins = <1 RK_PC0 2 &pcfg_pull_none>, /* mac_clk */ | |
370 | <1 RK_PC1 2 &pcfg_pull_none>, /* tx_en */ | |
371 | <1 RK_PC2 2 &pcfg_pull_none>, /* txd1 */ | |
372 | <1 RK_PC3 2 &pcfg_pull_none>, /* txd0 */ | |
373 | <1 RK_PC4 2 &pcfg_pull_none>, /* rx_err */ | |
374 | <1 RK_PC5 2 &pcfg_pull_none>, /* crs_dvalid */ | |
375 | <1 RK_PC6 2 &pcfg_pull_none>, /* rxd1 */ | |
376 | <1 RK_PC7 2 &pcfg_pull_none>; /* rxd0 */ | |
377 | }; | |
378 | ||
379 | emac_mdio: emac-mdio { | |
380 | rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, /* mac_md */ | |
381 | <1 RK_PD1 2 &pcfg_pull_none>; /* mac_mdclk */ | |
382 | }; | |
383 | }; | |
384 | ||
385 | emmc { | |
386 | emmc_clk: emmc-clk { | |
387 | rockchip,pins = <3 RK_PD7 2 &pcfg_pull_default>; | |
388 | }; | |
389 | ||
390 | emmc_cmd: emmc-cmd { | |
391 | rockchip,pins = <4 RK_PB1 2 &pcfg_pull_default>; | |
392 | }; | |
393 | ||
394 | emmc_rst: emmc-rst { | |
395 | rockchip,pins = <4 RK_PB2 2 &pcfg_pull_default>; | |
396 | }; | |
397 | ||
398 | /* | |
399 | * The data pins are shared between nandc and emmc and | |
400 | * not accessible through pinctrl. Also they should've | |
401 | * been already set correctly by firmware, as | |
402 | * flash/emmc is the boot-device. | |
403 | */ | |
404 | }; | |
405 | ||
406 | hdmi { | |
407 | hdmi_hpd: hdmi-hpd { | |
408 | rockchip,pins = <0 RK_PA0 1 &pcfg_pull_default>; | |
409 | }; | |
410 | ||
411 | hdmii2c_xfer: hdmii2c-xfer { | |
412 | rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>, | |
413 | <0 RK_PA2 1 &pcfg_pull_none>; | |
414 | }; | |
415 | }; | |
416 | ||
417 | i2c0 { | |
418 | i2c0_xfer: i2c0-xfer { | |
419 | rockchip,pins = <2 RK_PD4 1 &pcfg_pull_none>, | |
420 | <2 RK_PD5 1 &pcfg_pull_none>; | |
421 | }; | |
422 | }; | |
423 | ||
424 | i2c1 { | |
425 | i2c1_xfer: i2c1-xfer { | |
426 | rockchip,pins = <2 RK_PD6 1 &pcfg_pull_none>, | |
427 | <2 RK_PD7 1 &pcfg_pull_none>; | |
428 | }; | |
429 | }; | |
430 | ||
431 | i2c2 { | |
432 | i2c2_xfer: i2c2-xfer { | |
433 | rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none>, | |
434 | <3 RK_PA1 1 &pcfg_pull_none>; | |
435 | }; | |
436 | }; | |
437 | ||
438 | i2c3 { | |
439 | i2c3_xfer: i2c3-xfer { | |
440 | rockchip,pins = <3 RK_PA2 2 &pcfg_pull_none>, | |
441 | <3 RK_PA3 2 &pcfg_pull_none>; | |
442 | }; | |
443 | }; | |
444 | ||
445 | i2c4 { | |
446 | i2c4_xfer: i2c4-xfer { | |
447 | rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>, | |
448 | <3 RK_PA5 1 &pcfg_pull_none>; | |
449 | }; | |
450 | }; | |
451 | ||
452 | pwm0 { | |
453 | pwm0_out: pwm0-out { | |
454 | rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; | |
455 | }; | |
456 | }; | |
457 | ||
458 | pwm1 { | |
459 | pwm1_out: pwm1-out { | |
460 | rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>; | |
461 | }; | |
462 | }; | |
463 | ||
464 | pwm2 { | |
465 | pwm2_out: pwm2-out { | |
466 | rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>; | |
467 | }; | |
468 | }; | |
469 | ||
470 | pwm3 { | |
471 | pwm3_out: pwm3-out { | |
472 | rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>; | |
473 | }; | |
474 | }; | |
475 | ||
476 | spi0 { | |
477 | spi0_clk: spi0-clk { | |
478 | rockchip,pins = <1 RK_PA5 2 &pcfg_pull_default>; | |
479 | }; | |
480 | spi0_cs0: spi0-cs0 { | |
481 | rockchip,pins = <1 RK_PA4 2 &pcfg_pull_default>; | |
482 | }; | |
483 | spi0_tx: spi0-tx { | |
484 | rockchip,pins = <1 RK_PA7 2 &pcfg_pull_default>; | |
485 | }; | |
486 | spi0_rx: spi0-rx { | |
487 | rockchip,pins = <1 RK_PA6 2 &pcfg_pull_default>; | |
488 | }; | |
489 | spi0_cs1: spi0-cs1 { | |
490 | rockchip,pins = <4 RK_PB7 1 &pcfg_pull_default>; | |
491 | }; | |
492 | }; | |
493 | ||
494 | spi1 { | |
495 | spi1_clk: spi1-clk { | |
496 | rockchip,pins = <2 RK_PC3 2 &pcfg_pull_default>; | |
497 | }; | |
498 | spi1_cs0: spi1-cs0 { | |
499 | rockchip,pins = <2 RK_PC4 2 &pcfg_pull_default>; | |
500 | }; | |
501 | spi1_rx: spi1-rx { | |
502 | rockchip,pins = <2 RK_PC6 2 &pcfg_pull_default>; | |
503 | }; | |
504 | spi1_tx: spi1-tx { | |
505 | rockchip,pins = <2 RK_PC5 2 &pcfg_pull_default>; | |
506 | }; | |
507 | spi1_cs1: spi1-cs1 { | |
508 | rockchip,pins = <2 RK_PC7 2 &pcfg_pull_default>; | |
509 | }; | |
510 | }; | |
511 | ||
512 | uart0 { | |
513 | uart0_xfer: uart0-xfer { | |
514 | rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>, | |
515 | <1 RK_PA1 1 &pcfg_pull_default>; | |
516 | }; | |
517 | ||
518 | uart0_cts: uart0-cts { | |
519 | rockchip,pins = <1 RK_PA2 1 &pcfg_pull_default>; | |
520 | }; | |
521 | ||
522 | uart0_rts: uart0-rts { | |
523 | rockchip,pins = <1 RK_PA3 1 &pcfg_pull_default>; | |
524 | }; | |
525 | }; | |
526 | ||
527 | uart1 { | |
528 | uart1_xfer: uart1-xfer { | |
529 | rockchip,pins = <1 RK_PA4 1 &pcfg_pull_default>, | |
530 | <1 RK_PA5 1 &pcfg_pull_default>; | |
531 | }; | |
532 | ||
533 | uart1_cts: uart1-cts { | |
534 | rockchip,pins = <1 RK_PA6 1 &pcfg_pull_default>; | |
535 | }; | |
536 | ||
537 | uart1_rts: uart1-rts { | |
538 | rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>; | |
539 | }; | |
540 | }; | |
541 | ||
542 | uart2 { | |
543 | uart2_xfer: uart2-xfer { | |
544 | rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>, | |
545 | <1 RK_PB1 1 &pcfg_pull_default>; | |
546 | }; | |
547 | /* no rts / cts for uart2 */ | |
548 | }; | |
549 | ||
550 | uart3 { | |
551 | uart3_xfer: uart3-xfer { | |
552 | rockchip,pins = <3 RK_PD3 1 &pcfg_pull_default>, | |
553 | <3 RK_PD4 1 &pcfg_pull_default>; | |
554 | }; | |
555 | ||
556 | uart3_cts: uart3-cts { | |
557 | rockchip,pins = <3 RK_PD5 1 &pcfg_pull_default>; | |
558 | }; | |
559 | ||
560 | uart3_rts: uart3-rts { | |
561 | rockchip,pins = <3 RK_PD6 1 &pcfg_pull_default>; | |
562 | }; | |
563 | }; | |
564 | ||
565 | sd0 { | |
566 | sd0_clk: sd0-clk { | |
567 | rockchip,pins = <3 RK_PB0 1 &pcfg_pull_default>; | |
568 | }; | |
569 | ||
570 | sd0_cmd: sd0-cmd { | |
571 | rockchip,pins = <3 RK_PB1 1 &pcfg_pull_default>; | |
572 | }; | |
573 | ||
574 | sd0_cd: sd0-cd { | |
575 | rockchip,pins = <3 RK_PB6 1 &pcfg_pull_default>; | |
576 | }; | |
577 | ||
578 | sd0_wp: sd0-wp { | |
579 | rockchip,pins = <3 RK_PB7 1 &pcfg_pull_default>; | |
580 | }; | |
581 | ||
582 | sd0_bus1: sd0-bus-width1 { | |
583 | rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>; | |
584 | }; | |
585 | ||
586 | sd0_bus4: sd0-bus-width4 { | |
587 | rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>, | |
588 | <3 RK_PB3 1 &pcfg_pull_default>, | |
589 | <3 RK_PB4 1 &pcfg_pull_default>, | |
590 | <3 RK_PB5 1 &pcfg_pull_default>; | |
591 | }; | |
592 | }; | |
593 | ||
594 | sd1 { | |
595 | sd1_clk: sd1-clk { | |
596 | rockchip,pins = <3 RK_PC5 1 &pcfg_pull_default>; | |
597 | }; | |
598 | ||
599 | sd1_cmd: sd1-cmd { | |
600 | rockchip,pins = <3 RK_PC0 1 &pcfg_pull_default>; | |
601 | }; | |
602 | ||
603 | sd1_cd: sd1-cd { | |
604 | rockchip,pins = <3 RK_PC6 1 &pcfg_pull_default>; | |
605 | }; | |
606 | ||
607 | sd1_wp: sd1-wp { | |
608 | rockchip,pins = <3 RK_PC7 1 &pcfg_pull_default>; | |
609 | }; | |
610 | ||
611 | sd1_bus1: sd1-bus-width1 { | |
612 | rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>; | |
613 | }; | |
614 | ||
615 | sd1_bus4: sd1-bus-width4 { | |
616 | rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>, | |
617 | <3 RK_PC2 1 &pcfg_pull_default>, | |
618 | <3 RK_PC3 1 &pcfg_pull_default>, | |
619 | <3 RK_PC4 1 &pcfg_pull_default>; | |
620 | }; | |
621 | }; | |
622 | ||
623 | i2s0 { | |
624 | i2s0_bus: i2s0-bus { | |
625 | rockchip,pins = <0 RK_PA7 1 &pcfg_pull_default>, | |
626 | <0 RK_PB0 1 &pcfg_pull_default>, | |
627 | <0 RK_PB1 1 &pcfg_pull_default>, | |
628 | <0 RK_PB2 1 &pcfg_pull_default>, | |
629 | <0 RK_PB3 1 &pcfg_pull_default>, | |
630 | <0 RK_PB4 1 &pcfg_pull_default>, | |
631 | <0 RK_PB5 1 &pcfg_pull_default>, | |
632 | <0 RK_PB6 1 &pcfg_pull_default>, | |
633 | <0 RK_PB7 1 &pcfg_pull_default>; | |
634 | }; | |
635 | }; | |
636 | ||
637 | i2s1 { | |
638 | i2s1_bus: i2s1-bus { | |
639 | rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>, | |
640 | <0 RK_PC1 1 &pcfg_pull_default>, | |
641 | <0 RK_PC2 1 &pcfg_pull_default>, | |
642 | <0 RK_PC3 1 &pcfg_pull_default>, | |
643 | <0 RK_PC4 1 &pcfg_pull_default>, | |
644 | <0 RK_PC5 1 &pcfg_pull_default>; | |
645 | }; | |
646 | }; | |
647 | ||
648 | i2s2 { | |
649 | i2s2_bus: i2s2-bus { | |
650 | rockchip,pins = <0 RK_PD0 1 &pcfg_pull_default>, | |
651 | <0 RK_PD1 1 &pcfg_pull_default>, | |
652 | <0 RK_PD2 1 &pcfg_pull_default>, | |
653 | <0 RK_PD3 1 &pcfg_pull_default>, | |
654 | <0 RK_PD4 1 &pcfg_pull_default>, | |
655 | <0 RK_PD5 1 &pcfg_pull_default>; | |
656 | }; | |
657 | }; | |
658 | }; | |
659 | }; | |
660 | ||
661 | &gpu { | |
662 | compatible = "rockchip,rk3066-mali", "arm,mali-400"; | |
663 | interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, | |
664 | <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, | |
665 | <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, | |
666 | <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, | |
667 | <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, | |
668 | <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, | |
669 | <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, | |
670 | <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, | |
671 | <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, | |
672 | <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; | |
673 | interrupt-names = "gp", | |
674 | "gpmmu", | |
675 | "pp0", | |
676 | "ppmmu0", | |
677 | "pp1", | |
678 | "ppmmu1", | |
679 | "pp2", | |
680 | "ppmmu2", | |
681 | "pp3", | |
682 | "ppmmu3"; | |
683 | power-domains = <&power RK3066_PD_GPU>; | |
684 | }; | |
685 | ||
686 | &grf { | |
687 | compatible = "rockchip,rk3066-grf", "syscon", "simple-mfd"; | |
688 | ||
689 | usbphy: usbphy { | |
690 | compatible = "rockchip,rk3066a-usb-phy"; | |
691 | #address-cells = <1>; | |
692 | #size-cells = <0>; | |
693 | status = "disabled"; | |
694 | ||
695 | usbphy0: usb-phy@17c { | |
696 | reg = <0x17c>; | |
697 | clocks = <&cru SCLK_OTGPHY0>; | |
698 | clock-names = "phyclk"; | |
699 | #clock-cells = <0>; | |
700 | #phy-cells = <0>; | |
701 | }; | |
702 | ||
703 | usbphy1: usb-phy@188 { | |
704 | reg = <0x188>; | |
705 | clocks = <&cru SCLK_OTGPHY1>; | |
706 | clock-names = "phyclk"; | |
707 | #clock-cells = <0>; | |
708 | #phy-cells = <0>; | |
709 | }; | |
710 | }; | |
711 | }; | |
712 | ||
713 | &i2c0 { | |
714 | pinctrl-names = "default"; | |
715 | pinctrl-0 = <&i2c0_xfer>; | |
716 | }; | |
717 | ||
718 | &i2c1 { | |
719 | pinctrl-names = "default"; | |
720 | pinctrl-0 = <&i2c1_xfer>; | |
721 | }; | |
722 | ||
723 | &i2c2 { | |
724 | pinctrl-names = "default"; | |
725 | pinctrl-0 = <&i2c2_xfer>; | |
726 | }; | |
727 | ||
728 | &i2c3 { | |
729 | pinctrl-names = "default"; | |
730 | pinctrl-0 = <&i2c3_xfer>; | |
731 | }; | |
732 | ||
733 | &i2c4 { | |
734 | pinctrl-names = "default"; | |
735 | pinctrl-0 = <&i2c4_xfer>; | |
736 | }; | |
737 | ||
738 | &mmc0 { | |
739 | clock-frequency = <50000000>; | |
740 | dmas = <&dmac2 1>; | |
741 | dma-names = "rx-tx"; | |
742 | max-frequency = <50000000>; | |
743 | pinctrl-names = "default"; | |
744 | pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>; | |
745 | }; | |
746 | ||
747 | &mmc1 { | |
748 | dmas = <&dmac2 3>; | |
749 | dma-names = "rx-tx"; | |
750 | pinctrl-names = "default"; | |
751 | pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>; | |
752 | }; | |
753 | ||
754 | &emmc { | |
755 | dmas = <&dmac2 4>; | |
756 | dma-names = "rx-tx"; | |
757 | }; | |
758 | ||
759 | &pmu { | |
760 | power: power-controller { | |
761 | compatible = "rockchip,rk3066-power-controller"; | |
762 | #power-domain-cells = <1>; | |
763 | #address-cells = <1>; | |
764 | #size-cells = <0>; | |
765 | ||
766 | power-domain@RK3066_PD_VIO { | |
767 | reg = <RK3066_PD_VIO>; | |
768 | clocks = <&cru ACLK_LCDC0>, | |
769 | <&cru ACLK_LCDC1>, | |
770 | <&cru DCLK_LCDC0>, | |
771 | <&cru DCLK_LCDC1>, | |
772 | <&cru HCLK_LCDC0>, | |
773 | <&cru HCLK_LCDC1>, | |
774 | <&cru SCLK_CIF1>, | |
775 | <&cru ACLK_CIF1>, | |
776 | <&cru HCLK_CIF1>, | |
777 | <&cru SCLK_CIF0>, | |
778 | <&cru ACLK_CIF0>, | |
779 | <&cru HCLK_CIF0>, | |
780 | <&cru HCLK_HDMI>, | |
781 | <&cru ACLK_IPP>, | |
782 | <&cru HCLK_IPP>, | |
783 | <&cru ACLK_RGA>, | |
784 | <&cru HCLK_RGA>; | |
785 | pm_qos = <&qos_lcdc0>, | |
786 | <&qos_lcdc1>, | |
787 | <&qos_cif0>, | |
788 | <&qos_cif1>, | |
789 | <&qos_ipp>, | |
790 | <&qos_rga>; | |
791 | #power-domain-cells = <0>; | |
792 | }; | |
793 | ||
794 | power-domain@RK3066_PD_VIDEO { | |
795 | reg = <RK3066_PD_VIDEO>; | |
796 | clocks = <&cru ACLK_VDPU>, | |
797 | <&cru ACLK_VEPU>, | |
798 | <&cru HCLK_VDPU>, | |
799 | <&cru HCLK_VEPU>; | |
800 | pm_qos = <&qos_vpu>; | |
801 | #power-domain-cells = <0>; | |
802 | }; | |
803 | ||
804 | power-domain@RK3066_PD_GPU { | |
805 | reg = <RK3066_PD_GPU>; | |
806 | clocks = <&cru ACLK_GPU>; | |
807 | pm_qos = <&qos_gpu>; | |
808 | #power-domain-cells = <0>; | |
809 | }; | |
810 | }; | |
811 | }; | |
812 | ||
813 | &pwm0 { | |
814 | pinctrl-names = "default"; | |
815 | pinctrl-0 = <&pwm0_out>; | |
816 | }; | |
817 | ||
818 | &pwm1 { | |
819 | pinctrl-names = "default"; | |
820 | pinctrl-0 = <&pwm1_out>; | |
821 | }; | |
822 | ||
823 | &pwm2 { | |
824 | pinctrl-names = "default"; | |
825 | pinctrl-0 = <&pwm2_out>; | |
826 | }; | |
827 | ||
828 | &pwm3 { | |
829 | pinctrl-names = "default"; | |
830 | pinctrl-0 = <&pwm3_out>; | |
831 | }; | |
832 | ||
833 | &spi0 { | |
834 | pinctrl-names = "default"; | |
835 | pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; | |
836 | }; | |
837 | ||
838 | &spi1 { | |
839 | pinctrl-names = "default"; | |
840 | pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; | |
841 | }; | |
842 | ||
843 | &uart0 { | |
844 | compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; | |
845 | dmas = <&dmac1_s 0>, <&dmac1_s 1>; | |
846 | dma-names = "tx", "rx"; | |
847 | pinctrl-names = "default"; | |
848 | pinctrl-0 = <&uart0_xfer>; | |
849 | }; | |
850 | ||
851 | &uart1 { | |
852 | compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; | |
853 | dmas = <&dmac1_s 2>, <&dmac1_s 3>; | |
854 | dma-names = "tx", "rx"; | |
855 | pinctrl-names = "default"; | |
856 | pinctrl-0 = <&uart1_xfer>; | |
857 | }; | |
858 | ||
859 | &uart2 { | |
860 | compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; | |
861 | dmas = <&dmac2 6>, <&dmac2 7>; | |
862 | dma-names = "tx", "rx"; | |
863 | pinctrl-names = "default"; | |
864 | pinctrl-0 = <&uart2_xfer>; | |
865 | }; | |
866 | ||
867 | &uart3 { | |
868 | compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; | |
869 | dmas = <&dmac2 8>, <&dmac2 9>; | |
870 | dma-names = "tx", "rx"; | |
871 | pinctrl-names = "default"; | |
872 | pinctrl-0 = <&uart3_xfer>; | |
873 | }; | |
874 | ||
875 | &vpu { | |
876 | power-domains = <&power RK3066_PD_VIDEO>; | |
877 | }; | |
878 | ||
879 | &wdt { | |
880 | compatible = "rockchip,rk3066-wdt", "snps,dw-wdt"; | |
881 | }; | |
882 | ||
883 | &emac { | |
884 | compatible = "rockchip,rk3066-emac"; | |
885 | }; |