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53633a89 TR |
1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
2 | /* | |
3 | * Copyright 2019 NXP | |
4 | */ | |
5 | ||
6 | #include <dt-bindings/clock/imx8mn-clock.h> | |
7 | #include <dt-bindings/power/imx8mn-power.h> | |
8 | #include <dt-bindings/reset/imx8mq-reset.h> | |
9 | #include <dt-bindings/gpio/gpio.h> | |
10 | #include <dt-bindings/input/input.h> | |
11 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
12 | #include <dt-bindings/thermal/thermal.h> | |
13 | ||
14 | #include "imx8mn-pinfunc.h" | |
15 | ||
16 | / { | |
17 | interrupt-parent = <&gic>; | |
18 | #address-cells = <2>; | |
19 | #size-cells = <2>; | |
20 | ||
21 | aliases { | |
22 | ethernet0 = &fec1; | |
23 | gpio0 = &gpio1; | |
24 | gpio1 = &gpio2; | |
25 | gpio2 = &gpio3; | |
26 | gpio3 = &gpio4; | |
27 | gpio4 = &gpio5; | |
28 | i2c0 = &i2c1; | |
29 | i2c1 = &i2c2; | |
30 | i2c2 = &i2c3; | |
31 | i2c3 = &i2c4; | |
32 | mmc0 = &usdhc1; | |
33 | mmc1 = &usdhc2; | |
34 | mmc2 = &usdhc3; | |
35 | serial0 = &uart1; | |
36 | serial1 = &uart2; | |
37 | serial2 = &uart3; | |
38 | serial3 = &uart4; | |
39 | spi0 = &ecspi1; | |
40 | spi1 = &ecspi2; | |
41 | spi2 = &ecspi3; | |
42 | }; | |
43 | ||
44 | cpus { | |
45 | #address-cells = <1>; | |
46 | #size-cells = <0>; | |
47 | ||
48 | idle-states { | |
49 | entry-method = "psci"; | |
50 | ||
51 | cpu_pd_wait: cpu-pd-wait { | |
52 | compatible = "arm,idle-state"; | |
53 | arm,psci-suspend-param = <0x0010033>; | |
54 | local-timer-stop; | |
55 | entry-latency-us = <1000>; | |
56 | exit-latency-us = <700>; | |
57 | min-residency-us = <2700>; | |
58 | }; | |
59 | }; | |
60 | ||
61 | A53_0: cpu@0 { | |
62 | device_type = "cpu"; | |
63 | compatible = "arm,cortex-a53"; | |
64 | reg = <0x0>; | |
65 | clock-latency = <61036>; | |
66 | clocks = <&clk IMX8MN_CLK_ARM>; | |
67 | enable-method = "psci"; | |
68 | i-cache-size = <0x8000>; | |
69 | i-cache-line-size = <64>; | |
70 | i-cache-sets = <256>; | |
71 | d-cache-size = <0x8000>; | |
72 | d-cache-line-size = <64>; | |
73 | d-cache-sets = <128>; | |
74 | next-level-cache = <&A53_L2>; | |
75 | operating-points-v2 = <&a53_opp_table>; | |
76 | nvmem-cells = <&cpu_speed_grade>; | |
77 | nvmem-cell-names = "speed_grade"; | |
78 | cpu-idle-states = <&cpu_pd_wait>; | |
79 | #cooling-cells = <2>; | |
80 | }; | |
81 | ||
82 | A53_1: cpu@1 { | |
83 | device_type = "cpu"; | |
84 | compatible = "arm,cortex-a53"; | |
85 | reg = <0x1>; | |
86 | clock-latency = <61036>; | |
87 | clocks = <&clk IMX8MN_CLK_ARM>; | |
88 | enable-method = "psci"; | |
89 | i-cache-size = <0x8000>; | |
90 | i-cache-line-size = <64>; | |
91 | i-cache-sets = <256>; | |
92 | d-cache-size = <0x8000>; | |
93 | d-cache-line-size = <64>; | |
94 | d-cache-sets = <128>; | |
95 | next-level-cache = <&A53_L2>; | |
96 | operating-points-v2 = <&a53_opp_table>; | |
97 | cpu-idle-states = <&cpu_pd_wait>; | |
98 | #cooling-cells = <2>; | |
99 | }; | |
100 | ||
101 | A53_2: cpu@2 { | |
102 | device_type = "cpu"; | |
103 | compatible = "arm,cortex-a53"; | |
104 | reg = <0x2>; | |
105 | clock-latency = <61036>; | |
106 | clocks = <&clk IMX8MN_CLK_ARM>; | |
107 | enable-method = "psci"; | |
108 | i-cache-size = <0x8000>; | |
109 | i-cache-line-size = <64>; | |
110 | i-cache-sets = <256>; | |
111 | d-cache-size = <0x8000>; | |
112 | d-cache-line-size = <64>; | |
113 | d-cache-sets = <128>; | |
114 | next-level-cache = <&A53_L2>; | |
115 | operating-points-v2 = <&a53_opp_table>; | |
116 | cpu-idle-states = <&cpu_pd_wait>; | |
117 | #cooling-cells = <2>; | |
118 | }; | |
119 | ||
120 | A53_3: cpu@3 { | |
121 | device_type = "cpu"; | |
122 | compatible = "arm,cortex-a53"; | |
123 | reg = <0x3>; | |
124 | clock-latency = <61036>; | |
125 | clocks = <&clk IMX8MN_CLK_ARM>; | |
126 | enable-method = "psci"; | |
127 | i-cache-size = <0x8000>; | |
128 | i-cache-line-size = <64>; | |
129 | i-cache-sets = <256>; | |
130 | d-cache-size = <0x8000>; | |
131 | d-cache-line-size = <64>; | |
132 | d-cache-sets = <128>; | |
133 | next-level-cache = <&A53_L2>; | |
134 | operating-points-v2 = <&a53_opp_table>; | |
135 | cpu-idle-states = <&cpu_pd_wait>; | |
136 | #cooling-cells = <2>; | |
137 | }; | |
138 | ||
139 | A53_L2: l2-cache0 { | |
140 | compatible = "cache"; | |
141 | cache-level = <2>; | |
142 | cache-unified; | |
143 | cache-size = <0x80000>; | |
144 | cache-line-size = <64>; | |
145 | cache-sets = <512>; | |
146 | }; | |
147 | }; | |
148 | ||
149 | a53_opp_table: opp-table { | |
150 | compatible = "operating-points-v2"; | |
151 | opp-shared; | |
152 | ||
153 | opp-1200000000 { | |
154 | opp-hz = /bits/ 64 <1200000000>; | |
155 | opp-microvolt = <850000>; | |
156 | opp-supported-hw = <0xb00>, <0x7>; | |
157 | clock-latency-ns = <150000>; | |
158 | opp-suspend; | |
159 | }; | |
160 | ||
161 | opp-1400000000 { | |
162 | opp-hz = /bits/ 64 <1400000000>; | |
163 | opp-microvolt = <950000>; | |
164 | opp-supported-hw = <0x300>, <0x7>; | |
165 | clock-latency-ns = <150000>; | |
166 | opp-suspend; | |
167 | }; | |
168 | ||
169 | opp-1500000000 { | |
170 | opp-hz = /bits/ 64 <1500000000>; | |
171 | opp-microvolt = <1000000>; | |
172 | opp-supported-hw = <0x100>, <0x3>; | |
173 | clock-latency-ns = <150000>; | |
174 | opp-suspend; | |
175 | }; | |
176 | }; | |
177 | ||
178 | osc_32k: clock-osc-32k { | |
179 | compatible = "fixed-clock"; | |
180 | #clock-cells = <0>; | |
181 | clock-frequency = <32768>; | |
182 | clock-output-names = "osc_32k"; | |
183 | }; | |
184 | ||
185 | osc_24m: clock-osc-24m { | |
186 | compatible = "fixed-clock"; | |
187 | #clock-cells = <0>; | |
188 | clock-frequency = <24000000>; | |
189 | clock-output-names = "osc_24m"; | |
190 | }; | |
191 | ||
192 | clk_ext1: clock-ext1 { | |
193 | compatible = "fixed-clock"; | |
194 | #clock-cells = <0>; | |
195 | clock-frequency = <133000000>; | |
196 | clock-output-names = "clk_ext1"; | |
197 | }; | |
198 | ||
199 | clk_ext2: clock-ext2 { | |
200 | compatible = "fixed-clock"; | |
201 | #clock-cells = <0>; | |
202 | clock-frequency = <133000000>; | |
203 | clock-output-names = "clk_ext2"; | |
204 | }; | |
205 | ||
206 | clk_ext3: clock-ext3 { | |
207 | compatible = "fixed-clock"; | |
208 | #clock-cells = <0>; | |
209 | clock-frequency = <133000000>; | |
210 | clock-output-names = "clk_ext3"; | |
211 | }; | |
212 | ||
213 | clk_ext4: clock-ext4 { | |
214 | compatible = "fixed-clock"; | |
215 | #clock-cells = <0>; | |
216 | clock-frequency = <133000000>; | |
217 | clock-output-names = "clk_ext4"; | |
218 | }; | |
219 | ||
220 | pmu { | |
221 | compatible = "arm,cortex-a53-pmu"; | |
222 | interrupts = <GIC_PPI 7 | |
223 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; | |
224 | }; | |
225 | ||
226 | psci { | |
227 | compatible = "arm,psci-1.0"; | |
228 | method = "smc"; | |
229 | }; | |
230 | ||
231 | thermal-zones { | |
232 | cpu-thermal { | |
233 | polling-delay-passive = <250>; | |
234 | polling-delay = <2000>; | |
235 | thermal-sensors = <&tmu>; | |
236 | trips { | |
237 | cpu_alert0: trip0 { | |
238 | temperature = <85000>; | |
239 | hysteresis = <2000>; | |
240 | type = "passive"; | |
241 | }; | |
242 | ||
243 | cpu_crit0: trip1 { | |
244 | temperature = <95000>; | |
245 | hysteresis = <2000>; | |
246 | type = "critical"; | |
247 | }; | |
248 | }; | |
249 | ||
250 | cooling-maps { | |
251 | map0 { | |
252 | trip = <&cpu_alert0>; | |
253 | cooling-device = | |
254 | <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
255 | <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
256 | <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
257 | <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
258 | }; | |
259 | }; | |
260 | }; | |
261 | }; | |
262 | ||
263 | timer { | |
264 | compatible = "arm,armv8-timer"; | |
265 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
266 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
267 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
268 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; | |
269 | clock-frequency = <8000000>; | |
270 | arm,no-tick-in-suspend; | |
271 | }; | |
272 | ||
273 | soc: soc@0 { | |
274 | compatible = "fsl,imx8mn-soc", "simple-bus"; | |
275 | #address-cells = <1>; | |
276 | #size-cells = <1>; | |
277 | ranges = <0x0 0x0 0x0 0x3e000000>; | |
278 | dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; | |
279 | nvmem-cells = <&imx8mn_uid>; | |
280 | nvmem-cell-names = "soc_unique_id"; | |
281 | ||
282 | aips1: bus@30000000 { | |
283 | compatible = "fsl,aips-bus", "simple-bus"; | |
284 | reg = <0x30000000 0x400000>; | |
285 | #address-cells = <1>; | |
286 | #size-cells = <1>; | |
287 | ranges; | |
288 | ||
289 | spba2: spba-bus@30000000 { | |
290 | compatible = "fsl,spba-bus", "simple-bus"; | |
291 | #address-cells = <1>; | |
292 | #size-cells = <1>; | |
293 | reg = <0x30000000 0x100000>; | |
294 | ranges; | |
295 | ||
296 | sai2: sai@30020000 { | |
297 | compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; | |
298 | reg = <0x30020000 0x10000>; | |
299 | #sound-dai-cells = <0>; | |
300 | interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; | |
301 | clocks = <&clk IMX8MN_CLK_SAI2_IPG>, | |
302 | <&clk IMX8MN_CLK_DUMMY>, | |
303 | <&clk IMX8MN_CLK_SAI2_ROOT>, | |
304 | <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; | |
305 | clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; | |
306 | dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; | |
307 | dma-names = "rx", "tx"; | |
308 | status = "disabled"; | |
309 | }; | |
310 | ||
311 | sai3: sai@30030000 { | |
312 | compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; | |
313 | reg = <0x30030000 0x10000>; | |
314 | #sound-dai-cells = <0>; | |
315 | interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; | |
316 | clocks = <&clk IMX8MN_CLK_SAI3_IPG>, | |
317 | <&clk IMX8MN_CLK_DUMMY>, | |
318 | <&clk IMX8MN_CLK_SAI3_ROOT>, | |
319 | <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; | |
320 | clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; | |
321 | dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; | |
322 | dma-names = "rx", "tx"; | |
323 | status = "disabled"; | |
324 | }; | |
325 | ||
326 | sai5: sai@30050000 { | |
327 | compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; | |
328 | reg = <0x30050000 0x10000>; | |
329 | #sound-dai-cells = <0>; | |
330 | interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; | |
331 | clocks = <&clk IMX8MN_CLK_SAI5_IPG>, | |
332 | <&clk IMX8MN_CLK_DUMMY>, | |
333 | <&clk IMX8MN_CLK_SAI5_ROOT>, | |
334 | <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; | |
335 | clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; | |
336 | dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; | |
337 | dma-names = "rx", "tx"; | |
338 | fsl,shared-interrupt; | |
339 | fsl,dataline = <0 0xf 0xf>; | |
340 | status = "disabled"; | |
341 | }; | |
342 | ||
343 | sai6: sai@30060000 { | |
344 | compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; | |
345 | reg = <0x30060000 0x10000>; | |
346 | #sound-dai-cells = <0>; | |
347 | interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; | |
348 | clocks = <&clk IMX8MN_CLK_SAI6_IPG>, | |
349 | <&clk IMX8MN_CLK_DUMMY>, | |
350 | <&clk IMX8MN_CLK_SAI6_ROOT>, | |
351 | <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; | |
352 | clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; | |
353 | dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; | |
354 | dma-names = "rx", "tx"; | |
355 | status = "disabled"; | |
356 | }; | |
357 | ||
358 | micfil: audio-controller@30080000 { | |
359 | compatible = "fsl,imx8mm-micfil"; | |
360 | reg = <0x30080000 0x10000>; | |
361 | interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, | |
362 | <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, | |
363 | <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, | |
364 | <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; | |
365 | clocks = <&clk IMX8MN_CLK_PDM_IPG>, | |
366 | <&clk IMX8MN_CLK_PDM_ROOT>, | |
367 | <&clk IMX8MN_AUDIO_PLL1_OUT>, | |
368 | <&clk IMX8MN_AUDIO_PLL2_OUT>, | |
369 | <&clk IMX8MN_CLK_EXT3>; | |
370 | clock-names = "ipg_clk", "ipg_clk_app", | |
371 | "pll8k", "pll11k", "clkext3"; | |
372 | dmas = <&sdma2 24 25 0x80000000>; | |
373 | dma-names = "rx"; | |
374 | #sound-dai-cells = <0>; | |
375 | status = "disabled"; | |
376 | }; | |
377 | ||
378 | spdif1: spdif@30090000 { | |
379 | compatible = "fsl,imx35-spdif"; | |
380 | reg = <0x30090000 0x10000>; | |
381 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; | |
382 | clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, /* core */ | |
383 | <&clk IMX8MN_CLK_24M>, /* rxtx0 */ | |
384 | <&clk IMX8MN_CLK_SPDIF1>, /* rxtx1 */ | |
385 | <&clk IMX8MN_CLK_DUMMY>, /* rxtx2 */ | |
386 | <&clk IMX8MN_CLK_DUMMY>, /* rxtx3 */ | |
387 | <&clk IMX8MN_CLK_DUMMY>, /* rxtx4 */ | |
388 | <&clk IMX8MN_CLK_AUDIO_AHB>, /* rxtx5 */ | |
389 | <&clk IMX8MN_CLK_DUMMY>, /* rxtx6 */ | |
390 | <&clk IMX8MN_CLK_DUMMY>, /* rxtx7 */ | |
391 | <&clk IMX8MN_CLK_DUMMY>; /* spba */ | |
392 | clock-names = "core", "rxtx0", | |
393 | "rxtx1", "rxtx2", | |
394 | "rxtx3", "rxtx4", | |
395 | "rxtx5", "rxtx6", | |
396 | "rxtx7", "spba"; | |
397 | dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>; | |
398 | dma-names = "rx", "tx"; | |
399 | status = "disabled"; | |
400 | }; | |
401 | ||
402 | sai7: sai@300b0000 { | |
403 | compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; | |
404 | reg = <0x300b0000 0x10000>; | |
405 | #sound-dai-cells = <0>; | |
406 | interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; | |
407 | clocks = <&clk IMX8MN_CLK_SAI7_IPG>, | |
408 | <&clk IMX8MN_CLK_DUMMY>, | |
409 | <&clk IMX8MN_CLK_SAI7_ROOT>, | |
410 | <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; | |
411 | clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; | |
412 | dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>; | |
413 | dma-names = "rx", "tx"; | |
414 | status = "disabled"; | |
415 | }; | |
416 | ||
417 | easrc: easrc@300c0000 { | |
418 | compatible = "fsl,imx8mn-easrc"; | |
419 | reg = <0x300c0000 0x10000>; | |
420 | interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; | |
421 | clocks = <&clk IMX8MN_CLK_ASRC_ROOT>; | |
422 | clock-names = "mem"; | |
423 | dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>, | |
424 | <&sdma2 18 23 0> , <&sdma2 19 23 0>, | |
425 | <&sdma2 20 23 0> , <&sdma2 21 23 0>, | |
426 | <&sdma2 22 23 0> , <&sdma2 23 23 0>; | |
427 | dma-names = "ctx0_rx", "ctx0_tx", | |
428 | "ctx1_rx", "ctx1_tx", | |
429 | "ctx2_rx", "ctx2_tx", | |
430 | "ctx3_rx", "ctx3_tx"; | |
431 | firmware-name = "imx/easrc/easrc-imx8mn.bin"; | |
432 | fsl,asrc-rate = <8000>; | |
433 | fsl,asrc-format = <2>; | |
434 | status = "disabled"; | |
435 | }; | |
436 | }; | |
437 | ||
438 | gpio1: gpio@30200000 { | |
439 | compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; | |
440 | reg = <0x30200000 0x10000>; | |
441 | interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, | |
442 | <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; | |
443 | clocks = <&clk IMX8MN_CLK_GPIO1_ROOT>; | |
444 | gpio-controller; | |
445 | #gpio-cells = <2>; | |
446 | interrupt-controller; | |
447 | #interrupt-cells = <2>; | |
448 | gpio-ranges = <&iomuxc 0 10 30>; | |
449 | }; | |
450 | ||
451 | gpio2: gpio@30210000 { | |
452 | compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; | |
453 | reg = <0x30210000 0x10000>; | |
454 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, | |
455 | <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; | |
456 | clocks = <&clk IMX8MN_CLK_GPIO2_ROOT>; | |
457 | gpio-controller; | |
458 | #gpio-cells = <2>; | |
459 | interrupt-controller; | |
460 | #interrupt-cells = <2>; | |
461 | gpio-ranges = <&iomuxc 0 40 21>; | |
462 | }; | |
463 | ||
464 | gpio3: gpio@30220000 { | |
465 | compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; | |
466 | reg = <0x30220000 0x10000>; | |
467 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, | |
468 | <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; | |
469 | clocks = <&clk IMX8MN_CLK_GPIO3_ROOT>; | |
470 | gpio-controller; | |
471 | #gpio-cells = <2>; | |
472 | interrupt-controller; | |
473 | #interrupt-cells = <2>; | |
474 | gpio-ranges = <&iomuxc 0 61 26>; | |
475 | }; | |
476 | ||
477 | gpio4: gpio@30230000 { | |
478 | compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; | |
479 | reg = <0x30230000 0x10000>; | |
480 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, | |
481 | <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; | |
482 | clocks = <&clk IMX8MN_CLK_GPIO4_ROOT>; | |
483 | gpio-controller; | |
484 | #gpio-cells = <2>; | |
485 | interrupt-controller; | |
486 | #interrupt-cells = <2>; | |
487 | gpio-ranges = <&iomuxc 21 108 11>; | |
488 | }; | |
489 | ||
490 | gpio5: gpio@30240000 { | |
491 | compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; | |
492 | reg = <0x30240000 0x10000>; | |
493 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, | |
494 | <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; | |
495 | clocks = <&clk IMX8MN_CLK_GPIO5_ROOT>; | |
496 | gpio-controller; | |
497 | #gpio-cells = <2>; | |
498 | interrupt-controller; | |
499 | #interrupt-cells = <2>; | |
500 | gpio-ranges = <&iomuxc 0 119 30>; | |
501 | }; | |
502 | ||
503 | tmu: tmu@30260000 { | |
504 | compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu"; | |
505 | reg = <0x30260000 0x10000>; | |
506 | clocks = <&clk IMX8MN_CLK_TMU_ROOT>; | |
507 | nvmem-cells = <&tmu_calib>; | |
508 | nvmem-cell-names = "calib"; | |
509 | #thermal-sensor-cells = <0>; | |
510 | }; | |
511 | ||
512 | wdog1: watchdog@30280000 { | |
513 | compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; | |
514 | reg = <0x30280000 0x10000>; | |
515 | interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; | |
516 | clocks = <&clk IMX8MN_CLK_WDOG1_ROOT>; | |
517 | status = "disabled"; | |
518 | }; | |
519 | ||
520 | wdog2: watchdog@30290000 { | |
521 | compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; | |
522 | reg = <0x30290000 0x10000>; | |
523 | interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; | |
524 | clocks = <&clk IMX8MN_CLK_WDOG2_ROOT>; | |
525 | status = "disabled"; | |
526 | }; | |
527 | ||
528 | wdog3: watchdog@302a0000 { | |
529 | compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; | |
530 | reg = <0x302a0000 0x10000>; | |
531 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; | |
532 | clocks = <&clk IMX8MN_CLK_WDOG3_ROOT>; | |
533 | status = "disabled"; | |
534 | }; | |
535 | ||
536 | sdma3: dma-controller@302b0000 { | |
537 | compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; | |
538 | reg = <0x302b0000 0x10000>; | |
539 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; | |
540 | clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>, | |
541 | <&clk IMX8MN_CLK_SDMA3_ROOT>; | |
542 | clock-names = "ipg", "ahb"; | |
543 | #dma-cells = <3>; | |
544 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; | |
545 | }; | |
546 | ||
547 | sdma2: dma-controller@302c0000 { | |
548 | compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; | |
549 | reg = <0x302c0000 0x10000>; | |
550 | interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; | |
551 | clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>, | |
552 | <&clk IMX8MN_CLK_SDMA2_ROOT>; | |
553 | clock-names = "ipg", "ahb"; | |
554 | #dma-cells = <3>; | |
555 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; | |
556 | }; | |
557 | ||
558 | iomuxc: pinctrl@30330000 { | |
559 | compatible = "fsl,imx8mn-iomuxc"; | |
560 | reg = <0x30330000 0x10000>; | |
561 | }; | |
562 | ||
563 | gpr: syscon@30340000 { | |
564 | compatible = "fsl,imx8mn-iomuxc-gpr", "syscon"; | |
565 | reg = <0x30340000 0x10000>; | |
566 | }; | |
567 | ||
568 | ocotp: efuse@30350000 { | |
569 | compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon"; | |
570 | reg = <0x30350000 0x10000>; | |
571 | clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>; | |
572 | #address-cells = <1>; | |
573 | #size-cells = <1>; | |
574 | ||
575 | /* | |
576 | * The register address below maps to the MX8M | |
577 | * Fusemap Description Table entries this way. | |
578 | * Assuming | |
579 | * reg = <ADDR SIZE>; | |
580 | * then | |
581 | * Fuse Address = (ADDR * 4) + 0x400 | |
582 | * Note that if SIZE is greater than 4, then | |
583 | * each subsequent fuse is located at offset | |
584 | * +0x10 in Fusemap Description Table (e.g. | |
585 | * reg = <0x4 0x8> describes fuses 0x410 and | |
586 | * 0x420). | |
587 | */ | |
588 | imx8mn_uid: unique-id@4 { /* 0x410-0x420 */ | |
589 | reg = <0x4 0x8>; | |
590 | }; | |
591 | ||
592 | cpu_speed_grade: speed-grade@10 { /* 0x440 */ | |
593 | reg = <0x10 4>; | |
594 | }; | |
595 | ||
596 | tmu_calib: calib@3c { /* 0x4f0 */ | |
597 | reg = <0x3c 4>; | |
598 | }; | |
599 | ||
600 | fec_mac_address: mac-address@90 { /* 0x640 */ | |
601 | reg = <0x90 6>; | |
602 | }; | |
603 | }; | |
604 | ||
605 | anatop: clock-controller@30360000 { | |
606 | compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop"; | |
607 | reg = <0x30360000 0x10000>; | |
608 | #clock-cells = <1>; | |
609 | }; | |
610 | ||
611 | snvs: snvs@30370000 { | |
612 | compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; | |
613 | reg = <0x30370000 0x10000>; | |
614 | ||
615 | snvs_rtc: snvs-rtc-lp { | |
616 | compatible = "fsl,sec-v4.0-mon-rtc-lp"; | |
617 | regmap = <&snvs>; | |
618 | offset = <0x34>; | |
619 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, | |
620 | <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | |
621 | clocks = <&clk IMX8MN_CLK_SNVS_ROOT>; | |
622 | clock-names = "snvs-rtc"; | |
623 | }; | |
624 | ||
625 | snvs_pwrkey: snvs-powerkey { | |
626 | compatible = "fsl,sec-v4.0-pwrkey"; | |
627 | regmap = <&snvs>; | |
628 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; | |
629 | clocks = <&clk IMX8MN_CLK_SNVS_ROOT>; | |
630 | clock-names = "snvs-pwrkey"; | |
631 | linux,keycode = <KEY_POWER>; | |
632 | wakeup-source; | |
633 | status = "disabled"; | |
634 | }; | |
635 | }; | |
636 | ||
637 | clk: clock-controller@30380000 { | |
638 | compatible = "fsl,imx8mn-ccm"; | |
639 | reg = <0x30380000 0x10000>; | |
93743d24 TR |
640 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, |
641 | <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; | |
53633a89 TR |
642 | #clock-cells = <1>; |
643 | clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, | |
644 | <&clk_ext3>, <&clk_ext4>; | |
645 | clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", | |
646 | "clk_ext3", "clk_ext4"; | |
647 | assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>, | |
648 | <&clk IMX8MN_CLK_A53_CORE>, | |
649 | <&clk IMX8MN_CLK_NOC>, | |
650 | <&clk IMX8MN_CLK_AUDIO_AHB>, | |
651 | <&clk IMX8MN_CLK_IPG_AUDIO_ROOT>, | |
652 | <&clk IMX8MN_SYS_PLL3>, | |
653 | <&clk IMX8MN_AUDIO_PLL1>, | |
654 | <&clk IMX8MN_AUDIO_PLL2>; | |
655 | assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>, | |
656 | <&clk IMX8MN_ARM_PLL_OUT>, | |
657 | <&clk IMX8MN_SYS_PLL3_OUT>, | |
658 | <&clk IMX8MN_SYS_PLL1_800M>; | |
659 | assigned-clock-rates = <0>, <0>, <0>, | |
660 | <400000000>, | |
661 | <400000000>, | |
662 | <600000000>, | |
663 | <393216000>, | |
664 | <361267200>; | |
665 | }; | |
666 | ||
667 | src: reset-controller@30390000 { | |
668 | compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon"; | |
669 | reg = <0x30390000 0x10000>; | |
670 | interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; | |
671 | #reset-cells = <1>; | |
672 | }; | |
673 | ||
674 | gpc: gpc@303a0000 { | |
675 | compatible = "fsl,imx8mn-gpc"; | |
676 | reg = <0x303a0000 0x10000>; | |
677 | interrupt-parent = <&gic>; | |
678 | interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; | |
679 | ||
680 | pgc { | |
681 | #address-cells = <1>; | |
682 | #size-cells = <0>; | |
683 | ||
684 | pgc_hsiomix: power-domain@0 { | |
685 | #power-domain-cells = <0>; | |
686 | reg = <IMX8MN_POWER_DOMAIN_HSIOMIX>; | |
687 | clocks = <&clk IMX8MN_CLK_USB_BUS>; | |
688 | }; | |
689 | ||
690 | pgc_otg1: power-domain@1 { | |
691 | #power-domain-cells = <0>; | |
692 | reg = <IMX8MN_POWER_DOMAIN_OTG1>; | |
693 | }; | |
694 | ||
695 | pgc_gpumix: power-domain@2 { | |
696 | #power-domain-cells = <0>; | |
697 | reg = <IMX8MN_POWER_DOMAIN_GPUMIX>; | |
698 | clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>, | |
699 | <&clk IMX8MN_CLK_GPU_SHADER>, | |
700 | <&clk IMX8MN_CLK_GPU_BUS_ROOT>, | |
701 | <&clk IMX8MN_CLK_GPU_AHB>; | |
702 | }; | |
703 | ||
704 | pgc_dispmix: power-domain@3 { | |
705 | #power-domain-cells = <0>; | |
706 | reg = <IMX8MN_POWER_DOMAIN_DISPMIX>; | |
707 | clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>, | |
708 | <&clk IMX8MN_CLK_DISP_APB_ROOT>; | |
709 | }; | |
710 | ||
711 | pgc_mipi: power-domain@4 { | |
712 | #power-domain-cells = <0>; | |
713 | reg = <IMX8MN_POWER_DOMAIN_MIPI>; | |
714 | power-domains = <&pgc_dispmix>; | |
715 | }; | |
716 | }; | |
717 | }; | |
718 | }; | |
719 | ||
720 | aips2: bus@30400000 { | |
721 | compatible = "fsl,aips-bus", "simple-bus"; | |
722 | reg = <0x30400000 0x400000>; | |
723 | #address-cells = <1>; | |
724 | #size-cells = <1>; | |
725 | ranges; | |
726 | ||
727 | pwm1: pwm@30660000 { | |
728 | compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; | |
729 | reg = <0x30660000 0x10000>; | |
730 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; | |
731 | clocks = <&clk IMX8MN_CLK_PWM1_ROOT>, | |
732 | <&clk IMX8MN_CLK_PWM1_ROOT>; | |
733 | clock-names = "ipg", "per"; | |
734 | #pwm-cells = <3>; | |
735 | status = "disabled"; | |
736 | }; | |
737 | ||
738 | pwm2: pwm@30670000 { | |
739 | compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; | |
740 | reg = <0x30670000 0x10000>; | |
741 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; | |
742 | clocks = <&clk IMX8MN_CLK_PWM2_ROOT>, | |
743 | <&clk IMX8MN_CLK_PWM2_ROOT>; | |
744 | clock-names = "ipg", "per"; | |
745 | #pwm-cells = <3>; | |
746 | status = "disabled"; | |
747 | }; | |
748 | ||
749 | pwm3: pwm@30680000 { | |
750 | compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; | |
751 | reg = <0x30680000 0x10000>; | |
752 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; | |
753 | clocks = <&clk IMX8MN_CLK_PWM3_ROOT>, | |
754 | <&clk IMX8MN_CLK_PWM3_ROOT>; | |
755 | clock-names = "ipg", "per"; | |
756 | #pwm-cells = <3>; | |
757 | status = "disabled"; | |
758 | }; | |
759 | ||
760 | pwm4: pwm@30690000 { | |
761 | compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; | |
762 | reg = <0x30690000 0x10000>; | |
763 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; | |
764 | clocks = <&clk IMX8MN_CLK_PWM4_ROOT>, | |
765 | <&clk IMX8MN_CLK_PWM4_ROOT>; | |
766 | clock-names = "ipg", "per"; | |
767 | #pwm-cells = <3>; | |
768 | status = "disabled"; | |
769 | }; | |
770 | ||
771 | system_counter: timer@306a0000 { | |
772 | compatible = "nxp,sysctr-timer"; | |
773 | reg = <0x306a0000 0x20000>; | |
774 | interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; | |
775 | clocks = <&osc_24m>; | |
776 | clock-names = "per"; | |
777 | }; | |
778 | }; | |
779 | ||
780 | aips3: bus@30800000 { | |
781 | compatible = "fsl,aips-bus", "simple-bus"; | |
782 | reg = <0x30800000 0x400000>; | |
783 | #address-cells = <1>; | |
784 | #size-cells = <1>; | |
785 | ranges; | |
786 | ||
787 | spba1: spba-bus@30800000 { | |
788 | compatible = "fsl,spba-bus", "simple-bus"; | |
789 | #address-cells = <1>; | |
790 | #size-cells = <1>; | |
791 | reg = <0x30800000 0x100000>; | |
792 | ranges; | |
793 | ||
794 | ecspi1: spi@30820000 { | |
795 | compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; | |
796 | #address-cells = <1>; | |
797 | #size-cells = <0>; | |
798 | reg = <0x30820000 0x10000>; | |
799 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; | |
800 | clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>, | |
801 | <&clk IMX8MN_CLK_ECSPI1_ROOT>; | |
802 | clock-names = "ipg", "per"; | |
803 | dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; | |
804 | dma-names = "rx", "tx"; | |
805 | status = "disabled"; | |
806 | }; | |
807 | ||
808 | ecspi2: spi@30830000 { | |
809 | compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; | |
810 | #address-cells = <1>; | |
811 | #size-cells = <0>; | |
812 | reg = <0x30830000 0x10000>; | |
813 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; | |
814 | clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>, | |
815 | <&clk IMX8MN_CLK_ECSPI2_ROOT>; | |
816 | clock-names = "ipg", "per"; | |
817 | dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; | |
818 | dma-names = "rx", "tx"; | |
819 | status = "disabled"; | |
820 | }; | |
821 | ||
822 | ecspi3: spi@30840000 { | |
823 | compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; | |
824 | #address-cells = <1>; | |
825 | #size-cells = <0>; | |
826 | reg = <0x30840000 0x10000>; | |
827 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; | |
828 | clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>, | |
829 | <&clk IMX8MN_CLK_ECSPI3_ROOT>; | |
830 | clock-names = "ipg", "per"; | |
831 | dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; | |
832 | dma-names = "rx", "tx"; | |
833 | status = "disabled"; | |
834 | }; | |
835 | ||
836 | uart1: serial@30860000 { | |
837 | compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; | |
838 | reg = <0x30860000 0x10000>; | |
839 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; | |
840 | clocks = <&clk IMX8MN_CLK_UART1_ROOT>, | |
841 | <&clk IMX8MN_CLK_UART1_ROOT>; | |
842 | clock-names = "ipg", "per"; | |
843 | dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; | |
844 | dma-names = "rx", "tx"; | |
845 | status = "disabled"; | |
846 | }; | |
847 | ||
848 | uart3: serial@30880000 { | |
849 | compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; | |
850 | reg = <0x30880000 0x10000>; | |
851 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; | |
852 | clocks = <&clk IMX8MN_CLK_UART3_ROOT>, | |
853 | <&clk IMX8MN_CLK_UART3_ROOT>; | |
854 | clock-names = "ipg", "per"; | |
855 | dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; | |
856 | dma-names = "rx", "tx"; | |
857 | status = "disabled"; | |
858 | }; | |
859 | ||
860 | uart2: serial@30890000 { | |
861 | compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; | |
862 | reg = <0x30890000 0x10000>; | |
863 | interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; | |
864 | clocks = <&clk IMX8MN_CLK_UART2_ROOT>, | |
865 | <&clk IMX8MN_CLK_UART2_ROOT>; | |
866 | clock-names = "ipg", "per"; | |
867 | status = "disabled"; | |
868 | }; | |
869 | }; | |
870 | ||
871 | crypto: crypto@30900000 { | |
872 | compatible = "fsl,sec-v4.0"; | |
873 | #address-cells = <1>; | |
874 | #size-cells = <1>; | |
875 | reg = <0x30900000 0x40000>; | |
876 | ranges = <0 0x30900000 0x40000>; | |
877 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; | |
878 | clocks = <&clk IMX8MN_CLK_AHB>, | |
879 | <&clk IMX8MN_CLK_IPG_ROOT>; | |
880 | clock-names = "aclk", "ipg"; | |
881 | ||
882 | sec_jr0: jr@1000 { | |
883 | compatible = "fsl,sec-v4.0-job-ring"; | |
884 | reg = <0x1000 0x1000>; | |
885 | interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; | |
886 | status = "disabled"; | |
887 | }; | |
888 | ||
889 | sec_jr1: jr@2000 { | |
890 | compatible = "fsl,sec-v4.0-job-ring"; | |
891 | reg = <0x2000 0x1000>; | |
892 | interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; | |
893 | }; | |
894 | ||
895 | sec_jr2: jr@3000 { | |
896 | compatible = "fsl,sec-v4.0-job-ring"; | |
897 | reg = <0x3000 0x1000>; | |
898 | interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; | |
899 | }; | |
900 | }; | |
901 | ||
902 | i2c1: i2c@30a20000 { | |
903 | compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; | |
904 | #address-cells = <1>; | |
905 | #size-cells = <0>; | |
906 | reg = <0x30a20000 0x10000>; | |
907 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; | |
908 | clocks = <&clk IMX8MN_CLK_I2C1_ROOT>; | |
909 | status = "disabled"; | |
910 | }; | |
911 | ||
912 | i2c2: i2c@30a30000 { | |
913 | compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; | |
914 | #address-cells = <1>; | |
915 | #size-cells = <0>; | |
916 | reg = <0x30a30000 0x10000>; | |
917 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | |
918 | clocks = <&clk IMX8MN_CLK_I2C2_ROOT>; | |
919 | status = "disabled"; | |
920 | }; | |
921 | ||
922 | i2c3: i2c@30a40000 { | |
923 | #address-cells = <1>; | |
924 | #size-cells = <0>; | |
925 | compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; | |
926 | reg = <0x30a40000 0x10000>; | |
927 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; | |
928 | clocks = <&clk IMX8MN_CLK_I2C3_ROOT>; | |
929 | status = "disabled"; | |
930 | }; | |
931 | ||
932 | i2c4: i2c@30a50000 { | |
933 | compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; | |
934 | #address-cells = <1>; | |
935 | #size-cells = <0>; | |
936 | reg = <0x30a50000 0x10000>; | |
937 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; | |
938 | clocks = <&clk IMX8MN_CLK_I2C4_ROOT>; | |
939 | status = "disabled"; | |
940 | }; | |
941 | ||
942 | uart4: serial@30a60000 { | |
943 | compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; | |
944 | reg = <0x30a60000 0x10000>; | |
945 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; | |
946 | clocks = <&clk IMX8MN_CLK_UART4_ROOT>, | |
947 | <&clk IMX8MN_CLK_UART4_ROOT>; | |
948 | clock-names = "ipg", "per"; | |
949 | dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; | |
950 | dma-names = "rx", "tx"; | |
951 | status = "disabled"; | |
952 | }; | |
953 | ||
954 | mu: mailbox@30aa0000 { | |
955 | compatible = "fsl,imx8mn-mu", "fsl,imx6sx-mu"; | |
956 | reg = <0x30aa0000 0x10000>; | |
957 | interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; | |
958 | clocks = <&clk IMX8MN_CLK_MU_ROOT>; | |
959 | #mbox-cells = <2>; | |
960 | }; | |
961 | ||
962 | usdhc1: mmc@30b40000 { | |
963 | compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; | |
964 | reg = <0x30b40000 0x10000>; | |
965 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; | |
966 | clocks = <&clk IMX8MN_CLK_IPG_ROOT>, | |
967 | <&clk IMX8MN_CLK_NAND_USDHC_BUS>, | |
968 | <&clk IMX8MN_CLK_USDHC1_ROOT>; | |
969 | clock-names = "ipg", "ahb", "per"; | |
970 | fsl,tuning-start-tap = <20>; | |
971 | fsl,tuning-step = <2>; | |
972 | bus-width = <4>; | |
973 | status = "disabled"; | |
974 | }; | |
975 | ||
976 | usdhc2: mmc@30b50000 { | |
977 | compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; | |
978 | reg = <0x30b50000 0x10000>; | |
979 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
980 | clocks = <&clk IMX8MN_CLK_IPG_ROOT>, | |
981 | <&clk IMX8MN_CLK_NAND_USDHC_BUS>, | |
982 | <&clk IMX8MN_CLK_USDHC2_ROOT>; | |
983 | clock-names = "ipg", "ahb", "per"; | |
984 | fsl,tuning-start-tap = <20>; | |
985 | fsl,tuning-step = <2>; | |
986 | bus-width = <4>; | |
987 | status = "disabled"; | |
988 | }; | |
989 | ||
990 | usdhc3: mmc@30b60000 { | |
991 | compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; | |
992 | reg = <0x30b60000 0x10000>; | |
993 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; | |
994 | clocks = <&clk IMX8MN_CLK_IPG_ROOT>, | |
995 | <&clk IMX8MN_CLK_NAND_USDHC_BUS>, | |
996 | <&clk IMX8MN_CLK_USDHC3_ROOT>; | |
997 | clock-names = "ipg", "ahb", "per"; | |
998 | fsl,tuning-start-tap = <20>; | |
999 | fsl,tuning-step = <2>; | |
1000 | bus-width = <4>; | |
1001 | status = "disabled"; | |
1002 | }; | |
1003 | ||
1004 | flexspi: spi@30bb0000 { | |
1005 | #address-cells = <1>; | |
1006 | #size-cells = <0>; | |
1007 | compatible = "nxp,imx8mm-fspi"; | |
1008 | reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; | |
1009 | reg-names = "fspi_base", "fspi_mmap"; | |
1010 | interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; | |
1011 | clocks = <&clk IMX8MN_CLK_QSPI_ROOT>, | |
1012 | <&clk IMX8MN_CLK_QSPI_ROOT>; | |
1013 | clock-names = "fspi_en", "fspi"; | |
1014 | status = "disabled"; | |
1015 | }; | |
1016 | ||
1017 | sdma1: dma-controller@30bd0000 { | |
1018 | compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; | |
1019 | reg = <0x30bd0000 0x10000>; | |
1020 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; | |
1021 | clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>, | |
1022 | <&clk IMX8MN_CLK_AHB>; | |
1023 | clock-names = "ipg", "ahb"; | |
1024 | #dma-cells = <3>; | |
1025 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; | |
1026 | }; | |
1027 | ||
1028 | fec1: ethernet@30be0000 { | |
1029 | compatible = "fsl,imx8mn-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; | |
1030 | reg = <0x30be0000 0x10000>; | |
1031 | interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, | |
1032 | <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, | |
1033 | <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, | |
1034 | <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; | |
1035 | clocks = <&clk IMX8MN_CLK_ENET1_ROOT>, | |
1036 | <&clk IMX8MN_CLK_ENET1_ROOT>, | |
1037 | <&clk IMX8MN_CLK_ENET_TIMER>, | |
1038 | <&clk IMX8MN_CLK_ENET_REF>, | |
1039 | <&clk IMX8MN_CLK_ENET_PHY_REF>; | |
1040 | clock-names = "ipg", "ahb", "ptp", | |
1041 | "enet_clk_ref", "enet_out"; | |
1042 | assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>, | |
1043 | <&clk IMX8MN_CLK_ENET_TIMER>, | |
1044 | <&clk IMX8MN_CLK_ENET_REF>, | |
1045 | <&clk IMX8MN_CLK_ENET_PHY_REF>; | |
1046 | assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>, | |
1047 | <&clk IMX8MN_SYS_PLL2_100M>, | |
1048 | <&clk IMX8MN_SYS_PLL2_125M>, | |
1049 | <&clk IMX8MN_SYS_PLL2_50M>; | |
1050 | assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; | |
1051 | fsl,num-tx-queues = <3>; | |
1052 | fsl,num-rx-queues = <3>; | |
1053 | nvmem-cells = <&fec_mac_address>; | |
1054 | nvmem-cell-names = "mac-address"; | |
1055 | fsl,stop-mode = <&gpr 0x10 3>; | |
1056 | status = "disabled"; | |
1057 | }; | |
1058 | ||
1059 | }; | |
1060 | ||
1061 | aips4: bus@32c00000 { | |
1062 | compatible = "fsl,aips-bus", "simple-bus"; | |
1063 | reg = <0x32c00000 0x400000>; | |
1064 | #address-cells = <1>; | |
1065 | #size-cells = <1>; | |
1066 | ranges; | |
1067 | ||
1068 | lcdif: lcdif@32e00000 { | |
1069 | compatible = "fsl,imx8mn-lcdif", "fsl,imx6sx-lcdif"; | |
1070 | reg = <0x32e00000 0x10000>; | |
1071 | clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>, | |
1072 | <&clk IMX8MN_CLK_DISP_APB_ROOT>, | |
1073 | <&clk IMX8MN_CLK_DISP_AXI_ROOT>; | |
1074 | clock-names = "pix", "axi", "disp_axi"; | |
1075 | interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; | |
1076 | power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_LCDIF>; | |
1077 | status = "disabled"; | |
1078 | ||
1079 | port { | |
1080 | lcdif_to_dsim: endpoint { | |
1081 | remote-endpoint = <&dsim_from_lcdif>; | |
1082 | }; | |
1083 | }; | |
1084 | }; | |
1085 | ||
1086 | mipi_dsi: dsi@32e10000 { | |
1087 | compatible = "fsl,imx8mn-mipi-dsim", "fsl,imx8mm-mipi-dsim"; | |
1088 | reg = <0x32e10000 0x400>; | |
1089 | clocks = <&clk IMX8MN_CLK_DSI_CORE>, | |
1090 | <&clk IMX8MN_CLK_DSI_PHY_REF>; | |
1091 | clock-names = "bus_clk", "sclk_mipi"; | |
1092 | interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; | |
1093 | power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_DSI>; | |
1094 | status = "disabled"; | |
1095 | ||
1096 | ports { | |
1097 | #address-cells = <1>; | |
1098 | #size-cells = <0>; | |
1099 | ||
1100 | port@0 { | |
1101 | reg = <0>; | |
1102 | ||
1103 | dsim_from_lcdif: endpoint { | |
1104 | remote-endpoint = <&lcdif_to_dsim>; | |
1105 | }; | |
1106 | }; | |
1107 | }; | |
1108 | }; | |
1109 | ||
1110 | isi: isi@32e20000 { | |
1111 | compatible = "fsl,imx8mn-isi"; | |
1112 | reg = <0x32e20000 0x8000>; | |
1113 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; | |
1114 | clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>, | |
1115 | <&clk IMX8MN_CLK_DISP_APB_ROOT>; | |
1116 | clock-names = "axi", "apb"; | |
1117 | fsl,blk-ctrl = <&disp_blk_ctrl>; | |
1118 | power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_ISI>; | |
1119 | status = "disabled"; | |
1120 | ||
1121 | ports { | |
1122 | #address-cells = <1>; | |
1123 | #size-cells = <0>; | |
1124 | ||
1125 | port@0 { | |
1126 | reg = <0>; | |
1127 | isi_in: endpoint { | |
1128 | remote-endpoint = <&mipi_csi_out>; | |
1129 | }; | |
1130 | }; | |
1131 | }; | |
1132 | }; | |
1133 | ||
1134 | disp_blk_ctrl: blk-ctrl@32e28000 { | |
1135 | compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon"; | |
1136 | reg = <0x32e28000 0x100>; | |
1137 | power-domains = <&pgc_dispmix>, <&pgc_dispmix>, | |
1138 | <&pgc_dispmix>, <&pgc_mipi>, | |
1139 | <&pgc_mipi>; | |
1140 | power-domain-names = "bus", "isi", | |
1141 | "lcdif", "mipi-dsi", | |
1142 | "mipi-csi"; | |
1143 | clocks = <&clk IMX8MN_CLK_DISP_AXI>, | |
1144 | <&clk IMX8MN_CLK_DISP_APB>, | |
1145 | <&clk IMX8MN_CLK_DISP_AXI_ROOT>, | |
1146 | <&clk IMX8MN_CLK_DISP_APB_ROOT>, | |
1147 | <&clk IMX8MN_CLK_DISP_AXI_ROOT>, | |
1148 | <&clk IMX8MN_CLK_DISP_APB_ROOT>, | |
1149 | <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>, | |
1150 | <&clk IMX8MN_CLK_DSI_CORE>, | |
1151 | <&clk IMX8MN_CLK_DSI_PHY_REF>, | |
1152 | <&clk IMX8MN_CLK_CSI1_PHY_REF>, | |
1153 | <&clk IMX8MN_CLK_CAMERA_PIXEL_ROOT>; | |
1154 | clock-names = "disp_axi", "disp_apb", | |
1155 | "disp_axi_root", "disp_apb_root", | |
1156 | "lcdif-axi", "lcdif-apb", "lcdif-pix", | |
1157 | "dsi-pclk", "dsi-ref", | |
1158 | "csi-aclk", "csi-pclk"; | |
1159 | assigned-clocks = <&clk IMX8MN_CLK_DSI_CORE>, | |
1160 | <&clk IMX8MN_CLK_DSI_PHY_REF>, | |
1161 | <&clk IMX8MN_CLK_DISP_PIXEL>, | |
1162 | <&clk IMX8MN_CLK_DISP_AXI>, | |
1163 | <&clk IMX8MN_CLK_DISP_APB>; | |
1164 | assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>, | |
1165 | <&clk IMX8MN_CLK_24M>, | |
1166 | <&clk IMX8MN_VIDEO_PLL1_OUT>, | |
1167 | <&clk IMX8MN_SYS_PLL2_1000M>, | |
1168 | <&clk IMX8MN_SYS_PLL1_800M>; | |
1169 | assigned-clock-rates = <266000000>, | |
1170 | <24000000>, | |
1171 | <594000000>, | |
1172 | <500000000>, | |
1173 | <200000000>; | |
1174 | #power-domain-cells = <1>; | |
1175 | }; | |
1176 | ||
1177 | mipi_csi: mipi-csi@32e30000 { | |
1178 | compatible = "fsl,imx8mm-mipi-csi2"; | |
1179 | reg = <0x32e30000 0x1000>; | |
1180 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
1181 | assigned-clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>; | |
1182 | assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>; | |
1183 | assigned-clock-rates = <333000000>; | |
1184 | clock-frequency = <333000000>; | |
1185 | clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>, | |
1186 | <&clk IMX8MN_CLK_CAMERA_PIXEL>, | |
1187 | <&clk IMX8MN_CLK_CSI1_PHY_REF>, | |
1188 | <&clk IMX8MN_CLK_DISP_AXI_ROOT>; | |
1189 | clock-names = "pclk", "wrap", "phy", "axi"; | |
1190 | power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_CSI>; | |
1191 | status = "disabled"; | |
1192 | ||
1193 | ports { | |
1194 | #address-cells = <1>; | |
1195 | #size-cells = <0>; | |
1196 | ||
1197 | port@0 { | |
1198 | reg = <0>; | |
1199 | }; | |
1200 | ||
1201 | port@1 { | |
1202 | reg = <1>; | |
1203 | ||
1204 | mipi_csi_out: endpoint { | |
1205 | remote-endpoint = <&isi_in>; | |
1206 | }; | |
1207 | }; | |
1208 | }; | |
1209 | }; | |
1210 | ||
1211 | usbotg1: usb@32e40000 { | |
1212 | compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; | |
1213 | reg = <0x32e40000 0x200>; | |
1214 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; | |
1215 | clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>; | |
1216 | clock-names = "usb1_ctrl_root_clk"; | |
1217 | assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>; | |
1218 | assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>; | |
1219 | phys = <&usbphynop1>; | |
1220 | fsl,usbmisc = <&usbmisc1 0>; | |
1221 | power-domains = <&pgc_hsiomix>; | |
1222 | status = "disabled"; | |
1223 | }; | |
1224 | ||
1225 | usbmisc1: usbmisc@32e40200 { | |
1226 | compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc", | |
1227 | "fsl,imx6q-usbmisc"; | |
1228 | #index-cells = <1>; | |
1229 | reg = <0x32e40200 0x200>; | |
1230 | }; | |
1231 | }; | |
1232 | ||
1233 | dma_apbh: dma-controller@33000000 { | |
1234 | compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; | |
1235 | reg = <0x33000000 0x2000>; | |
1236 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, | |
1237 | <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, | |
1238 | <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, | |
1239 | <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; | |
1240 | #dma-cells = <1>; | |
1241 | dma-channels = <4>; | |
1242 | clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; | |
1243 | }; | |
1244 | ||
1245 | gpmi: nand-controller@33002000 { | |
1246 | compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand"; | |
1247 | #address-cells = <1>; | |
1248 | #size-cells = <0>; | |
1249 | reg = <0x33002000 0x2000>, <0x33004000 0x4000>; | |
1250 | reg-names = "gpmi-nand", "bch"; | |
1251 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; | |
1252 | interrupt-names = "bch"; | |
1253 | clocks = <&clk IMX8MN_CLK_NAND_ROOT>, | |
1254 | <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; | |
1255 | clock-names = "gpmi_io", "gpmi_bch_apb"; | |
1256 | dmas = <&dma_apbh 0>; | |
1257 | dma-names = "rx-tx"; | |
1258 | status = "disabled"; | |
1259 | }; | |
1260 | ||
1261 | gpu: gpu@38000000 { | |
1262 | compatible = "vivante,gc"; | |
1263 | reg = <0x38000000 0x8000>; | |
1264 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; | |
1265 | clocks = <&clk IMX8MN_CLK_GPU_AHB>, | |
1266 | <&clk IMX8MN_CLK_GPU_BUS_ROOT>, | |
1267 | <&clk IMX8MN_CLK_GPU_CORE_ROOT>, | |
1268 | <&clk IMX8MN_CLK_GPU_SHADER>; | |
1269 | clock-names = "reg", "bus", "core", "shader"; | |
1270 | assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE>, | |
1271 | <&clk IMX8MN_CLK_GPU_SHADER>, | |
1272 | <&clk IMX8MN_CLK_GPU_AXI>, | |
1273 | <&clk IMX8MN_CLK_GPU_AHB>, | |
1274 | <&clk IMX8MN_GPU_PLL>; | |
1275 | assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>, | |
1276 | <&clk IMX8MN_GPU_PLL_OUT>, | |
1277 | <&clk IMX8MN_SYS_PLL1_800M>, | |
1278 | <&clk IMX8MN_SYS_PLL1_800M>; | |
1279 | assigned-clock-rates = <400000000>, | |
1280 | <400000000>, | |
1281 | <800000000>, | |
1282 | <400000000>, | |
1283 | <1200000000>; | |
1284 | power-domains = <&pgc_gpumix>; | |
1285 | }; | |
1286 | ||
1287 | gic: interrupt-controller@38800000 { | |
1288 | compatible = "arm,gic-v3"; | |
1289 | reg = <0x38800000 0x10000>, | |
1290 | <0x38880000 0xc0000>; | |
1291 | #interrupt-cells = <3>; | |
1292 | interrupt-controller; | |
1293 | interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; | |
1294 | }; | |
1295 | ||
1296 | ddrc: memory-controller@3d400000 { | |
1297 | compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc"; | |
1298 | reg = <0x3d400000 0x400000>; | |
1299 | clock-names = "core", "pll", "alt", "apb"; | |
1300 | clocks = <&clk IMX8MN_CLK_DRAM_CORE>, | |
1301 | <&clk IMX8MN_DRAM_PLL>, | |
1302 | <&clk IMX8MN_CLK_DRAM_ALT>, | |
1303 | <&clk IMX8MN_CLK_DRAM_APB>; | |
1304 | }; | |
1305 | ||
1306 | ddr-pmu@3d800000 { | |
1307 | compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu"; | |
1308 | reg = <0x3d800000 0x400000>; | |
1309 | interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; | |
1310 | }; | |
1311 | }; | |
1312 | ||
1313 | usbphynop1: usbphynop1 { | |
1314 | #phy-cells = <0>; | |
1315 | compatible = "usb-nop-xceiv"; | |
1316 | clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; | |
1317 | assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; | |
1318 | assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>; | |
1319 | clock-names = "main_clk"; | |
1320 | power-domains = <&pgc_otg1>; | |
1321 | }; | |
1322 | }; |