[thirdparty/u-boot.git] / src / arm64 / freescale / imx93-11x11-evk.dts

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2022 NXP
 */

/dts-v1/;

#include "imx93.dtsi"

/ {
	model = "NXP i.MX93 11X11 EVK board";
	compatible = "fsl,imx93-11x11-evk", "fsl,imx93";

	chosen {
		stdout-path = &lpuart1;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		linux,cma {
			compatible = "shared-dma-pool";
			reusable;
			alloc-ranges = <0 0x80000000 0 0x40000000>;
			size = <0 0x10000000>;
			linux,cma-default;
		};

		vdev0vring0: vdev0vring0@a4000000 {
			reg = <0 0xa4000000 0 0x8000>;
			no-map;
		};

		vdev0vring1: vdev0vring1@a4008000 {
			reg = <0 0xa4008000 0 0x8000>;
			no-map;
		};

		vdev1vring0: vdev1vring0@a4000000 {
			reg = <0 0xa4010000 0 0x8000>;
			no-map;
		};

		vdev1vring1: vdev1vring1@a4018000 {
			reg = <0 0xa4018000 0 0x8000>;
			no-map;
		};

		rsc_table: rsc-table@2021f000 {
			reg = <0 0x2021f000 0 0x1000>;
			no-map;
		};

		vdevbuffer: vdevbuffer@a4020000 {
			compatible = "shared-dma-pool";
			reg = <0 0xa4020000 0 0x100000>;
			no-map;
		};

	};

	reg_vref_1v8: regulator-adc-vref {
		compatible = "regulator-fixed";
		regulator-name = "vref_1v8";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};

	reg_usdhc2_vmmc: regulator-usdhc2 {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
		regulator-name = "VSD_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
		off-on-delay-us = <12000>;
		enable-active-high;
	};
};

&adc1 {
	vref-supply = <&reg_vref_1v8>;
	status = "okay";
};

&cm33 {
	mbox-names = "tx", "rx", "rxdb";
	mboxes = <&mu1 0 1>,
		 <&mu1 1 1>,
		 <&mu1 3 1>;
	memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
			<&vdev1vring0>, <&vdev1vring1>, <&rsc_table>;
	status = "okay";
};

&mu1 {
	status = "okay";
};

&mu2 {
	status = "okay";
};

&eqos {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_eqos>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy1>;
	status = "okay";

	mdio {
		compatible = "snps,dwmac-mdio";
		#address-cells = <1>;
		#size-cells = <0>;
		clock-frequency = <5000000>;

		ethphy1: ethernet-phy@1 {
			reg = <1>;
			eee-broken-1000t;
		};
	};
};

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy2>;
	fsl,magic-packet;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;
		clock-frequency = <5000000>;

		ethphy2: ethernet-phy@2 {
			reg = <2>;
			eee-broken-1000t;
		};
	};
};

&lpuart1 { /* console */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

&lpuart5 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart5>;
	status = "okay";
};

&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1>;
	pinctrl-2 = <&pinctrl_usdhc1>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&usdhc2 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	bus-width = <4>;
	status = "okay";
	no-sdio;
	no-mmc;
};

&wdog3 {
	status = "okay";
};

&iomuxc {
	pinctrl_eqos: eqosgrp {
		fsl,pins = <
			MX93_PAD_ENET1_MDC__ENET_QOS_MDC			0x57e
			MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO			0x57e
			MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0			0x57e
			MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1			0x57e
			MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2			0x57e
			MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3			0x57e
			MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x5fe
			MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x57e
			MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0			0x57e
			MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1			0x57e
			MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2			0x57e
			MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3			0x57e
			MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x5fe
			MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x57e
		>;
	};

	pinctrl_fec: fecgrp {
		fsl,pins = <
			MX93_PAD_ENET2_MDC__ENET1_MDC			0x57e
			MX93_PAD_ENET2_MDIO__ENET1_MDIO			0x57e
			MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0		0x57e
			MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1		0x57e
			MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2		0x57e
			MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3		0x57e
			MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC		0x5fe
			MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL	0x57e
			MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0		0x57e
			MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1		0x57e
			MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2		0x57e
			MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3		0x57e
			MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC		0x5fe
			MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL	0x57e
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX93_PAD_UART1_RXD__LPUART1_RX			0x31e
			MX93_PAD_UART1_TXD__LPUART1_TX			0x31e
		>;
	};

	pinctrl_uart5: uart5grp {
		fsl,pins = <
			MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX		0x31e
			MX93_PAD_DAP_TDI__LPUART5_RX			0x31e
			MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B		0x31e
			MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B		0x31e
		>;
	};

	/* need to config the SION for data and cmd pad, refer to ERR052021 */
	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX93_PAD_SD1_CLK__USDHC1_CLK		0x15fe
			MX93_PAD_SD1_CMD__USDHC1_CMD		0x400013fe
			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x400013fe
			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x400013fe
			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x400013fe
			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x400013fe
			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x400013fe
			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x400013fe
			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x400013fe
			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x400013fe
			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x15fe
		>;
	};

	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
		fsl,pins = <
			MX93_PAD_SD2_RESET_B__GPIO3_IO07	0x31e
		>;
	};

	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
		fsl,pins = <
			MX93_PAD_SD2_CD_B__GPIO3_IO00		0x31e
		>;
	};

	/* need to config the SION for data and cmd pad, refer to ERR052021 */
	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX93_PAD_SD2_CLK__USDHC2_CLK		0x15fe
			MX93_PAD_SD2_CMD__USDHC2_CMD		0x400013fe
			MX93_PAD_SD2_DATA0__USDHC2_DATA0	0x400013fe
			MX93_PAD_SD2_DATA1__USDHC2_DATA1	0x400013fe
			MX93_PAD_SD2_DATA2__USDHC2_DATA2	0x400013fe
			MX93_PAD_SD2_DATA3__USDHC2_DATA3	0x400013fe
			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e
		>;
	};
};
Commit	Line	Data
53633a89 TR	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	2	/*
	3	* Copyright 2022 NXP
	4	*/
	5
	6	/dts-v1/;
	7
	8	#include "imx93.dtsi"
	9
	10	/ {
	11	model = "NXP i.MX93 11X11 EVK board";
	12	compatible = "fsl,imx93-11x11-evk", "fsl,imx93";
	13
	14	chosen {
	15	stdout-path = &lpuart1;
	16	};
	17
	18	reserved-memory {
	19	#address-cells = <2>;
	20	#size-cells = <2>;
	21	ranges;
	22
	23	linux,cma {
	24	compatible = "shared-dma-pool";
	25	reusable;
	26	alloc-ranges = <0 0x80000000 0 0x40000000>;
	27	size = <0 0x10000000>;
	28	linux,cma-default;
	29	};
	30
	31	vdev0vring0: vdev0vring0@a4000000 {
	32	reg = <0 0xa4000000 0 0x8000>;
	33	no-map;
	34	};
	35
	36	vdev0vring1: vdev0vring1@a4008000 {
	37	reg = <0 0xa4008000 0 0x8000>;
	38	no-map;
	39	};
	40
	41	vdev1vring0: vdev1vring0@a4000000 {
	42	reg = <0 0xa4010000 0 0x8000>;
	43	no-map;
	44	};
	45
	46	vdev1vring1: vdev1vring1@a4018000 {
	47	reg = <0 0xa4018000 0 0x8000>;
	48	no-map;
	49	};
	50
	51	rsc_table: rsc-table@2021f000 {
	52	reg = <0 0x2021f000 0 0x1000>;
	53	no-map;
	54	};
	55
	56	vdevbuffer: vdevbuffer@a4020000 {
	57	compatible = "shared-dma-pool";
	58	reg = <0 0xa4020000 0 0x100000>;
	59	no-map;
	60	};
	61
	62	};
	63
	64	reg_vref_1v8: regulator-adc-vref {
65	compatible = "regulator-fixed";
66	regulator-name = "vref_1v8";
67	regulator-min-microvolt = <1800000>;
68	regulator-max-microvolt = <1800000>;
69	};
70
71	reg_usdhc2_vmmc: regulator-usdhc2 {
72	compatible = "regulator-fixed";
73	pinctrl-names = "default";
74	pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
75	regulator-name = "VSD_3V3";
76	regulator-min-microvolt = <3300000>;
77	regulator-max-microvolt = <3300000>;
78	gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
93743d24	79	off-on-delay-us = <12000>;
53633a89 TR	80	enable-active-high;
	81	};
	82	};
	83
	84	&adc1 {
	85	vref-supply = <&reg_vref_1v8>;
	86	status = "okay";
	87	};
	88
	89	&cm33 {
	90	mbox-names = "tx", "rx", "rxdb";
	91	mboxes = <&mu1 0 1>,
	92	<&mu1 1 1>,
	93	<&mu1 3 1>;
	94	memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
	95	<&vdev1vring0>, <&vdev1vring1>, <&rsc_table>;
	96	status = "okay";
	97	};
	98
	99	&mu1 {
	100	status = "okay";
	101	};
	102
	103	&mu2 {
	104	status = "okay";
	105	};
	106
	107	&eqos {
	108	pinctrl-names = "default";
	109	pinctrl-0 = <&pinctrl_eqos>;
	110	phy-mode = "rgmii-id";
	111	phy-handle = <&ethphy1>;
	112	status = "okay";
	113
	114	mdio {
	115	compatible = "snps,dwmac-mdio";
	116	#address-cells = <1>;
	117	#size-cells = <0>;
	118	clock-frequency = <5000000>;
	119
	120	ethphy1: ethernet-phy@1 {
	121	reg = <1>;
	122	eee-broken-1000t;
	123	};
	124	};
	125	};
	126
	127	&fec {
	128	pinctrl-names = "default";
	129	pinctrl-0 = <&pinctrl_fec>;
	130	phy-mode = "rgmii-id";
	131	phy-handle = <&ethphy2>;
	132	fsl,magic-packet;
	133	status = "okay";
	134
	135	mdio {
	136	#address-cells = <1>;
	137	#size-cells = <0>;
	138	clock-frequency = <5000000>;
	139
	140	ethphy2: ethernet-phy@2 {
	141	reg = <2>;
	142	eee-broken-1000t;
	143	};
144	};
145	};
146
147	&lpuart1 { /* console */
148	pinctrl-names = "default";
149	pinctrl-0 = <&pinctrl_uart1>;
150	status = "okay";
151	};
152
153	&lpuart5 {
154	pinctrl-names = "default";
155	pinctrl-0 = <&pinctrl_uart5>;
156	status = "okay";
157	};
158
159	&usdhc1 {
160	pinctrl-names = "default", "state_100mhz", "state_200mhz";
161	pinctrl-0 = <&pinctrl_usdhc1>;
162	pinctrl-1 = <&pinctrl_usdhc1>;
163	pinctrl-2 = <&pinctrl_usdhc1>;
164	bus-width = <8>;
165	non-removable;
166	status = "okay";
167	};
168
169	&usdhc2 {
170	pinctrl-names = "default", "state_100mhz", "state_200mhz";
171	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
172	pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
173	pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
174	cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
175	vmmc-supply = <&reg_usdhc2_vmmc>;
176	bus-width = <4>;
177	status = "okay";
178	no-sdio;
179	no-mmc;
180	};
181
182	&wdog3 {
183	status = "okay";
184	};
185
186	&iomuxc {
187	pinctrl_eqos: eqosgrp {
188	fsl,pins = <
189	MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e
190	MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e
191	MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
192	MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
193	MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
194	MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
195	MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe
196	MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
197	MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e
198	MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e
199	MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e
200	MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e
201	MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe
202	MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e
203	>;
204	};
205
206	pinctrl_fec: fecgrp {
207	fsl,pins = <
208	MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e
209	MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e
210	MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
211	MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
212	MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e
213	MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e
214	MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe
215	MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
216	MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e
217	MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e
218	MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e
219	MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e
220	MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe
221	MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e
222	>;
223	};
224
225	pinctrl_uart1: uart1grp {
226	fsl,pins = <
227	MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
228	MX93_PAD_UART1_TXD__LPUART1_TX 0x31e
229	>;
230	};
231
232	pinctrl_uart5: uart5grp {
233	fsl,pins = <
234	MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e
235	MX93_PAD_DAP_TDI__LPUART5_RX 0x31e
236	MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e
237	MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e
238	>;
239	};
240
93743d24	241	/* need to config the SION for data and cmd pad, refer to ERR052021 */
53633a89 TR	242	pinctrl_usdhc1: usdhc1grp {
	243	fsl,pins = <
	244	MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe
93743d24 TR	245	MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe
	246	MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe
	247	MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe
	248	MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe
	249	MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe
	250	MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe
	251	MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe
	252	MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe
	253	MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe
53633a89 TR	254	MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
	255	>;
	256	};
	257
	258	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
	259	fsl,pins = <
	260	MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e
	261	>;
	262	};
	263
	264	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
	265	fsl,pins = <
	266	MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
	267	>;
	268	};
	269
93743d24	270	/* need to config the SION for data and cmd pad, refer to ERR052021 */
53633a89 TR	271	pinctrl_usdhc2: usdhc2grp {
	272	fsl,pins = <
	273	MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe
93743d24 TR	274	MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe
	275	MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe
	276	MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe
	277	MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe
	278	MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe
53633a89 TR	279	MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
	280	>;
	281	};
	282	};