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Squashed 'dts/upstream/' changes from aaba2d45dc2a..b35b9bd1d4ee
[thirdparty/u-boot.git] / src / arm64 / mediatek / mt8192.dtsi
CommitLineData
53633a89
TR		 1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2020 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8192-clk.h>
9#include <dt-bindings/gce/mt8192-gce.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/memory/mt8192-larb-port.h>
13#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
14#include <dt-bindings/phy/phy.h>
15#include <dt-bindings/power/mt8192-power.h>
16#include <dt-bindings/reset/mt8192-resets.h>
93743d24
TR		 17#include <dt-bindings/thermal/thermal.h>
18#include <dt-bindings/thermal/mediatek,lvts-thermal.h>
53633a89
TR		 19
20/ {
21 compatible = "mediatek,mt8192";
22 interrupt-parent = <&gic>;
23 #address-cells = <2>;
24 #size-cells = <2>;
25
26 aliases {
27 ovl0 = &ovl0;
28 ovl-2l0 = &ovl_2l0;
29 ovl-2l2 = &ovl_2l2;
30 rdma0 = &rdma0;
31 rdma4 = &rdma4;
32 };
33
34 clk13m: fixed-factor-clock-13m {
35 compatible = "fixed-factor-clock";
36 #clock-cells = <0>;
37 clocks = <&clk26m>;
38 clock-div = <2>;
39 clock-mult = <1>;
40 clock-output-names = "clk13m";
41 };
42
43 clk26m: oscillator0 {
44 compatible = "fixed-clock";
45 #clock-cells = <0>;
46 clock-frequency = <26000000>;
47 clock-output-names = "clk26m";
48 };
49
50 clk32k: oscillator1 {
51 compatible = "fixed-clock";
52 #clock-cells = <0>;
53 clock-frequency = <32768>;
54 clock-output-names = "clk32k";
55 };
56
57 cpus {
58 #address-cells = <1>;
59 #size-cells = <0>;
60
61 cpu0: cpu@0 {
62 device_type = "cpu";
63 compatible = "arm,cortex-a55";
64 reg = <0x000>;
65 enable-method = "psci";
66 clock-frequency = <1701000000>;
67 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
68 i-cache-size = <32768>;
69 i-cache-line-size = <64>;
70 i-cache-sets = <128>;
71 d-cache-size = <32768>;
72 d-cache-line-size = <64>;
73 d-cache-sets = <128>;
74 next-level-cache = <&l2_0>;
75 performance-domains = <&performance 0>;
76 capacity-dmips-mhz = <427>;
93743d24 77 #cooling-cells = <2>;
53633a89
TR		 78 };
79
80 cpu1: cpu@100 {
81 device_type = "cpu";
82 compatible = "arm,cortex-a55";
83 reg = <0x100>;
84 enable-method = "psci";
85 clock-frequency = <1701000000>;
86 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
87 i-cache-size = <32768>;
88 i-cache-line-size = <64>;
89 i-cache-sets = <128>;
90 d-cache-size = <32768>;
91 d-cache-line-size = <64>;
92 d-cache-sets = <128>;
93 next-level-cache = <&l2_0>;
94 performance-domains = <&performance 0>;
95 capacity-dmips-mhz = <427>;
93743d24 96 #cooling-cells = <2>;
53633a89
TR		 97 };
98
99 cpu2: cpu@200 {
100 device_type = "cpu";
101 compatible = "arm,cortex-a55";
102 reg = <0x200>;
103 enable-method = "psci";
104 clock-frequency = <1701000000>;
105 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
106 i-cache-size = <32768>;
107 i-cache-line-size = <64>;
108 i-cache-sets = <128>;
109 d-cache-size = <32768>;
110 d-cache-line-size = <64>;
111 d-cache-sets = <128>;
112 next-level-cache = <&l2_0>;
113 performance-domains = <&performance 0>;
114 capacity-dmips-mhz = <427>;
93743d24 115 #cooling-cells = <2>;
53633a89
TR		 116 };
117
118 cpu3: cpu@300 {
119 device_type = "cpu";
120 compatible = "arm,cortex-a55";
121 reg = <0x300>;
122 enable-method = "psci";
123 clock-frequency = <1701000000>;
124 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
125 i-cache-size = <32768>;
126 i-cache-line-size = <64>;
127 i-cache-sets = <128>;
128 d-cache-size = <32768>;
129 d-cache-line-size = <64>;
130 d-cache-sets = <128>;
131 next-level-cache = <&l2_0>;
132 performance-domains = <&performance 0>;
133 capacity-dmips-mhz = <427>;
93743d24 134 #cooling-cells = <2>;
53633a89
TR		 135 };
136
137 cpu4: cpu@400 {
138 device_type = "cpu";
139 compatible = "arm,cortex-a76";
140 reg = <0x400>;
141 enable-method = "psci";
142 clock-frequency = <2171000000>;
143 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
144 i-cache-size = <65536>;
145 i-cache-line-size = <64>;
146 i-cache-sets = <256>;
147 d-cache-size = <65536>;
148 d-cache-line-size = <64>;
149 d-cache-sets = <256>;
150 next-level-cache = <&l2_1>;
151 performance-domains = <&performance 1>;
152 capacity-dmips-mhz = <1024>;
93743d24 153 #cooling-cells = <2>;
53633a89
TR		 154 };
155
156 cpu5: cpu@500 {
157 device_type = "cpu";
158 compatible = "arm,cortex-a76";
159 reg = <0x500>;
160 enable-method = "psci";
161 clock-frequency = <2171000000>;
162 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
163 i-cache-size = <65536>;
164 i-cache-line-size = <64>;
165 i-cache-sets = <256>;
166 d-cache-size = <65536>;
167 d-cache-line-size = <64>;
168 d-cache-sets = <256>;
169 next-level-cache = <&l2_1>;
170 performance-domains = <&performance 1>;
171 capacity-dmips-mhz = <1024>;
93743d24 172 #cooling-cells = <2>;
53633a89
TR		 173 };
174
175 cpu6: cpu@600 {
176 device_type = "cpu";
177 compatible = "arm,cortex-a76";
178 reg = <0x600>;
179 enable-method = "psci";
180 clock-frequency = <2171000000>;
181 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
182 i-cache-size = <65536>;
183 i-cache-line-size = <64>;
184 i-cache-sets = <256>;
185 d-cache-size = <65536>;
186 d-cache-line-size = <64>;
187 d-cache-sets = <256>;
188 next-level-cache = <&l2_1>;
189 performance-domains = <&performance 1>;
190 capacity-dmips-mhz = <1024>;
93743d24 191 #cooling-cells = <2>;
53633a89
TR		 192 };
193
194 cpu7: cpu@700 {
195 device_type = "cpu";
196 compatible = "arm,cortex-a76";
197 reg = <0x700>;
198 enable-method = "psci";
199 clock-frequency = <2171000000>;
200 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
201 i-cache-size = <65536>;
202 i-cache-line-size = <64>;
203 i-cache-sets = <256>;
204 d-cache-size = <65536>;
205 d-cache-line-size = <64>;
206 d-cache-sets = <256>;
207 next-level-cache = <&l2_1>;
208 performance-domains = <&performance 1>;
209 capacity-dmips-mhz = <1024>;
93743d24 210 #cooling-cells = <2>;
53633a89
TR		 211 };
212
213 cpu-map {
214 cluster0 {
215 core0 {
216 cpu = <&cpu0>;
217 };
218 core1 {
219 cpu = <&cpu1>;
220 };
221 core2 {
222 cpu = <&cpu2>;
223 };
224 core3 {
225 cpu = <&cpu3>;
226 };
227 core4 {
228 cpu = <&cpu4>;
229 };
230 core5 {
231 cpu = <&cpu5>;
232 };
233 core6 {
234 cpu = <&cpu6>;
235 };
236 core7 {
237 cpu = <&cpu7>;
238 };
239 };
240 };
241
242 l2_0: l2-cache0 {
243 compatible = "cache";
244 cache-level = <2>;
245 cache-size = <131072>;
246 cache-line-size = <64>;
247 cache-sets = <512>;
248 next-level-cache = <&l3_0>;
249 cache-unified;
250 };
251
252 l2_1: l2-cache1 {
253 compatible = "cache";
254 cache-level = <2>;
255 cache-size = <262144>;
256 cache-line-size = <64>;
257 cache-sets = <512>;
258 next-level-cache = <&l3_0>;
259 cache-unified;
260 };
261
262 l3_0: l3-cache {
263 compatible = "cache";
264 cache-level = <3>;
265 cache-size = <2097152>;
266 cache-line-size = <64>;
267 cache-sets = <2048>;
268 cache-unified;
269 };
270
271 idle-states {
272 entry-method = "psci";
273 cpu_ret_l: cpu-retention-l {
274 compatible = "arm,idle-state";
275 arm,psci-suspend-param = <0x00010001>;
276 local-timer-stop;
277 entry-latency-us = <55>;
278 exit-latency-us = <140>;
279 min-residency-us = <780>;
280 };
281 cpu_ret_b: cpu-retention-b {
282 compatible = "arm,idle-state";
283 arm,psci-suspend-param = <0x00010001>;
284 local-timer-stop;
285 entry-latency-us = <35>;
286 exit-latency-us = <145>;
287 min-residency-us = <720>;
288 };
289 cpu_off_l: cpu-off-l {
290 compatible = "arm,idle-state";
291 arm,psci-suspend-param = <0x01010002>;
292 local-timer-stop;
293 entry-latency-us = <60>;
294 exit-latency-us = <155>;
295 min-residency-us = <860>;
296 };
297 cpu_off_b: cpu-off-b {
298 compatible = "arm,idle-state";
299 arm,psci-suspend-param = <0x01010002>;
300 local-timer-stop;
301 entry-latency-us = <40>;
302 exit-latency-us = <155>;
303 min-residency-us = <780>;
304 };
305 };
306 };
307
308 pmu-a55 {
309 compatible = "arm,cortex-a55-pmu";
310 interrupt-parent = <&gic>;
311 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
312 };
313
314 pmu-a76 {
315 compatible = "arm,cortex-a76-pmu";
316 interrupt-parent = <&gic>;
317 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
318 };
319
320 psci {
321 compatible = "arm,psci-1.0";
322 method = "smc";
323 };
324
325 timer: timer {
326 compatible = "arm,armv8-timer";
327 interrupt-parent = <&gic>;
328 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
329 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
330 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
331 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
332 clock-frequency = <13000000>;
333 };
334
335 gpu_opp_table: opp-table-0 {
336 compatible = "operating-points-v2";
337 opp-shared;
338
339 opp-358000000 {
340 opp-hz = /bits/ 64 <358000000>;
341 opp-microvolt = <606250>;
342 };
343
344 opp-399000000 {
345 opp-hz = /bits/ 64 <399000000>;
346 opp-microvolt = <618750>;
347 };
348
349 opp-440000000 {
350 opp-hz = /bits/ 64 <440000000>;
351 opp-microvolt = <631250>;
352 };
353
354 opp-482000000 {
355 opp-hz = /bits/ 64 <482000000>;
356 opp-microvolt = <643750>;
357 };
358
359 opp-523000000 {
360 opp-hz = /bits/ 64 <523000000>;
361 opp-microvolt = <656250>;
362 };
363
364 opp-564000000 {
365 opp-hz = /bits/ 64 <564000000>;
366 opp-microvolt = <668750>;
367 };
368
369 opp-605000000 {
370 opp-hz = /bits/ 64 <605000000>;
371 opp-microvolt = <681250>;
372 };
373
374 opp-647000000 {
375 opp-hz = /bits/ 64 <647000000>;
376 opp-microvolt = <693750>;
377 };
378
379 opp-688000000 {
380 opp-hz = /bits/ 64 <688000000>;
381 opp-microvolt = <706250>;
382 };
383
384 opp-724000000 {
385 opp-hz = /bits/ 64 <724000000>;
386 opp-microvolt = <725000>;
387 };
388
389 opp-748000000 {
390 opp-hz = /bits/ 64 <748000000>;
391 opp-microvolt = <737500>;
392 };
393
394 opp-772000000 {
395 opp-hz = /bits/ 64 <772000000>;
396 opp-microvolt = <750000>;
397 };
398
399 opp-795000000 {
400 opp-hz = /bits/ 64 <795000000>;
401 opp-microvolt = <762500>;
402 };
403
404 opp-819000000 {
405 opp-hz = /bits/ 64 <819000000>;
406 opp-microvolt = <775000>;
407 };
408
409 opp-843000000 {
410 opp-hz = /bits/ 64 <843000000>;
411 opp-microvolt = <787500>;
412 };
413
414 opp-866000000 {
415 opp-hz = /bits/ 64 <866000000>;
416 opp-microvolt = <800000>;
417 };
418 };
419
420 soc {
421 #address-cells = <2>;
422 #size-cells = <2>;
423 compatible = "simple-bus";
424 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
425 ranges;
426
427 performance: performance-controller@11bc10 {
428 compatible = "mediatek,cpufreq-hw";
429 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
430 #performance-domain-cells = <1>;
431 };
432
433 gic: interrupt-controller@c000000 {
434 compatible = "arm,gic-v3";
435 #interrupt-cells = <4>;
436 #redistributor-regions = <1>;
437 interrupt-parent = <&gic>;
438 interrupt-controller;
439 reg = <0 0x0c000000 0 0x40000>,
440 <0 0x0c040000 0 0x200000>;
441 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
442
443 ppi-partitions {
444 ppi_cluster0: interrupt-partition-0 {
445 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
446 };
447 ppi_cluster1: interrupt-partition-1 {
448 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
449 };
450 };
451 };
452
453 topckgen: syscon@10000000 {
454 compatible = "mediatek,mt8192-topckgen", "syscon";
455 reg = <0 0x10000000 0 0x1000>;
456 #clock-cells = <1>;
457 };
458
459 infracfg: syscon@10001000 {
460 compatible = "mediatek,mt8192-infracfg", "syscon";
461 reg = <0 0x10001000 0 0x1000>;
462 #clock-cells = <1>;
463 #reset-cells = <1>;
464 };
465
466 pericfg: syscon@10003000 {
467 compatible = "mediatek,mt8192-pericfg", "syscon";
468 reg = <0 0x10003000 0 0x1000>;
469 #clock-cells = <1>;
470 };
471
472 pio: pinctrl@10005000 {
473 compatible = "mediatek,mt8192-pinctrl";
474 reg = <0 0x10005000 0 0x1000>,
475 <0 0x11c20000 0 0x1000>,
476 <0 0x11d10000 0 0x1000>,
477 <0 0x11d30000 0 0x1000>,
478 <0 0x11d40000 0 0x1000>,
479 <0 0x11e20000 0 0x1000>,
480 <0 0x11e70000 0 0x1000>,
481 <0 0x11ea0000 0 0x1000>,
482 <0 0x11f20000 0 0x1000>,
483 <0 0x11f30000 0 0x1000>,
484 <0 0x1000b000 0 0x1000>;
485 reg-names = "iocfg0", "iocfg_rm", "iocfg_bm",
486 "iocfg_bl", "iocfg_br", "iocfg_lm",
487 "iocfg_lb", "iocfg_rt", "iocfg_lt",
488 "iocfg_tl", "eint";
489 gpio-controller;
490 #gpio-cells = <2>;
491 gpio-ranges = <&pio 0 0 220>;
492 interrupt-controller;
493 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>;
494 #interrupt-cells = <2>;
495 };
496
497 scpsys: syscon@10006000 {
498 compatible = "mediatek,mt8192-scpsys", "syscon", "simple-mfd";
499 reg = <0 0x10006000 0 0x1000>;
500
501 /* System Power Manager */
502 spm: power-controller {
503 compatible = "mediatek,mt8192-power-controller";
504 #address-cells = <1>;
505 #size-cells = <0>;
506 #power-domain-cells = <1>;
507
508 /* power domain of the SoC */
509 power-domain@MT8192_POWER_DOMAIN_AUDIO {
510 reg = <MT8192_POWER_DOMAIN_AUDIO>;
511 clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
512 <&infracfg CLK_INFRA_AUDIO_26M_B>,
513 <&infracfg CLK_INFRA_AUDIO>;
514 clock-names = "audio", "audio1", "audio2";
515 mediatek,infracfg = <&infracfg>;
516 #power-domain-cells = <0>;
517 };
518
519 power-domain@MT8192_POWER_DOMAIN_CONN {
520 reg = <MT8192_POWER_DOMAIN_CONN>;
521 clocks = <&infracfg CLK_INFRA_PMIC_CONN>;
522 clock-names = "conn";
523 mediatek,infracfg = <&infracfg>;
524 #power-domain-cells = <0>;
525 };
526
527 mfg0: power-domain@MT8192_POWER_DOMAIN_MFG0 {
528 reg = <MT8192_POWER_DOMAIN_MFG0>;
529 clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>,
530 <&topckgen CLK_TOP_MFG_REF_SEL>;
531 clock-names = "mfg", "alt";
532 #address-cells = <1>;
533 #size-cells = <0>;
534 #power-domain-cells = <1>;
535
536 mfg1: power-domain@MT8192_POWER_DOMAIN_MFG1 {
537 reg = <MT8192_POWER_DOMAIN_MFG1>;
538 mediatek,infracfg = <&infracfg>;
539 #address-cells = <1>;
540 #size-cells = <0>;
541 #power-domain-cells = <1>;
542
543 power-domain@MT8192_POWER_DOMAIN_MFG2 {
544 reg = <MT8192_POWER_DOMAIN_MFG2>;
545 #power-domain-cells = <0>;
546 };
547
548 power-domain@MT8192_POWER_DOMAIN_MFG3 {
549 reg = <MT8192_POWER_DOMAIN_MFG3>;
550 #power-domain-cells = <0>;
551 };
552
553 power-domain@MT8192_POWER_DOMAIN_MFG4 {
554 reg = <MT8192_POWER_DOMAIN_MFG4>;
555 #power-domain-cells = <0>;
556 };
557
558 power-domain@MT8192_POWER_DOMAIN_MFG5 {
559 reg = <MT8192_POWER_DOMAIN_MFG5>;
560 #power-domain-cells = <0>;
561 };
562
563 power-domain@MT8192_POWER_DOMAIN_MFG6 {
564 reg = <MT8192_POWER_DOMAIN_MFG6>;
565 #power-domain-cells = <0>;
566 };
567 };
568 };
569
570 power-domain@MT8192_POWER_DOMAIN_DISP {
571 reg = <MT8192_POWER_DOMAIN_DISP>;
572 clocks = <&topckgen CLK_TOP_DISP_SEL>,
573 <&mmsys CLK_MM_SMI_INFRA>,
574 <&mmsys CLK_MM_SMI_COMMON>,
575 <&mmsys CLK_MM_SMI_GALS>,
576 <&mmsys CLK_MM_SMI_IOMMU>;
577 clock-names = "disp", "disp-0", "disp-1", "disp-2",
578 "disp-3";
579 mediatek,infracfg = <&infracfg>;
580 #address-cells = <1>;
581 #size-cells = <0>;
582 #power-domain-cells = <1>;
583
584 power-domain@MT8192_POWER_DOMAIN_IPE {
585 reg = <MT8192_POWER_DOMAIN_IPE>;
586 clocks = <&topckgen CLK_TOP_IPE_SEL>,
587 <&ipesys CLK_IPE_LARB19>,
588 <&ipesys CLK_IPE_LARB20>,
589 <&ipesys CLK_IPE_SMI_SUBCOM>,
590 <&ipesys CLK_IPE_GALS>;
591 clock-names = "ipe", "ipe-0", "ipe-1", "ipe-2",
592 "ipe-3";
593 mediatek,infracfg = <&infracfg>;
594 #power-domain-cells = <0>;
595 };
596
597 power-domain@MT8192_POWER_DOMAIN_ISP {
598 reg = <MT8192_POWER_DOMAIN_ISP>;
599 clocks = <&topckgen CLK_TOP_IMG1_SEL>,
600 <&imgsys CLK_IMG_LARB9>,
601 <&imgsys CLK_IMG_GALS>;
602 clock-names = "isp", "isp-0", "isp-1";
603 mediatek,infracfg = <&infracfg>;
604 #power-domain-cells = <0>;
605 };
606
607 power-domain@MT8192_POWER_DOMAIN_ISP2 {
608 reg = <MT8192_POWER_DOMAIN_ISP2>;
609 clocks = <&topckgen CLK_TOP_IMG2_SEL>,
610 <&imgsys2 CLK_IMG2_LARB11>,
611 <&imgsys2 CLK_IMG2_GALS>;
612 clock-names = "isp2", "isp2-0", "isp2-1";
613 mediatek,infracfg = <&infracfg>;
614 #power-domain-cells = <0>;
615 };
616
617 power-domain@MT8192_POWER_DOMAIN_MDP {
618 reg = <MT8192_POWER_DOMAIN_MDP>;
619 clocks = <&topckgen CLK_TOP_MDP_SEL>,
620 <&mdpsys CLK_MDP_SMI0>;
621 clock-names = "mdp", "mdp-0";
622 mediatek,infracfg = <&infracfg>;
623 #power-domain-cells = <0>;
624 };
625
626 power-domain@MT8192_POWER_DOMAIN_VENC {
627 reg = <MT8192_POWER_DOMAIN_VENC>;
628 clocks = <&topckgen CLK_TOP_VENC_SEL>,
629 <&vencsys CLK_VENC_SET1_VENC>;
630 clock-names = "venc", "venc-0";
631 mediatek,infracfg = <&infracfg>;
632 #power-domain-cells = <0>;
633 };
634
635 power-domain@MT8192_POWER_DOMAIN_VDEC {
636 reg = <MT8192_POWER_DOMAIN_VDEC>;
637 clocks = <&topckgen CLK_TOP_VDEC_SEL>,
638 <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
639 <&vdecsys_soc CLK_VDEC_SOC_LAT>,
640 <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
641 clock-names = "vdec", "vdec-0", "vdec-1", "vdec-2";
642 mediatek,infracfg = <&infracfg>;
643 #address-cells = <1>;
644 #size-cells = <0>;
645 #power-domain-cells = <1>;
646
647 power-domain@MT8192_POWER_DOMAIN_VDEC2 {
648 reg = <MT8192_POWER_DOMAIN_VDEC2>;
649 clocks = <&vdecsys CLK_VDEC_VDEC>,
650 <&vdecsys CLK_VDEC_LAT>,
651 <&vdecsys CLK_VDEC_LARB1>;
652 clock-names = "vdec2-0", "vdec2-1",
653 "vdec2-2";
654 #power-domain-cells = <0>;
655 };
656 };
657
658 power-domain@MT8192_POWER_DOMAIN_CAM {
659 reg = <MT8192_POWER_DOMAIN_CAM>;
660 clocks = <&topckgen CLK_TOP_CAM_SEL>,
661 <&camsys CLK_CAM_LARB13>,
662 <&camsys CLK_CAM_LARB14>,
663 <&camsys CLK_CAM_CCU_GALS>,
664 <&camsys CLK_CAM_CAM2MM_GALS>;
665 clock-names = "cam", "cam-0", "cam-1", "cam-2",
666 "cam-3";
667 mediatek,infracfg = <&infracfg>;
668 #address-cells = <1>;
669 #size-cells = <0>;
670 #power-domain-cells = <1>;
671
672 power-domain@MT8192_POWER_DOMAIN_CAM_RAWA {
673 reg = <MT8192_POWER_DOMAIN_CAM_RAWA>;
674 clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>;
675 clock-names = "cam_rawa-0";
676 #power-domain-cells = <0>;
677 };
678
679 power-domain@MT8192_POWER_DOMAIN_CAM_RAWB {
680 reg = <MT8192_POWER_DOMAIN_CAM_RAWB>;
681 clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>;
682 clock-names = "cam_rawb-0";
683 #power-domain-cells = <0>;
684 };
685
686 power-domain@MT8192_POWER_DOMAIN_CAM_RAWC {
687 reg = <MT8192_POWER_DOMAIN_CAM_RAWC>;
688 clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>;
689 clock-names = "cam_rawc-0";
690 #power-domain-cells = <0>;
691 };
692 };
693 };
694 };
695 };
696
697 watchdog: watchdog@10007000 {
698 compatible = "mediatek,mt8192-wdt";
699 reg = <0 0x10007000 0 0x100>;
700 #reset-cells = <1>;
701 };
702
703 apmixedsys: syscon@1000c000 {
704 compatible = "mediatek,mt8192-apmixedsys", "syscon";
705 reg = <0 0x1000c000 0 0x1000>;
706 #clock-cells = <1>;
707 };
708
709 systimer: timer@10017000 {
710 compatible = "mediatek,mt8192-timer",
711 "mediatek,mt6765-timer";
712 reg = <0 0x10017000 0 0x1000>;
713 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>;
714 clocks = <&clk13m>;
715 };
716
717 pwrap: pwrap@10026000 {
718 compatible = "mediatek,mt6873-pwrap";
719 reg = <0 0x10026000 0 0x1000>;
720 reg-names = "pwrap";
721 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
722 clocks = <&infracfg CLK_INFRA_PMIC_AP>,
723 <&infracfg CLK_INFRA_PMIC_TMR>;
724 clock-names = "spi", "wrap";
725 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
726 assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
727 };
728
729 spmi: spmi@10027000 {
730 compatible = "mediatek,mt6873-spmi";
731 reg = <0 0x10027000 0 0x000e00>,
732 <0 0x10029000 0 0x000100>;
733 reg-names = "pmif", "spmimst";
734 clocks = <&infracfg CLK_INFRA_PMIC_AP>,
735 <&infracfg CLK_INFRA_PMIC_TMR>,
736 <&topckgen CLK_TOP_SPMI_MST_SEL>;
737 clock-names = "pmif_sys_ck",
738 "pmif_tmr_ck",
739 "spmimst_clk_mux";
740 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
741 assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
742 };
743
744 gce: mailbox@10228000 {
745 compatible = "mediatek,mt8192-gce";
746 reg = <0 0x10228000 0 0x4000>;
747 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
748 #mbox-cells = <2>;
749 clocks = <&infracfg CLK_INFRA_GCE>;
750 clock-names = "gce";
751 };
752
753 scp_adsp: clock-controller@10720000 {
754 compatible = "mediatek,mt8192-scp_adsp";
755 reg = <0 0x10720000 0 0x1000>;
756 #clock-cells = <1>;
757 /* power domain dependency not upstreamed */
758 status = "fail";
759 };
760
761 uart0: serial@11002000 {
762 compatible = "mediatek,mt8192-uart",
763 "mediatek,mt6577-uart";
764 reg = <0 0x11002000 0 0x1000>;
765 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
766 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
767 clock-names = "baud", "bus";
768 status = "disabled";
769 };
770
771 uart1: serial@11003000 {
772 compatible = "mediatek,mt8192-uart",
773 "mediatek,mt6577-uart";
774 reg = <0 0x11003000 0 0x1000>;
775 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
776 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
777 clock-names = "baud", "bus";
778 status = "disabled";
779 };
780
781 imp_iic_wrap_c: clock-controller@11007000 {
782 compatible = "mediatek,mt8192-imp_iic_wrap_c";
783 reg = <0 0x11007000 0 0x1000>;
784 #clock-cells = <1>;
785 };
786
787 spi0: spi@1100a000 {
788 compatible = "mediatek,mt8192-spi",
789 "mediatek,mt6765-spi";
790 #address-cells = <1>;
791 #size-cells = <0>;
792 reg = <0 0x1100a000 0 0x1000>;
793 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>;
794 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
795 <&topckgen CLK_TOP_SPI_SEL>,
796 <&infracfg CLK_INFRA_SPI0>;
797 clock-names = "parent-clk", "sel-clk", "spi-clk";
798 status = "disabled";
799 };
800
93743d24
TR		 801 lvts_ap: thermal-sensor@1100b000 {
802 compatible = "mediatek,mt8192-lvts-ap";
803 reg = <0 0x1100b000 0 0xc00>;
804 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>;
805 clocks = <&infracfg CLK_INFRA_THERM>;
806 resets = <&infracfg MT8192_INFRA_RST0_THERM_CTRL_SWRST>;
807 nvmem-cells = <&lvts_e_data1>;
808 nvmem-cell-names = "lvts-calib-data-1";
809 #thermal-sensor-cells = <1>;
810 };
811
812 svs: svs@1100bc00 {
813 compatible = "mediatek,mt8192-svs";
814 reg = <0 0x1100bc00 0 0x400>;
815 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH 0>;
816 clocks = <&infracfg CLK_INFRA_THERM>;
817 clock-names = "main";
818 nvmem-cells = <&svs_calibration>, <&lvts_e_data1>;
819 nvmem-cell-names = "svs-calibration-data", "t-calibration-data";
820 resets = <&infracfg MT8192_INFRA_RST3_THERM_CTRL_PTP_SWRST>;
821 reset-names = "svs_rst";
822 };
823
53633a89
TR		 824 pwm0: pwm@1100e000 {
825 compatible = "mediatek,mt8183-disp-pwm";
826 reg = <0 0x1100e000 0 0x1000>;
827 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>;
828 #pwm-cells = <2>;
829 clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>,
830 <&infracfg CLK_INFRA_DISP_PWM>;
831 clock-names = "main", "mm";
832 status = "disabled";
833 };
834
835 spi1: spi@11010000 {
836 compatible = "mediatek,mt8192-spi",
837 "mediatek,mt6765-spi";
838 #address-cells = <1>;
839 #size-cells = <0>;
840 reg = <0 0x11010000 0 0x1000>;
841 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>;
842 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
843 <&topckgen CLK_TOP_SPI_SEL>,
844 <&infracfg CLK_INFRA_SPI1>;
845 clock-names = "parent-clk", "sel-clk", "spi-clk";
846 status = "disabled";
847 };
848
849 spi2: spi@11012000 {
850 compatible = "mediatek,mt8192-spi",
851 "mediatek,mt6765-spi";
852 #address-cells = <1>;
853 #size-cells = <0>;
854 reg = <0 0x11012000 0 0x1000>;
855 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>;
856 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
857 <&topckgen CLK_TOP_SPI_SEL>,
858 <&infracfg CLK_INFRA_SPI2>;
859 clock-names = "parent-clk", "sel-clk", "spi-clk";
860 status = "disabled";
861 };
862
863 spi3: spi@11013000 {
864 compatible = "mediatek,mt8192-spi",
865 "mediatek,mt6765-spi";
866 #address-cells = <1>;
867 #size-cells = <0>;
868 reg = <0 0x11013000 0 0x1000>;
869 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>;
870 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
871 <&topckgen CLK_TOP_SPI_SEL>,
872 <&infracfg CLK_INFRA_SPI3>;
873 clock-names = "parent-clk", "sel-clk", "spi-clk";
874 status = "disabled";
875 };
876
877 spi4: spi@11018000 {
878 compatible = "mediatek,mt8192-spi",
879 "mediatek,mt6765-spi";
880 #address-cells = <1>;
881 #size-cells = <0>;
882 reg = <0 0x11018000 0 0x1000>;
883 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>;
884 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
885 <&topckgen CLK_TOP_SPI_SEL>,
886 <&infracfg CLK_INFRA_SPI4>;
887 clock-names = "parent-clk", "sel-clk", "spi-clk";
888 status = "disabled";
889 };
890
891 spi5: spi@11019000 {
892 compatible = "mediatek,mt8192-spi",
893 "mediatek,mt6765-spi";
894 #address-cells = <1>;
895 #size-cells = <0>;
896 reg = <0 0x11019000 0 0x1000>;
897 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>;
898 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
899 <&topckgen CLK_TOP_SPI_SEL>,
900 <&infracfg CLK_INFRA_SPI5>;
901 clock-names = "parent-clk", "sel-clk", "spi-clk";
902 status = "disabled";
903 };
904
905 spi6: spi@1101d000 {
906 compatible = "mediatek,mt8192-spi",
907 "mediatek,mt6765-spi";
908 #address-cells = <1>;
909 #size-cells = <0>;
910 reg = <0 0x1101d000 0 0x1000>;
911 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>;
912 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
913 <&topckgen CLK_TOP_SPI_SEL>,
914 <&infracfg CLK_INFRA_SPI6>;
915 clock-names = "parent-clk", "sel-clk", "spi-clk";
916 status = "disabled";
917 };
918
919 spi7: spi@1101e000 {
920 compatible = "mediatek,mt8192-spi",
921 "mediatek,mt6765-spi";
922 #address-cells = <1>;
923 #size-cells = <0>;
924 reg = <0 0x1101e000 0 0x1000>;
925 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>;
926 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
927 <&topckgen CLK_TOP_SPI_SEL>,
928 <&infracfg CLK_INFRA_SPI7>;
929 clock-names = "parent-clk", "sel-clk", "spi-clk";
930 status = "disabled";
931 };
932
933 scp: scp@10500000 {
934 compatible = "mediatek,mt8192-scp";
935 reg = <0 0x10500000 0 0x100000>,
936 <0 0x10720000 0 0xe0000>,
937 <0 0x10700000 0 0x8000>;
938 reg-names = "sram", "cfg", "l1tcm";
939 interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>;
940 clocks = <&infracfg CLK_INFRA_SCPSYS>;
941 clock-names = "main";
942 status = "disabled";
943 };
944
945 xhci: usb@11200000 {
946 compatible = "mediatek,mt8192-xhci",
947 "mediatek,mtk-xhci";
948 reg = <0 0x11200000 0 0x1000>,
949 <0 0x11203e00 0 0x0100>;
950 reg-names = "mac", "ippc";
951 interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
952 interrupt-names = "host";
953 phys = <&u2port0 PHY_TYPE_USB2>,
954 <&u3port0 PHY_TYPE_USB3>;
955 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>,
956 <&topckgen CLK_TOP_SSUSB_XHCI_SEL>;
957 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
958 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
959 clocks = <&infracfg CLK_INFRA_SSUSB>,
960 <&apmixedsys CLK_APMIXED_USBPLL>,
961 <&clk26m>,
962 <&clk26m>,
963 <&infracfg CLK_INFRA_SSUSB_XHCI>;
964 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
965 "xhci_ck";
966 wakeup-source;
967 mediatek,syscon-wakeup = <&pericfg 0x420 102>;
968 status = "disabled";
969 };
970
971 audsys: syscon@11210000 {
972 compatible = "mediatek,mt8192-audsys", "syscon";
973 reg = <0 0x11210000 0 0x2000>;
974 #clock-cells = <1>;
975
976 afe: mt8192-afe-pcm {
977 compatible = "mediatek,mt8192-audio";
978 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>;
979 resets = <&watchdog 17>;
980 reset-names = "audiosys";
981 mediatek,apmixedsys = <&apmixedsys>;
982 mediatek,infracfg = <&infracfg>;
983 mediatek,topckgen = <&topckgen>;
984 power-domains = <&spm MT8192_POWER_DOMAIN_AUDIO>;
985 clocks = <&audsys CLK_AUD_AFE>,
986 <&audsys CLK_AUD_DAC>,
987 <&audsys CLK_AUD_DAC_PREDIS>,
988 <&audsys CLK_AUD_ADC>,
989 <&audsys CLK_AUD_ADDA6_ADC>,
990 <&audsys CLK_AUD_22M>,
991 <&audsys CLK_AUD_24M>,
992 <&audsys CLK_AUD_APLL_TUNER>,
993 <&audsys CLK_AUD_APLL2_TUNER>,
994 <&audsys CLK_AUD_TDM>,
995 <&audsys CLK_AUD_TML>,
996 <&audsys CLK_AUD_NLE>,
997 <&audsys CLK_AUD_DAC_HIRES>,
998 <&audsys CLK_AUD_ADC_HIRES>,
999 <&audsys CLK_AUD_ADC_HIRES_TML>,
1000 <&audsys CLK_AUD_ADDA6_ADC_HIRES>,
1001 <&audsys CLK_AUD_3RD_DAC>,
1002 <&audsys CLK_AUD_3RD_DAC_PREDIS>,
1003 <&audsys CLK_AUD_3RD_DAC_TML>,
1004 <&audsys CLK_AUD_3RD_DAC_HIRES>,
1005 <&infracfg CLK_INFRA_AUDIO>,
1006 <&infracfg CLK_INFRA_AUDIO_26M_B>,
1007 <&topckgen CLK_TOP_AUDIO_SEL>,
1008 <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
1009 <&topckgen CLK_TOP_MAINPLL_D4_D4>,
1010 <&topckgen CLK_TOP_AUD_1_SEL>,
1011 <&topckgen CLK_TOP_APLL1>,
1012 <&topckgen CLK_TOP_AUD_2_SEL>,
1013 <&topckgen CLK_TOP_APLL2>,
1014 <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
1015 <&topckgen CLK_TOP_APLL1_D4>,
1016 <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
1017 <&topckgen CLK_TOP_APLL2_D4>,
1018 <&topckgen CLK_TOP_APLL_I2S0_M_SEL>,
1019 <&topckgen CLK_TOP_APLL_I2S1_M_SEL>,
1020 <&topckgen CLK_TOP_APLL_I2S2_M_SEL>,
1021 <&topckgen CLK_TOP_APLL_I2S3_M_SEL>,
1022 <&topckgen CLK_TOP_APLL_I2S4_M_SEL>,
1023 <&topckgen CLK_TOP_APLL_I2S5_M_SEL>,
1024 <&topckgen CLK_TOP_APLL_I2S6_M_SEL>,
1025 <&topckgen CLK_TOP_APLL_I2S7_M_SEL>,
1026 <&topckgen CLK_TOP_APLL_I2S8_M_SEL>,
1027 <&topckgen CLK_TOP_APLL_I2S9_M_SEL>,
1028 <&topckgen CLK_TOP_APLL12_DIV0>,
1029 <&topckgen CLK_TOP_APLL12_DIV1>,
1030 <&topckgen CLK_TOP_APLL12_DIV2>,
1031 <&topckgen CLK_TOP_APLL12_DIV3>,
1032 <&topckgen CLK_TOP_APLL12_DIV4>,
1033 <&topckgen CLK_TOP_APLL12_DIVB>,
1034 <&topckgen CLK_TOP_APLL12_DIV5>,
1035 <&topckgen CLK_TOP_APLL12_DIV6>,
1036 <&topckgen CLK_TOP_APLL12_DIV7>,
1037 <&topckgen CLK_TOP_APLL12_DIV8>,
1038 <&topckgen CLK_TOP_APLL12_DIV9>,
1039 <&topckgen CLK_TOP_AUDIO_H_SEL>,
1040 <&clk26m>;
1041 clock-names = "aud_afe_clk",
1042 "aud_dac_clk",
1043 "aud_dac_predis_clk",
1044 "aud_adc_clk",
1045 "aud_adda6_adc_clk",
1046 "aud_apll22m_clk",
1047 "aud_apll24m_clk",
1048 "aud_apll1_tuner_clk",
1049 "aud_apll2_tuner_clk",
1050 "aud_tdm_clk",
1051 "aud_tml_clk",
1052 "aud_nle",
1053 "aud_dac_hires_clk",
1054 "aud_adc_hires_clk",
1055 "aud_adc_hires_tml",
1056 "aud_adda6_adc_hires_clk",
1057 "aud_3rd_dac_clk",
1058 "aud_3rd_dac_predis_clk",
1059 "aud_3rd_dac_tml",
1060 "aud_3rd_dac_hires_clk",
1061 "aud_infra_clk",
1062 "aud_infra_26m_clk",
1063 "top_mux_audio",
1064 "top_mux_audio_int",
1065 "top_mainpll_d4_d4",
1066 "top_mux_aud_1",
1067 "top_apll1_ck",
1068 "top_mux_aud_2",
1069 "top_apll2_ck",
1070 "top_mux_aud_eng1",
1071 "top_apll1_d4",
1072 "top_mux_aud_eng2",
1073 "top_apll2_d4",
1074 "top_i2s0_m_sel",
1075 "top_i2s1_m_sel",
1076 "top_i2s2_m_sel",
1077 "top_i2s3_m_sel",
1078 "top_i2s4_m_sel",
1079 "top_i2s5_m_sel",
1080 "top_i2s6_m_sel",
1081 "top_i2s7_m_sel",
1082 "top_i2s8_m_sel",
1083 "top_i2s9_m_sel",
1084 "top_apll12_div0",
1085 "top_apll12_div1",
1086 "top_apll12_div2",
1087 "top_apll12_div3",
1088 "top_apll12_div4",
1089 "top_apll12_divb",
1090 "top_apll12_div5",
1091 "top_apll12_div6",
1092 "top_apll12_div7",
1093 "top_apll12_div8",
1094 "top_apll12_div9",
1095 "top_mux_audio_h",
1096 "top_clk26m_clk";
1097 };
1098 };
1099
1100 pcie: pcie@11230000 {
1101 compatible = "mediatek,mt8192-pcie";
1102 device_type = "pci";
1103 reg = <0 0x11230000 0 0x2000>;
1104 reg-names = "pcie-mac";
1105 #address-cells = <3>;
1106 #size-cells = <2>;
1107 clocks = <&infracfg CLK_INFRA_PCIE_PL_P_250M>,
1108 <&infracfg CLK_INFRA_PCIE_TL_26M>,
1109 <&infracfg CLK_INFRA_PCIE_TL_96M>,
1110 <&infracfg CLK_INFRA_PCIE_TL_32K>,
1111 <&infracfg CLK_INFRA_PCIE_PERI_26M>,
1112 <&infracfg CLK_INFRA_PCIE_TOP_H_133M>;
1113 clock-names = "pl_250m", "tl_26m", "tl_96m",
1114 "tl_32k", "peri_26m", "top_133m";
1115 assigned-clocks = <&topckgen CLK_TOP_TL_SEL>;
1116 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>;
1117 interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
1118 bus-range = <0x00 0xff>;
1119 ranges = <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>,
1120 <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>;
1121 #interrupt-cells = <1>;
1122 interrupt-map-mask = <0 0 0 7>;
1123 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
1124 <0 0 0 2 &pcie_intc0 1>,
1125 <0 0 0 3 &pcie_intc0 2>,
1126 <0 0 0 4 &pcie_intc0 3>;
1127
1128 pcie_intc0: interrupt-controller {
1129 interrupt-controller;
1130 #address-cells = <0>;
1131 #interrupt-cells = <1>;
1132 };
1133 };
1134
1135 nor_flash: spi@11234000 {
1136 compatible = "mediatek,mt8192-nor";
1137 reg = <0 0x11234000 0 0xe0>;
1138 interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0>;
1139 clocks = <&topckgen CLK_TOP_SFLASH_SEL>,
1140 <&infracfg CLK_INFRA_FLASHIF_SFLASH>,
1141 <&infracfg CLK_INFRA_FLASHIF_TOP_H_133M>;
1142 clock-names = "spi", "sf", "axi";
1143 assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>;
1144 assigned-clock-parents = <&clk26m>;
1145 #address-cells = <1>;
1146 #size-cells = <0>;
1147 status = "disabled";
1148 };
1149
93743d24
TR		 1150 lvts_mcu: thermal-sensor@11278000 {
1151 compatible = "mediatek,mt8192-lvts-mcu";
1152 reg = <0 0x11278000 0 0x1000>;
1153 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>;
1154 clocks = <&infracfg CLK_INFRA_THERM>;
1155 resets = <&infracfg MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST>;
1156 nvmem-cells = <&lvts_e_data1>;
1157 nvmem-cell-names = "lvts-calib-data-1";
1158 #thermal-sensor-cells = <1>;
1159 };
1160
53633a89
TR		 1161 efuse: efuse@11c10000 {
1162 compatible = "mediatek,mt8192-efuse", "mediatek,efuse";
1163 reg = <0 0x11c10000 0 0x1000>;
1164 #address-cells = <1>;
1165 #size-cells = <1>;
1166
1167 lvts_e_data1: data1@1c0 {
1168 reg = <0x1c0 0x58>;
1169 };
1170
1171 svs_calibration: calib@580 {
1172 reg = <0x580 0x68>;
1173 };
1174 };
1175
1176 i2c3: i2c@11cb0000 {
1177 compatible = "mediatek,mt8192-i2c";
1178 reg = <0 0x11cb0000 0 0x1000>,
1179 <0 0x10217300 0 0x80>;
1180 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
1181 clocks = <&imp_iic_wrap_e CLK_IMP_IIC_WRAP_E_I2C3>,
1182 <&infracfg CLK_INFRA_AP_DMA>;
1183 clock-names = "main", "dma";
1184 clock-div = <1>;
1185 #address-cells = <1>;
1186 #size-cells = <0>;
1187 status = "disabled";
1188 };
1189
1190 imp_iic_wrap_e: clock-controller@11cb1000 {
1191 compatible = "mediatek,mt8192-imp_iic_wrap_e";
1192 reg = <0 0x11cb1000 0 0x1000>;
1193 #clock-cells = <1>;
1194 };
1195
1196 i2c7: i2c@11d00000 {
1197 compatible = "mediatek,mt8192-i2c";
1198 reg = <0 0x11d00000 0 0x1000>,
1199 <0 0x10217600 0 0x180>;
1200 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1201 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>,
1202 <&infracfg CLK_INFRA_AP_DMA>;
1203 clock-names = "main", "dma";
1204 clock-div = <1>;
1205 #address-cells = <1>;
1206 #size-cells = <0>;
1207 status = "disabled";
1208 };
1209
1210 i2c8: i2c@11d01000 {
1211 compatible = "mediatek,mt8192-i2c";
1212 reg = <0 0x11d01000 0 0x1000>,
1213 <0 0x10217780 0 0x180>;
1214 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1215 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C8>,
1216 <&infracfg CLK_INFRA_AP_DMA>;
1217 clock-names = "main", "dma";
1218 clock-div = <1>;
1219 #address-cells = <1>;
1220 #size-cells = <0>;
1221 status = "disabled";
1222 };
1223
1224 i2c9: i2c@11d02000 {
1225 compatible = "mediatek,mt8192-i2c";
1226 reg = <0 0x11d02000 0 0x1000>,
1227 <0 0x10217900 0 0x180>;
1228 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>;
1229 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C9>,
1230 <&infracfg CLK_INFRA_AP_DMA>;
1231 clock-names = "main", "dma";
1232 clock-div = <1>;
1233 #address-cells = <1>;
1234 #size-cells = <0>;
1235 status = "disabled";
1236 };
1237
1238 imp_iic_wrap_s: clock-controller@11d03000 {
1239 compatible = "mediatek,mt8192-imp_iic_wrap_s";
1240 reg = <0 0x11d03000 0 0x1000>;
1241 #clock-cells = <1>;
1242 };
1243
1244 i2c1: i2c@11d20000 {
1245 compatible = "mediatek,mt8192-i2c";
1246 reg = <0 0x11d20000 0 0x1000>,
1247 <0 0x10217100 0 0x80>;
1248 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
1249 clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C1>,
1250 <&infracfg CLK_INFRA_AP_DMA>;
1251 clock-names = "main", "dma";
1252 clock-div = <1>;
1253 #address-cells = <1>;
1254 #size-cells = <0>;
1255 status = "disabled";
1256 };
1257
1258 i2c2: i2c@11d21000 {
1259 compatible = "mediatek,mt8192-i2c";
1260 reg = <0 0x11d21000 0 0x1000>,
1261 <0 0x10217180 0 0x180>;
1262 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
1263 clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C2>,
1264 <&infracfg CLK_INFRA_AP_DMA>;
1265 clock-names = "main", "dma";
1266 clock-div = <1>;
1267 #address-cells = <1>;
1268 #size-cells = <0>;
1269 status = "disabled";
1270 };
1271
1272 i2c4: i2c@11d22000 {
1273 compatible = "mediatek,mt8192-i2c";
1274 reg = <0 0x11d22000 0 0x1000>,
1275 <0 0x10217380 0 0x180>;
1276 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
1277 clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C4>,
1278 <&infracfg CLK_INFRA_AP_DMA>;
1279 clock-names = "main", "dma";
1280 clock-div = <1>;
1281 #address-cells = <1>;
1282 #size-cells = <0>;
1283 status = "disabled";
1284 };
1285
1286 imp_iic_wrap_ws: clock-controller@11d23000 {
1287 compatible = "mediatek,mt8192-imp_iic_wrap_ws";
1288 reg = <0 0x11d23000 0 0x1000>;
1289 #clock-cells = <1>;
1290 };
1291
1292 i2c5: i2c@11e00000 {
1293 compatible = "mediatek,mt8192-i2c";
1294 reg = <0 0x11e00000 0 0x1000>,
1295 <0 0x10217500 0 0x80>;
1296 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1297 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C5>,
1298 <&infracfg CLK_INFRA_AP_DMA>;
1299 clock-names = "main", "dma";
1300 clock-div = <1>;
1301 #address-cells = <1>;
1302 #size-cells = <0>;
1303 status = "disabled";
1304 };
1305
1306 imp_iic_wrap_w: clock-controller@11e01000 {
1307 compatible = "mediatek,mt8192-imp_iic_wrap_w";
1308 reg = <0 0x11e01000 0 0x1000>;
1309 #clock-cells = <1>;
1310 };
1311
1312 u3phy0: t-phy@11e40000 {
1313 compatible = "mediatek,mt8192-tphy",
1314 "mediatek,generic-tphy-v2";
1315 #address-cells = <1>;
1316 #size-cells = <1>;
1317 ranges = <0x0 0x0 0x11e40000 0x1000>;
1318
1319 u2port0: usb-phy@0 {
1320 reg = <0x0 0x700>;
1321 clocks = <&clk26m>;
1322 clock-names = "ref";
1323 #phy-cells = <1>;
1324 };
1325
1326 u3port0: usb-phy@700 {
1327 reg = <0x700 0x900>;
1328 clocks = <&clk26m>;
1329 clock-names = "ref";
1330 #phy-cells = <1>;
1331 };
1332 };
1333
1334 mipi_tx0: dsi-phy@11e50000 {
1335 compatible = "mediatek,mt8183-mipi-tx";
1336 reg = <0 0x11e50000 0 0x1000>;
1337 clocks = <&apmixedsys CLK_APMIXED_MIPID26M>;
1338 #clock-cells = <0>;
1339 #phy-cells = <0>;
1340 clock-output-names = "mipi_tx0_pll";
1341 status = "disabled";
1342 };
1343
1344 i2c0: i2c@11f00000 {
1345 compatible = "mediatek,mt8192-i2c";
1346 reg = <0 0x11f00000 0 0x1000>,
1347 <0 0x10217080 0 0x80>;
1348 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;
1349 clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C0>,
1350 <&infracfg CLK_INFRA_AP_DMA>;
1351 clock-names = "main", "dma";
1352 clock-div = <1>;
1353 #address-cells = <1>;
1354 #size-cells = <0>;
1355 status = "disabled";
1356 };
1357
1358 i2c6: i2c@11f01000 {
1359 compatible = "mediatek,mt8192-i2c";
1360 reg = <0 0x11f01000 0 0x1000>,
1361 <0 0x10217580 0 0x80>;
1362 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1363 clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C6>,
1364 <&infracfg CLK_INFRA_AP_DMA>;
1365 clock-names = "main", "dma";
1366 clock-div = <1>;
1367 #address-cells = <1>;
1368 #size-cells = <0>;
1369 status = "disabled";
1370 };
1371
1372 imp_iic_wrap_n: clock-controller@11f02000 {
1373 compatible = "mediatek,mt8192-imp_iic_wrap_n";
1374 reg = <0 0x11f02000 0 0x1000>;
1375 #clock-cells = <1>;
1376 };
1377
1378 msdc_top: clock-controller@11f10000 {
1379 compatible = "mediatek,mt8192-msdc_top";
1380 reg = <0 0x11f10000 0 0x1000>;
1381 #clock-cells = <1>;
1382 };
1383
1384 mmc0: mmc@11f60000 {
1385 compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
1386 reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0 0x1000>;
1387 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
1388 clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
1389 <&msdc_top CLK_MSDC_TOP_H_MST_0P>,
1390 <&msdc_top CLK_MSDC_TOP_SRC_0P>,
1391 <&msdc_top CLK_MSDC_TOP_P_CFG>,
1392 <&msdc_top CLK_MSDC_TOP_P_MSDC0>,
1393 <&msdc_top CLK_MSDC_TOP_AXI>,
1394 <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
1395 clock-names = "source", "hclk", "source_cg", "sys_cg",
1396 "pclk_cg", "axi_cg", "ahb_cg";
1397 status = "disabled";
1398 };
1399
1400 mmc1: mmc@11f70000 {
1401 compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
1402 reg = <0 0x11f70000 0 0x1000>, <0 0x11c70000 0 0x1000>;
1403 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>;
1404 clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
1405 <&msdc_top CLK_MSDC_TOP_H_MST_1P>,
1406 <&msdc_top CLK_MSDC_TOP_SRC_1P>,
1407 <&msdc_top CLK_MSDC_TOP_P_CFG>,
1408 <&msdc_top CLK_MSDC_TOP_P_MSDC1>,
1409 <&msdc_top CLK_MSDC_TOP_AXI>,
1410 <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
1411 clock-names = "source", "hclk", "source_cg", "sys_cg",
1412 "pclk_cg", "axi_cg", "ahb_cg";
1413 status = "disabled";
1414 };
1415
1416 gpu: gpu@13000000 {
1417 compatible = "mediatek,mt8192-mali", "arm,mali-valhall-jm";
1418 reg = <0 0x13000000 0 0x4000>;
1419 interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH 0>,
1420 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH 0>,
1421 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>;
1422 interrupt-names = "job", "mmu", "gpu";
1423
1424 clocks = <&apmixedsys CLK_APMIXED_MFGPLL>;
1425
1426 power-domains = <&spm MT8192_POWER_DOMAIN_MFG2>,
1427 <&spm MT8192_POWER_DOMAIN_MFG3>,
1428 <&spm MT8192_POWER_DOMAIN_MFG4>,
1429 <&spm MT8192_POWER_DOMAIN_MFG5>,
1430 <&spm MT8192_POWER_DOMAIN_MFG6>;
1431 power-domain-names = "core0", "core1", "core2", "core3", "core4";
1432
1433 operating-points-v2 = <&gpu_opp_table>;
1434
1435 status = "disabled";
1436 };
1437
1438 mfgcfg: clock-controller@13fbf000 {
1439 compatible = "mediatek,mt8192-mfgcfg";
1440 reg = <0 0x13fbf000 0 0x1000>;
1441 #clock-cells = <1>;
1442 };
1443
1444 mmsys: syscon@14000000 {
1445 compatible = "mediatek,mt8192-mmsys", "syscon";
1446 reg = <0 0x14000000 0 0x1000>;
1447 #clock-cells = <1>;
1448 #reset-cells = <1>;
1449 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
1450 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
1451 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1452 };
1453
1454 mutex: mutex@14001000 {
1455 compatible = "mediatek,mt8192-disp-mutex";
1456 reg = <0 0x14001000 0 0x1000>;
1457 interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
1458 clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
1459 mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
1460 <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
1461 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1462 };
1463
1464 smi_common: smi@14002000 {
1465 compatible = "mediatek,mt8192-smi-common";
1466 reg = <0 0x14002000 0 0x1000>;
1467 clocks = <&mmsys CLK_MM_SMI_COMMON>,
1468 <&mmsys CLK_MM_SMI_INFRA>,
1469 <&mmsys CLK_MM_SMI_GALS>,
1470 <&mmsys CLK_MM_SMI_GALS>;
1471 clock-names = "apb", "smi", "gals0", "gals1";
1472 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1473 };
1474
1475 larb0: larb@14003000 {
1476 compatible = "mediatek,mt8192-smi-larb";
1477 reg = <0 0x14003000 0 0x1000>;
1478 mediatek,larb-id = <0>;
1479 mediatek,smi = <&smi_common>;
1480 clocks = <&clk26m>, <&clk26m>;
1481 clock-names = "apb", "smi";
1482 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1483 };
1484
1485 larb1: larb@14004000 {
1486 compatible = "mediatek,mt8192-smi-larb";
1487 reg = <0 0x14004000 0 0x1000>;
1488 mediatek,larb-id = <1>;
1489 mediatek,smi = <&smi_common>;
1490 clocks = <&clk26m>, <&clk26m>;
1491 clock-names = "apb", "smi";
1492 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1493 };
1494
1495 ovl0: ovl@14005000 {
1496 compatible = "mediatek,mt8192-disp-ovl";
1497 reg = <0 0x14005000 0 0x1000>;
1498 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
1499 clocks = <&mmsys CLK_MM_DISP_OVL0>;
1500 iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
1501 <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
1502 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1503 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
1504 };
1505
1506 ovl_2l0: ovl@14006000 {
1507 compatible = "mediatek,mt8192-disp-ovl-2l";
1508 reg = <0 0x14006000 0 0x1000>;
1509 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>;
1510 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1511 clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
1512 iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
1513 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
1514 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
1515 };
1516
1517 rdma0: rdma@14007000 {
1518 compatible = "mediatek,mt8192-disp-rdma",
1519 "mediatek,mt8183-disp-rdma";
1520 reg = <0 0x14007000 0 0x1000>;
1521 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>;
1522 clocks = <&mmsys CLK_MM_DISP_RDMA0>;
1523 iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
1524 mediatek,rdma-fifo-size = <5120>;
1525 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1526 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
1527 };
1528
1529 color0: color@14009000 {
1530 compatible = "mediatek,mt8192-disp-color",
1531 "mediatek,mt8173-disp-color";
1532 reg = <0 0x14009000 0 0x1000>;
1533 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
1534 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1535 clocks = <&mmsys CLK_MM_DISP_COLOR0>;
1536 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
1537 };
1538
1539 ccorr0: ccorr@1400a000 {
1540 compatible = "mediatek,mt8192-disp-ccorr";
1541 reg = <0 0x1400a000 0 0x1000>;
1542 interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
1543 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1544 clocks = <&mmsys CLK_MM_DISP_CCORR0>;
1545 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
1546 };
1547
1548 aal0: aal@1400b000 {
1549 compatible = "mediatek,mt8192-disp-aal",
1550 "mediatek,mt8183-disp-aal";
1551 reg = <0 0x1400b000 0 0x1000>;
1552 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
1553 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1554 clocks = <&mmsys CLK_MM_DISP_AAL0>;
1555 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
1556 };
1557
1558 gamma0: gamma@1400c000 {
1559 compatible = "mediatek,mt8192-disp-gamma",
1560 "mediatek,mt8183-disp-gamma";
1561 reg = <0 0x1400c000 0 0x1000>;
1562 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
1563 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1564 clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
1565 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1566 };
1567
1568 postmask0: postmask@1400d000 {
1569 compatible = "mediatek,mt8192-disp-postmask";
1570 reg = <0 0x1400d000 0 0x1000>;
1571 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
1572 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1573 clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
1574 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
1575 };
1576
1577 dither0: dither@1400e000 {
1578 compatible = "mediatek,mt8192-disp-dither",
1579 "mediatek,mt8183-disp-dither";
1580 reg = <0 0x1400e000 0 0x1000>;
1581 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
1582 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1583 clocks = <&mmsys CLK_MM_DISP_DITHER0>;
1584 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
1585 };
1586
1587 dsi0: dsi@14010000 {
1588 compatible = "mediatek,mt8183-dsi";
1589 reg = <0 0x14010000 0 0x1000>;
1590 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
1591 clocks = <&mmsys CLK_MM_DSI0>,
1592 <&mmsys CLK_MM_DSI_DSI0>,
1593 <&mipi_tx0>;
1594 clock-names = "engine", "digital", "hs";
1595 phys = <&mipi_tx0>;
1596 phy-names = "dphy";
1597 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1598 resets = <&mmsys MT8192_MMSYS_SW0_RST_B_DISP_DSI0>;
1599 status = "disabled";
1600
1601 port {
1602 dsi_out: endpoint { };
1603 };
1604 };
1605
1606 ovl_2l2: ovl@14014000 {
1607 compatible = "mediatek,mt8192-disp-ovl-2l";
1608 reg = <0 0x14014000 0 0x1000>;
1609 interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>;
1610 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1611 clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
1612 iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
1613 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
1614 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
1615 };
1616
1617 rdma4: rdma@14015000 {
1618 compatible = "mediatek,mt8192-disp-rdma",
1619 "mediatek,mt8183-disp-rdma";
1620 reg = <0 0x14015000 0 0x1000>;
1621 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>;
1622 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1623 clocks = <&mmsys CLK_MM_DISP_RDMA4>;
1624 iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
1625 mediatek,rdma-fifo-size = <2048>;
1626 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
1627 };
1628
1629 dpi0: dpi@14016000 {
1630 compatible = "mediatek,mt8192-dpi";
1631 reg = <0 0x14016000 0 0x1000>;
1632 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>;
1633 clocks = <&mmsys CLK_MM_DPI_DPI0>,
1634 <&mmsys CLK_MM_DISP_DPI0>,
1635 <&apmixedsys CLK_APMIXED_TVDPLL>;
1636 clock-names = "pixel", "engine", "pll";
1637 status = "disabled";
1638 };
1639
1640 iommu0: m4u@1401d000 {
1641 compatible = "mediatek,mt8192-m4u";
1642 reg = <0 0x1401d000 0 0x1000>;
1643 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
1644 <&larb4>, <&larb5>, <&larb7>,
1645 <&larb9>, <&larb11>, <&larb13>,
1646 <&larb14>, <&larb16>, <&larb17>,
1647 <&larb18>, <&larb19>, <&larb20>;
1648 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>;
1649 clocks = <&mmsys CLK_MM_SMI_IOMMU>;
1650 clock-names = "bclk";
1651 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1652 #iommu-cells = <1>;
1653 };
1654
1655 imgsys: clock-controller@15020000 {
1656 compatible = "mediatek,mt8192-imgsys";
1657 reg = <0 0x15020000 0 0x1000>;
1658 #clock-cells = <1>;
1659 };
1660
1661 larb9: larb@1502e000 {
1662 compatible = "mediatek,mt8192-smi-larb";
1663 reg = <0 0x1502e000 0 0x1000>;
1664 mediatek,larb-id = <9>;
1665 mediatek,smi = <&smi_common>;
1666 clocks = <&imgsys CLK_IMG_LARB9>,
1667 <&imgsys CLK_IMG_LARB9>;
1668 clock-names = "apb", "smi";
1669 power-domains = <&spm MT8192_POWER_DOMAIN_ISP>;
1670 };
1671
1672 imgsys2: clock-controller@15820000 {
1673 compatible = "mediatek,mt8192-imgsys2";
1674 reg = <0 0x15820000 0 0x1000>;
1675 #clock-cells = <1>;
1676 };
1677
1678 larb11: larb@1582e000 {
1679 compatible = "mediatek,mt8192-smi-larb";
1680 reg = <0 0x1582e000 0 0x1000>;
1681 mediatek,larb-id = <11>;
1682 mediatek,smi = <&smi_common>;
1683 clocks = <&imgsys2 CLK_IMG2_LARB11>,
1684 <&imgsys2 CLK_IMG2_LARB11>;
1685 clock-names = "apb", "smi";
1686 power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
1687 };
1688
1689 vcodec_dec: video-codec@16000000 {
1690 compatible = "mediatek,mt8192-vcodec-dec";
1691 reg = <0 0x16000000 0 0x1000>;
1692 mediatek,scp = <&scp>;
1693 iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
1694 #address-cells = <2>;
1695 #size-cells = <2>;
1696 ranges = <0 0 0 0x16000000 0 0x26000>;
1697
1698 video-codec@10000 {
1699 compatible = "mediatek,mtk-vcodec-lat";
1700 reg = <0x0 0x10000 0 0x800>;
1701 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
1702 iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
1703 <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
1704 <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
1705 <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
1706 <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
1707 <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
1708 <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
1709 <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
1710 clocks = <&topckgen CLK_TOP_VDEC_SEL>,
1711 <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
1712 <&vdecsys_soc CLK_VDEC_SOC_LAT>,
1713 <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
1714 <&topckgen CLK_TOP_MAINPLL_D4>;
1715 clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
1716 assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
1717 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
1718 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
1719 };
1720
1721 video-codec@25000 {
1722 compatible = "mediatek,mtk-vcodec-core";
1723 reg = <0 0x25000 0 0x1000>;
1724 interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
1725 iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
1726 <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
1727 <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
1728 <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
1729 <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
1730 <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
1731 <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
1732 <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
1733 <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
1734 <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
1735 <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
1736 clocks = <&topckgen CLK_TOP_VDEC_SEL>,
1737 <&vdecsys CLK_VDEC_VDEC>,
1738 <&vdecsys CLK_VDEC_LAT>,
1739 <&vdecsys CLK_VDEC_LARB1>,
1740 <&topckgen CLK_TOP_MAINPLL_D4>;
1741 clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
1742 assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
1743 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
1744 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
1745 };
1746 };
1747
1748 larb5: larb@1600d000 {
1749 compatible = "mediatek,mt8192-smi-larb";
1750 reg = <0 0x1600d000 0 0x1000>;
1751 mediatek,larb-id = <5>;
1752 mediatek,smi = <&smi_common>;
1753 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
1754 <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
1755 clock-names = "apb", "smi";
1756 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
1757 };
1758
1759 vdecsys_soc: clock-controller@1600f000 {
1760 compatible = "mediatek,mt8192-vdecsys_soc";
1761 reg = <0 0x1600f000 0 0x1000>;
1762 #clock-cells = <1>;
1763 };
1764
1765 larb4: larb@1602e000 {
1766 compatible = "mediatek,mt8192-smi-larb";
1767 reg = <0 0x1602e000 0 0x1000>;
1768 mediatek,larb-id = <4>;
1769 mediatek,smi = <&smi_common>;
1770 clocks = <&vdecsys CLK_VDEC_SOC_LARB1>,
1771 <&vdecsys CLK_VDEC_SOC_LARB1>;
1772 clock-names = "apb", "smi";
1773 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
1774 };
1775
1776 vdecsys: clock-controller@1602f000 {
1777 compatible = "mediatek,mt8192-vdecsys";
1778 reg = <0 0x1602f000 0 0x1000>;
1779 #clock-cells = <1>;
1780 };
1781
1782 vencsys: clock-controller@17000000 {
1783 compatible = "mediatek,mt8192-vencsys";
1784 reg = <0 0x17000000 0 0x1000>;
1785 #clock-cells = <1>;
1786 };
1787
1788 larb7: larb@17010000 {
1789 compatible = "mediatek,mt8192-smi-larb";
1790 reg = <0 0x17010000 0 0x1000>;
1791 mediatek,larb-id = <7>;
1792 mediatek,smi = <&smi_common>;
1793 clocks = <&vencsys CLK_VENC_SET0_LARB>,
1794 <&vencsys CLK_VENC_SET1_VENC>;
1795 clock-names = "apb", "smi";
1796 power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
1797 };
1798
1799 vcodec_enc: vcodec@17020000 {
1800 compatible = "mediatek,mt8192-vcodec-enc";
1801 reg = <0 0x17020000 0 0x2000>;
1802 iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>,
1803 <&iommu0 M4U_PORT_L7_VENC_REC>,
1804 <&iommu0 M4U_PORT_L7_VENC_BSDMA>,
1805 <&iommu0 M4U_PORT_L7_VENC_SV_COMV>,
1806 <&iommu0 M4U_PORT_L7_VENC_RD_COMV>,
1807 <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>,
1808 <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>,
1809 <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>,
1810 <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>,
1811 <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>,
1812 <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>;
1813 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>;
1814 mediatek,scp = <&scp>;
1815 power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
1816 clocks = <&vencsys CLK_VENC_SET1_VENC>;
1817 clock-names = "venc-set1";
1818 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
1819 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
1820 };
1821
1822 camsys: clock-controller@1a000000 {
1823 compatible = "mediatek,mt8192-camsys";
1824 reg = <0 0x1a000000 0 0x1000>;
1825 #clock-cells = <1>;
1826 };
1827
1828 larb13: larb@1a001000 {
1829 compatible = "mediatek,mt8192-smi-larb";
1830 reg = <0 0x1a001000 0 0x1000>;
1831 mediatek,larb-id = <13>;
1832 mediatek,smi = <&smi_common>;
1833 clocks = <&camsys CLK_CAM_CAM>,
1834 <&camsys CLK_CAM_LARB13>;
1835 clock-names = "apb", "smi";
1836 power-domains = <&spm MT8192_POWER_DOMAIN_CAM>;
1837 };
1838
1839 larb14: larb@1a002000 {
1840 compatible = "mediatek,mt8192-smi-larb";
1841 reg = <0 0x1a002000 0 0x1000>;
1842 mediatek,larb-id = <14>;
1843 mediatek,smi = <&smi_common>;
1844 clocks = <&camsys CLK_CAM_CAM>,
1845 <&camsys CLK_CAM_LARB14>;
1846 clock-names = "apb", "smi";
1847 power-domains = <&spm MT8192_POWER_DOMAIN_CAM>;
1848 };
1849
1850 larb16: larb@1a00f000 {
1851 compatible = "mediatek,mt8192-smi-larb";
1852 reg = <0 0x1a00f000 0 0x1000>;
1853 mediatek,larb-id = <16>;
1854 mediatek,smi = <&smi_common>;
1855 clocks = <&camsys_rawa CLK_CAM_RAWA_CAM>,
1856 <&camsys_rawa CLK_CAM_RAWA_LARBX>;
1857 clock-names = "apb", "smi";
1858 power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWA>;
1859 };
1860
1861 larb17: larb@1a010000 {
1862 compatible = "mediatek,mt8192-smi-larb";
1863 reg = <0 0x1a010000 0 0x1000>;
1864 mediatek,larb-id = <17>;
1865 mediatek,smi = <&smi_common>;
1866 clocks = <&camsys_rawb CLK_CAM_RAWB_CAM>,
1867 <&camsys_rawb CLK_CAM_RAWB_LARBX>;
1868 clock-names = "apb", "smi";
1869 power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWB>;
1870 };
1871
1872 larb18: larb@1a011000 {
1873 compatible = "mediatek,mt8192-smi-larb";
1874 reg = <0 0x1a011000 0 0x1000>;
1875 mediatek,larb-id = <18>;
1876 mediatek,smi = <&smi_common>;
1877 clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>,
1878 <&camsys_rawc CLK_CAM_RAWC_CAM>;
1879 clock-names = "apb", "smi";
1880 power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWC>;
1881 };
1882
1883 camsys_rawa: clock-controller@1a04f000 {
1884 compatible = "mediatek,mt8192-camsys_rawa";
1885 reg = <0 0x1a04f000 0 0x1000>;
1886 #clock-cells = <1>;
1887 };
1888
1889 camsys_rawb: clock-controller@1a06f000 {
1890 compatible = "mediatek,mt8192-camsys_rawb";
1891 reg = <0 0x1a06f000 0 0x1000>;
1892 #clock-cells = <1>;
1893 };
1894
1895 camsys_rawc: clock-controller@1a08f000 {
1896 compatible = "mediatek,mt8192-camsys_rawc";
1897 reg = <0 0x1a08f000 0 0x1000>;
1898 #clock-cells = <1>;
1899 };
1900
1901 ipesys: clock-controller@1b000000 {
1902 compatible = "mediatek,mt8192-ipesys";
1903 reg = <0 0x1b000000 0 0x1000>;
1904 #clock-cells = <1>;
1905 };
1906
1907 larb20: larb@1b00f000 {
1908 compatible = "mediatek,mt8192-smi-larb";
1909 reg = <0 0x1b00f000 0 0x1000>;
1910 mediatek,larb-id = <20>;
1911 mediatek,smi = <&smi_common>;
1912 clocks = <&ipesys CLK_IPE_SMI_SUBCOM>,
1913 <&ipesys CLK_IPE_LARB20>;
1914 clock-names = "apb", "smi";
1915 power-domains = <&spm MT8192_POWER_DOMAIN_IPE>;
1916 };
1917
1918 larb19: larb@1b10f000 {
1919 compatible = "mediatek,mt8192-smi-larb";
1920 reg = <0 0x1b10f000 0 0x1000>;
1921 mediatek,larb-id = <19>;
1922 mediatek,smi = <&smi_common>;
1923 clocks = <&ipesys CLK_IPE_SMI_SUBCOM>,
1924 <&ipesys CLK_IPE_LARB19>;
1925 clock-names = "apb", "smi";
1926 power-domains = <&spm MT8192_POWER_DOMAIN_IPE>;
1927 };
1928
1929 mdpsys: clock-controller@1f000000 {
1930 compatible = "mediatek,mt8192-mdpsys";
1931 reg = <0 0x1f000000 0 0x1000>;
1932 #clock-cells = <1>;
1933 };
1934
1935 larb2: larb@1f002000 {
1936 compatible = "mediatek,mt8192-smi-larb";
1937 reg = <0 0x1f002000 0 0x1000>;
1938 mediatek,larb-id = <2>;
1939 mediatek,smi = <&smi_common>;
1940 clocks = <&mdpsys CLK_MDP_SMI0>,
1941 <&mdpsys CLK_MDP_SMI0>;
1942 clock-names = "apb", "smi";
1943 power-domains = <&spm MT8192_POWER_DOMAIN_MDP>;
1944 };
1945 };
93743d24
TR		 1946
1947 thermal_zones: thermal-zones {
1948 cpu0-thermal {
1949 polling-delay = <1000>;
1950 polling-delay-passive = <250>;
1951 thermal-sensors = <&lvts_mcu MT8192_MCU_LITTLE_CPU0>;
1952
1953 trips {
1954 cpu0_alert: trip-alert {
1955 temperature = <85000>;
1956 hysteresis = <2000>;
1957 type = "passive";
1958 };
1959
1960 cpu0_crit: trip-crit {
1961 temperature = <100000>;
1962 hysteresis = <2000>;
1963 type = "critical";
1964 };
1965 };
1966
1967 cooling-maps {
1968 map0 {
1969 trip = <&cpu0_alert>;
1970 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1971 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1972 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1973 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1974 };
1975 };
1976 };
1977
1978 cpu1-thermal {
1979 polling-delay = <1000>;
1980 polling-delay-passive = <250>;
1981 thermal-sensors = <&lvts_mcu MT8192_MCU_LITTLE_CPU1>;
1982
1983 trips {
1984 cpu1_alert: trip-alert {
1985 temperature = <85000>;
1986 hysteresis = <2000>;
1987 type = "passive";
1988 };
1989
1990 cpu1_crit: trip-crit {
1991 temperature = <100000>;
1992 hysteresis = <2000>;
1993 type = "critical";
1994 };
1995 };
1996
1997 cooling-maps {
1998 map0 {
1999 trip = <&cpu1_alert>;
2000 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2001 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2002 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2003 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2004 };
2005 };
2006 };
2007
2008 cpu2-thermal {
2009 polling-delay = <1000>;
2010 polling-delay-passive = <250>;
2011 thermal-sensors = <&lvts_mcu MT8192_MCU_LITTLE_CPU2>;
2012
2013 trips {
2014 cpu2_alert: trip-alert {
2015 temperature = <85000>;
2016 hysteresis = <2000>;
2017 type = "passive";
2018 };
2019
2020 cpu2_crit: trip-crit {
2021 temperature = <100000>;
2022 hysteresis = <2000>;
2023 type = "critical";
2024 };
2025 };
2026
2027 cooling-maps {
2028 map0 {
2029 trip = <&cpu2_alert>;
2030 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2031 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2032 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2033 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2034 };
2035 };
2036 };
2037
2038 cpu3-thermal {
2039 polling-delay = <1000>;
2040 polling-delay-passive = <250>;
2041 thermal-sensors = <&lvts_mcu MT8192_MCU_LITTLE_CPU3>;
2042
2043 trips {
2044 cpu3_alert: trip-alert {
2045 temperature = <85000>;
2046 hysteresis = <2000>;
2047 type = "passive";
2048 };
2049
2050 cpu3_crit: trip-crit {
2051 temperature = <100000>;
2052 hysteresis = <2000>;
2053 type = "critical";
2054 };
2055 };
2056
2057 cooling-maps {
2058 map0 {
2059 trip = <&cpu3_alert>;
2060 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2061 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2062 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2063 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2064 };
2065 };
2066 };
2067
2068 cpu4-thermal {
2069 polling-delay = <1000>;
2070 polling-delay-passive = <250>;
2071 thermal-sensors = <&lvts_mcu MT8192_MCU_BIG_CPU0>;
2072
2073 trips {
2074 cpu4_alert: trip-alert {
2075 temperature = <85000>;
2076 hysteresis = <2000>;
2077 type = "passive";
2078 };
2079
2080 cpu4_crit: trip-crit {
2081 temperature = <100000>;
2082 hysteresis = <2000>;
2083 type = "critical";
2084 };
2085 };
2086
2087 cooling-maps {
2088 map0 {
2089 trip = <&cpu4_alert>;
2090 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2091 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2092 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2093 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2094 };
2095 };
2096 };
2097
2098 cpu5-thermal {
2099 polling-delay = <1000>;
2100 polling-delay-passive = <250>;
2101 thermal-sensors = <&lvts_mcu MT8192_MCU_BIG_CPU1>;
2102
2103 trips {
2104 cpu5_alert: trip-alert {
2105 temperature = <85000>;
2106 hysteresis = <2000>;
2107 type = "passive";
2108 };
2109
2110 cpu5_crit: trip-crit {
2111 temperature = <100000>;
2112 hysteresis = <2000>;
2113 type = "critical";
2114 };
2115 };
2116
2117 cooling-maps {
2118 map0 {
2119 trip = <&cpu5_alert>;
2120 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2121 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2122 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2123 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2124 };
2125 };
2126 };
2127
2128 cpu6-thermal {
2129 polling-delay = <1000>;
2130 polling-delay-passive = <250>;
2131 thermal-sensors = <&lvts_mcu MT8192_MCU_BIG_CPU2>;
2132
2133 trips {
2134 cpu6_alert: trip-alert {
2135 temperature = <85000>;
2136 hysteresis = <2000>;
2137 type = "passive";
2138 };
2139
2140 cpu6_crit: trip-crit {
2141 temperature = <100000>;
2142 hysteresis = <2000>;
2143 type = "critical";
2144 };
2145 };
2146
2147 cooling-maps {
2148 map0 {
2149 trip = <&cpu6_alert>;
2150 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2151 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2152 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2153 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2154 };
2155 };
2156 };
2157
2158 cpu7-thermal {
2159 polling-delay = <1000>;
2160 polling-delay-passive = <250>;
2161 thermal-sensors = <&lvts_mcu MT8192_MCU_BIG_CPU3>;
2162
2163 trips {
2164 cpu7_alert: trip-alert {
2165 temperature = <85000>;
2166 hysteresis = <2000>;
2167 type = "passive";
2168 };
2169
2170 cpu7_crit: trip-crit {
2171 temperature = <100000>;
2172 hysteresis = <2000>;
2173 type = "critical";
2174 };
2175 };
2176
2177 cooling-maps {
2178 map0 {
2179 trip = <&cpu7_alert>;
2180 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2181 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2182 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2183 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2184 };
2185 };
2186 };
2187
2188 vpu0-thermal {
2189 polling-delay = <1000>;
2190 polling-delay-passive = <250>;
2191 thermal-sensors = <&lvts_ap MT8192_AP_VPU0>;
2192
2193 trips {
2194 vpu0_alert: trip-alert {
2195 temperature = <85000>;
2196 hysteresis = <2000>;
2197 type = "passive";
2198 };
2199
2200 vpu0_crit: trip-crit {
2201 temperature = <100000>;
2202 hysteresis = <2000>;
2203 type = "critical";
2204 };
2205 };
2206 };
2207
2208 vpu1-thermal {
2209 polling-delay = <1000>;
2210 polling-delay-passive = <250>;
2211 thermal-sensors = <&lvts_ap MT8192_AP_VPU1>;
2212
2213 trips {
2214 vpu1_alert: trip-alert {
2215 temperature = <85000>;
2216 hysteresis = <2000>;
2217 type = "passive";
2218 };
2219
2220 vpu1_crit: trip-crit {
2221 temperature = <100000>;
2222 hysteresis = <2000>;
2223 type = "critical";
2224 };
2225 };
2226 };
2227
2228 gpu0-thermal {
2229 polling-delay = <1000>;
2230 polling-delay-passive = <250>;
2231 thermal-sensors = <&lvts_ap MT8192_AP_GPU0>;
2232
2233 trips {
2234 gpu0_alert: trip-alert {
2235 temperature = <85000>;
2236 hysteresis = <2000>;
2237 type = "passive";
2238 };
2239
2240 gpu0_crit: trip-crit {
2241 temperature = <100000>;
2242 hysteresis = <2000>;
2243 type = "critical";
2244 };
2245 };
2246 };
2247
2248 gpu1-thermal {
2249 polling-delay = <1000>;
2250 polling-delay-passive = <250>;
2251 thermal-sensors = <&lvts_ap MT8192_AP_GPU1>;
2252
2253 trips {
2254 gpu1_alert: trip-alert {
2255 temperature = <85000>;
2256 hysteresis = <2000>;
2257 type = "passive";
2258 };
2259
2260 gpu1_crit: trip-crit {
2261 temperature = <100000>;
2262 hysteresis = <2000>;
2263 type = "critical";
2264 };
2265 };
2266 };
2267
2268 infra-thermal {
2269 polling-delay = <1000>;
2270 polling-delay-passive = <250>;
2271 thermal-sensors = <&lvts_ap MT8192_AP_INFRA>;
2272
2273 trips {
2274 infra_alert: trip-alert {
2275 temperature = <85000>;
2276 hysteresis = <2000>;
2277 type = "passive";
2278 };
2279
2280 infra_crit: trip-crit {
2281 temperature = <100000>;
2282 hysteresis = <2000>;
2283 type = "critical";
2284 };
2285 };
2286 };
2287
2288 cam-thermal {
2289 polling-delay = <1000>;
2290 polling-delay-passive = <250>;
2291 thermal-sensors = <&lvts_ap MT8192_AP_CAM>;
2292
2293 trips {
2294 cam_alert: trip-alert {
2295 temperature = <85000>;
2296 hysteresis = <2000>;
2297 type = "passive";
2298 };
2299
2300 cam_crit: trip-crit {
2301 temperature = <100000>;
2302 hysteresis = <2000>;
2303 type = "critical";
2304 };
2305 };
2306 };
2307
2308 md0-thermal {
2309 polling-delay = <1000>;
2310 polling-delay-passive = <250>;
2311 thermal-sensors = <&lvts_ap MT8192_AP_MD0>;
2312
2313 trips {
2314 md0_alert: trip-alert {
2315 temperature = <85000>;
2316 hysteresis = <2000>;
2317 type = "passive";
2318 };
2319
2320 md0_crit: trip-crit {
2321 temperature = <100000>;
2322 hysteresis = <2000>;
2323 type = "critical";
2324 };
2325 };
2326 };
2327
2328 md1-thermal {
2329 polling-delay = <1000>;
2330 polling-delay-passive = <250>;
2331 thermal-sensors = <&lvts_ap MT8192_AP_MD1>;
2332
2333 trips {
2334 md1_alert: trip-alert {
2335 temperature = <85000>;
2336 hysteresis = <2000>;
2337 type = "passive";
2338 };
2339
2340 md1_crit: trip-crit {
2341 temperature = <100000>;
2342 hysteresis = <2000>;
2343 type = "critical";
2344 };
2345 };
2346 };
2347
2348 md2-thermal {
2349 polling-delay = <1000>;
2350 polling-delay-passive = <250>;
2351 thermal-sensors = <&lvts_ap MT8192_AP_MD2>;
2352
2353 trips {
2354 md2_alert: trip-alert {
2355 temperature = <85000>;
2356 hysteresis = <2000>;
2357 type = "passive";
2358 };
2359
2360 md2_crit: trip-crit {
2361 temperature = <100000>;
2362 hysteresis = <2000>;
2363 type = "critical";
2364 };
2365 };
2366 };
2367 };
53633a89 2368};
"Das U-Boot" Source Tree