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53633a89 TR |
1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* | |
3 | * Unisoc SC9863A SoC DTS file | |
4 | * | |
5 | * Copyright (C) 2019, Unisoc Inc. | |
6 | */ | |
7 | ||
8 | #include <dt-bindings/clock/sprd,sc9863a-clk.h> | |
9 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
10 | #include "sharkl3.dtsi" | |
11 | ||
12 | / { | |
13 | cpus { | |
14 | #address-cells = <2>; | |
15 | #size-cells = <0>; | |
16 | ||
17 | cpu-map { | |
18 | cluster0 { | |
19 | core0 { | |
20 | cpu = <&CPU0>; | |
21 | }; | |
22 | core1 { | |
23 | cpu = <&CPU1>; | |
24 | }; | |
25 | core2 { | |
26 | cpu = <&CPU2>; | |
27 | }; | |
28 | core3 { | |
29 | cpu = <&CPU3>; | |
30 | }; | |
31 | core4 { | |
32 | cpu = <&CPU4>; | |
33 | }; | |
34 | core5 { | |
35 | cpu = <&CPU5>; | |
36 | }; | |
37 | core6 { | |
38 | cpu = <&CPU6>; | |
39 | }; | |
40 | core7 { | |
41 | cpu = <&CPU7>; | |
42 | }; | |
43 | }; | |
44 | }; | |
45 | ||
46 | CPU0: cpu@0 { | |
47 | device_type = "cpu"; | |
48 | compatible = "arm,cortex-a55"; | |
49 | reg = <0x0 0x0>; | |
50 | enable-method = "psci"; | |
51 | cpu-idle-states = <&CORE_PD>; | |
52 | }; | |
53 | ||
54 | CPU1: cpu@100 { | |
55 | device_type = "cpu"; | |
56 | compatible = "arm,cortex-a55"; | |
57 | reg = <0x0 0x100>; | |
58 | enable-method = "psci"; | |
59 | cpu-idle-states = <&CORE_PD>; | |
60 | }; | |
61 | ||
62 | CPU2: cpu@200 { | |
63 | device_type = "cpu"; | |
64 | compatible = "arm,cortex-a55"; | |
65 | reg = <0x0 0x200>; | |
66 | enable-method = "psci"; | |
67 | cpu-idle-states = <&CORE_PD>; | |
68 | }; | |
69 | ||
70 | CPU3: cpu@300 { | |
71 | device_type = "cpu"; | |
72 | compatible = "arm,cortex-a55"; | |
73 | reg = <0x0 0x300>; | |
74 | enable-method = "psci"; | |
75 | cpu-idle-states = <&CORE_PD>; | |
76 | }; | |
77 | ||
78 | CPU4: cpu@400 { | |
79 | device_type = "cpu"; | |
80 | compatible = "arm,cortex-a55"; | |
81 | reg = <0x0 0x400>; | |
82 | enable-method = "psci"; | |
83 | cpu-idle-states = <&CORE_PD>; | |
84 | }; | |
85 | ||
86 | CPU5: cpu@500 { | |
87 | device_type = "cpu"; | |
88 | compatible = "arm,cortex-a55"; | |
89 | reg = <0x0 0x500>; | |
90 | enable-method = "psci"; | |
91 | cpu-idle-states = <&CORE_PD>; | |
92 | }; | |
93 | ||
94 | CPU6: cpu@600 { | |
95 | device_type = "cpu"; | |
96 | compatible = "arm,cortex-a55"; | |
97 | reg = <0x0 0x600>; | |
98 | enable-method = "psci"; | |
99 | cpu-idle-states = <&CORE_PD>; | |
100 | }; | |
101 | ||
102 | CPU7: cpu@700 { | |
103 | device_type = "cpu"; | |
104 | compatible = "arm,cortex-a55"; | |
105 | reg = <0x0 0x700>; | |
106 | enable-method = "psci"; | |
107 | cpu-idle-states = <&CORE_PD>; | |
108 | }; | |
109 | }; | |
110 | ||
111 | idle-states { | |
112 | entry-method = "psci"; | |
113 | CORE_PD: core-pd { | |
114 | compatible = "arm,idle-state"; | |
115 | entry-latency-us = <4000>; | |
116 | exit-latency-us = <4000>; | |
117 | min-residency-us = <10000>; | |
118 | local-timer-stop; | |
119 | arm,psci-suspend-param = <0x00010000>; | |
120 | }; | |
121 | }; | |
122 | ||
123 | psci { | |
124 | compatible = "arm,psci-0.2"; | |
125 | method = "smc"; | |
126 | }; | |
127 | ||
128 | timer { | |
129 | compatible = "arm,armv8-timer"; | |
130 | interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, /* Physical Secure PPI */ | |
131 | <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, /* Physical Non-Secure PPI */ | |
132 | <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, /* Virtual PPI */ | |
133 | <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; /* Hipervisor PPI */ | |
134 | }; | |
135 | ||
136 | pmu { | |
137 | compatible = "arm,armv8-pmuv3"; | |
138 | interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, | |
139 | <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, | |
140 | <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, | |
141 | <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, | |
142 | <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, | |
143 | <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, | |
144 | <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, | |
145 | <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; | |
146 | }; | |
147 | ||
148 | soc { | |
149 | gic: interrupt-controller@14000000 { | |
150 | compatible = "arm,gic-v3"; | |
151 | #interrupt-cells = <3>; | |
152 | #address-cells = <2>; | |
153 | #size-cells = <2>; | |
154 | ranges; | |
155 | redistributor-stride = <0x0 0x20000>; /* 128KB stride */ | |
156 | #redistributor-regions = <1>; | |
157 | interrupt-controller; | |
158 | reg = <0x0 0x14000000 0 0x20000>, /* GICD */ | |
159 | <0x0 0x14040000 0 0x100000>; /* GICR */ | |
160 | interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; | |
161 | }; | |
162 | ||
163 | ap_clk: clock-controller@21500000 { | |
164 | compatible = "sprd,sc9863a-ap-clk"; | |
165 | reg = <0 0x21500000 0 0x1000>; | |
166 | clocks = <&ext_32k>, <&ext_26m>; | |
167 | clock-names = "ext-32k", "ext-26m"; | |
168 | #clock-cells = <1>; | |
169 | }; | |
170 | ||
171 | aon_clk: clock-controller@402d0000 { | |
172 | compatible = "sprd,sc9863a-aon-clk"; | |
173 | reg = <0 0x402d0000 0 0x1000>; | |
174 | clocks = <&ext_26m>, <&rco_100m>, | |
175 | <&ext_32k>, <&ext_4m>; | |
176 | clock-names = "ext-26m", "rco-100m", | |
177 | "ext-32k", "ext-4m"; | |
178 | #clock-cells = <1>; | |
179 | }; | |
180 | ||
181 | mm_clk: clock-controller@60900000 { | |
182 | compatible = "sprd,sc9863a-mm-clk"; | |
183 | reg = <0 0x60900000 0 0x1000>; | |
184 | #clock-cells = <1>; | |
185 | }; | |
186 | ||
187 | funnel@10001000 { | |
188 | compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; | |
189 | reg = <0 0x10001000 0 0x1000>; | |
190 | clocks = <&ext_26m>; | |
191 | clock-names = "apb_pclk"; | |
192 | ||
193 | out-ports { | |
194 | port { | |
195 | funnel_soc_out_port: endpoint { | |
196 | remote-endpoint = <&etb_in>; | |
197 | }; | |
198 | }; | |
199 | }; | |
200 | ||
201 | in-ports { | |
202 | port { | |
203 | funnel_soc_in_port: endpoint { | |
204 | remote-endpoint = | |
205 | <&funnel_ca55_out_port>; | |
206 | }; | |
207 | }; | |
208 | }; | |
209 | }; | |
210 | ||
211 | etb@10003000 { | |
212 | compatible = "arm,coresight-tmc", "arm,primecell"; | |
213 | reg = <0 0x10003000 0 0x1000>; | |
214 | clocks = <&ext_26m>; | |
215 | clock-names = "apb_pclk"; | |
216 | ||
217 | in-ports { | |
218 | port { | |
219 | etb_in: endpoint { | |
220 | remote-endpoint = | |
221 | <&funnel_soc_out_port>; | |
222 | }; | |
223 | }; | |
224 | }; | |
225 | }; | |
226 | ||
227 | funnel@12001000 { | |
228 | compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; | |
229 | reg = <0 0x12001000 0 0x1000>; | |
230 | clocks = <&ext_26m>; | |
231 | clock-names = "apb_pclk"; | |
232 | ||
233 | out-ports { | |
234 | port { | |
235 | funnel_little_out_port: endpoint { | |
236 | remote-endpoint = | |
237 | <&etf_little_in>; | |
238 | }; | |
239 | }; | |
240 | }; | |
241 | ||
242 | in-ports { | |
243 | #address-cells = <1>; | |
244 | #size-cells = <0>; | |
245 | ||
246 | port@0 { | |
247 | reg = <0>; | |
248 | funnel_little_in_port0: endpoint { | |
249 | remote-endpoint = <&etm0_out>; | |
250 | }; | |
251 | }; | |
252 | ||
253 | port@1 { | |
254 | reg = <1>; | |
255 | funnel_little_in_port1: endpoint { | |
256 | remote-endpoint = <&etm1_out>; | |
257 | }; | |
258 | }; | |
259 | ||
260 | port@2 { | |
261 | reg = <2>; | |
262 | funnel_little_in_port2: endpoint { | |
263 | remote-endpoint = <&etm2_out>; | |
264 | }; | |
265 | }; | |
266 | ||
267 | port@3 { | |
268 | reg = <3>; | |
269 | funnel_little_in_port3: endpoint { | |
270 | remote-endpoint = <&etm3_out>; | |
271 | }; | |
272 | }; | |
273 | }; | |
274 | }; | |
275 | ||
276 | etf@12002000 { | |
277 | compatible = "arm,coresight-tmc", "arm,primecell"; | |
278 | reg = <0 0x12002000 0 0x1000>; | |
279 | clocks = <&ext_26m>; | |
280 | clock-names = "apb_pclk"; | |
281 | ||
282 | out-ports { | |
283 | port { | |
284 | etf_little_out: endpoint { | |
285 | remote-endpoint = | |
286 | <&funnel_ca55_in_port0>; | |
287 | }; | |
288 | }; | |
289 | }; | |
290 | ||
291 | in-port { | |
292 | port { | |
293 | etf_little_in: endpoint { | |
294 | remote-endpoint = | |
295 | <&funnel_little_out_port>; | |
296 | }; | |
297 | }; | |
298 | }; | |
299 | }; | |
300 | ||
301 | etf@12003000 { | |
302 | compatible = "arm,coresight-tmc", "arm,primecell"; | |
303 | reg = <0 0x12003000 0 0x1000>; | |
304 | clocks = <&ext_26m>; | |
305 | clock-names = "apb_pclk"; | |
306 | ||
307 | out-ports { | |
308 | port { | |
309 | etf_big_out: endpoint { | |
310 | remote-endpoint = | |
311 | <&funnel_ca55_in_port1>; | |
312 | }; | |
313 | }; | |
314 | }; | |
315 | ||
316 | in-ports { | |
317 | port { | |
318 | etf_big_in: endpoint { | |
319 | remote-endpoint = | |
320 | <&funnel_big_out_port>; | |
321 | }; | |
322 | }; | |
323 | }; | |
324 | }; | |
325 | ||
326 | funnel@12004000 { | |
327 | compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; | |
328 | reg = <0 0x12004000 0 0x1000>; | |
329 | clocks = <&ext_26m>; | |
330 | clock-names = "apb_pclk"; | |
331 | ||
332 | out-ports { | |
333 | port { | |
334 | funnel_ca55_out_port: endpoint { | |
335 | remote-endpoint = | |
336 | <&funnel_soc_in_port>; | |
337 | }; | |
338 | }; | |
339 | }; | |
340 | ||
341 | in-ports { | |
342 | #address-cells = <1>; | |
343 | #size-cells = <0>; | |
344 | ||
345 | port@0 { | |
346 | reg = <0>; | |
347 | funnel_ca55_in_port0: endpoint { | |
348 | remote-endpoint = | |
349 | <&etf_little_out>; | |
350 | }; | |
351 | }; | |
352 | ||
353 | port@1 { | |
354 | reg = <1>; | |
355 | funnel_ca55_in_port1: endpoint { | |
356 | remote-endpoint = | |
357 | <&etf_big_out>; | |
358 | }; | |
359 | }; | |
360 | }; | |
361 | }; | |
362 | ||
363 | funnel@12005000 { | |
364 | compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; | |
365 | reg = <0 0x12005000 0 0x1000>; | |
366 | clocks = <&ext_26m>; | |
367 | clock-names = "apb_pclk"; | |
368 | ||
369 | out-ports { | |
370 | port { | |
371 | funnel_big_out_port: endpoint { | |
372 | remote-endpoint = | |
373 | <&etf_big_in>; | |
374 | }; | |
375 | }; | |
376 | }; | |
377 | ||
378 | in-ports { | |
379 | #address-cells = <1>; | |
380 | #size-cells = <0>; | |
381 | ||
382 | port@0 { | |
383 | reg = <0>; | |
384 | funnel_big_in_port0: endpoint { | |
385 | remote-endpoint = <&etm4_out>; | |
386 | }; | |
387 | }; | |
388 | ||
389 | port@1 { | |
390 | reg = <1>; | |
391 | funnel_big_in_port1: endpoint { | |
392 | remote-endpoint = <&etm5_out>; | |
393 | }; | |
394 | }; | |
395 | ||
396 | port@2 { | |
397 | reg = <2>; | |
398 | funnel_big_in_port2: endpoint { | |
399 | remote-endpoint = <&etm6_out>; | |
400 | }; | |
401 | }; | |
402 | ||
403 | port@3 { | |
404 | reg = <3>; | |
405 | funnel_big_in_port3: endpoint { | |
406 | remote-endpoint = <&etm7_out>; | |
407 | }; | |
408 | }; | |
409 | }; | |
410 | }; | |
411 | ||
412 | etm@13040000 { | |
413 | compatible = "arm,coresight-etm4x", "arm,primecell"; | |
414 | reg = <0 0x13040000 0 0x1000>; | |
415 | cpu = <&CPU0>; | |
416 | clocks = <&ext_26m>; | |
417 | clock-names = "apb_pclk"; | |
418 | ||
419 | out-ports { | |
420 | port { | |
421 | etm0_out: endpoint { | |
422 | remote-endpoint = | |
423 | <&funnel_little_in_port0>; | |
424 | }; | |
425 | }; | |
426 | }; | |
427 | }; | |
428 | ||
429 | etm@13140000 { | |
430 | compatible = "arm,coresight-etm4x", "arm,primecell"; | |
431 | reg = <0 0x13140000 0 0x1000>; | |
432 | cpu = <&CPU1>; | |
433 | clocks = <&ext_26m>; | |
434 | clock-names = "apb_pclk"; | |
435 | ||
436 | out-ports { | |
437 | port { | |
438 | etm1_out: endpoint { | |
439 | remote-endpoint = | |
440 | <&funnel_little_in_port1>; | |
441 | }; | |
442 | }; | |
443 | }; | |
444 | }; | |
445 | ||
446 | etm@13240000 { | |
447 | compatible = "arm,coresight-etm4x", "arm,primecell"; | |
448 | reg = <0 0x13240000 0 0x1000>; | |
449 | cpu = <&CPU2>; | |
450 | clocks = <&ext_26m>; | |
451 | clock-names = "apb_pclk"; | |
452 | ||
453 | out-ports { | |
454 | port { | |
455 | etm2_out: endpoint { | |
456 | remote-endpoint = | |
457 | <&funnel_little_in_port2>; | |
458 | }; | |
459 | }; | |
460 | }; | |
461 | }; | |
462 | ||
463 | etm@13340000 { | |
464 | compatible = "arm,coresight-etm4x", "arm,primecell"; | |
465 | reg = <0 0x13340000 0 0x1000>; | |
466 | cpu = <&CPU3>; | |
467 | clocks = <&ext_26m>; | |
468 | clock-names = "apb_pclk"; | |
469 | ||
470 | out-ports { | |
471 | port { | |
472 | etm3_out: endpoint { | |
473 | remote-endpoint = | |
474 | <&funnel_little_in_port3>; | |
475 | }; | |
476 | }; | |
477 | }; | |
478 | }; | |
479 | ||
480 | etm@13440000 { | |
481 | compatible = "arm,coresight-etm4x", "arm,primecell"; | |
482 | reg = <0 0x13440000 0 0x1000>; | |
483 | cpu = <&CPU4>; | |
484 | clocks = <&ext_26m>; | |
485 | clock-names = "apb_pclk"; | |
486 | ||
487 | out-ports { | |
488 | port { | |
489 | etm4_out: endpoint { | |
490 | remote-endpoint = | |
491 | <&funnel_big_in_port0>; | |
492 | }; | |
493 | }; | |
494 | }; | |
495 | }; | |
496 | ||
497 | etm@13540000 { | |
498 | compatible = "arm,coresight-etm4x", "arm,primecell"; | |
499 | reg = <0 0x13540000 0 0x1000>; | |
500 | cpu = <&CPU5>; | |
501 | clocks = <&ext_26m>; | |
502 | clock-names = "apb_pclk"; | |
503 | ||
504 | out-ports { | |
505 | port { | |
506 | etm5_out: endpoint { | |
507 | remote-endpoint = | |
508 | <&funnel_big_in_port1>; | |
509 | }; | |
510 | }; | |
511 | }; | |
512 | }; | |
513 | ||
514 | etm@13640000 { | |
515 | compatible = "arm,coresight-etm4x", "arm,primecell"; | |
516 | reg = <0 0x13640000 0 0x1000>; | |
517 | cpu = <&CPU6>; | |
518 | clocks = <&ext_26m>; | |
519 | clock-names = "apb_pclk"; | |
520 | ||
521 | out-ports { | |
522 | port { | |
523 | etm6_out: endpoint { | |
524 | remote-endpoint = | |
525 | <&funnel_big_in_port2>; | |
526 | }; | |
527 | }; | |
528 | }; | |
529 | }; | |
530 | ||
531 | etm@13740000 { | |
532 | compatible = "arm,coresight-etm4x", "arm,primecell"; | |
533 | reg = <0 0x13740000 0 0x1000>; | |
534 | cpu = <&CPU7>; | |
535 | clocks = <&ext_26m>; | |
536 | clock-names = "apb_pclk"; | |
537 | ||
538 | out-ports { | |
539 | port { | |
540 | etm7_out: endpoint { | |
541 | remote-endpoint = | |
542 | <&funnel_big_in_port3>; | |
543 | }; | |
544 | }; | |
545 | }; | |
546 | }; | |
547 | ||
548 | ap-ahb { | |
549 | compatible = "simple-bus"; | |
550 | #address-cells = <2>; | |
551 | #size-cells = <2>; | |
552 | ranges; | |
553 | ||
554 | sdio0: sdio@20300000 { | |
555 | compatible = "sprd,sdhci-r11"; | |
556 | reg = <0 0x20300000 0 0x1000>; | |
557 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; | |
558 | ||
559 | clock-names = "sdio", "enable"; | |
560 | clocks = <&aon_clk CLK_SDIO0_2X>, | |
561 | <&apahb_gate CLK_SDIO0_EB>; | |
562 | assigned-clocks = <&aon_clk CLK_SDIO0_2X>; | |
563 | assigned-clock-parents = <&rpll CLK_RPLL_390M>; | |
564 | ||
565 | bus-width = <4>; | |
566 | no-sdio; | |
567 | no-mmc; | |
568 | }; | |
569 | ||
570 | sdio3: sdio@20600000 { | |
571 | compatible = "sprd,sdhci-r11"; | |
572 | reg = <0 0x20600000 0 0x1000>; | |
573 | interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; | |
574 | ||
575 | clock-names = "sdio", "enable"; | |
576 | clocks = <&aon_clk CLK_EMMC_2X>, | |
577 | <&apahb_gate CLK_EMMC_EB>; | |
578 | assigned-clocks = <&aon_clk CLK_EMMC_2X>; | |
579 | assigned-clock-parents = <&rpll CLK_RPLL_390M>; | |
580 | ||
581 | bus-width = <8>; | |
582 | non-removable; | |
583 | no-sdio; | |
584 | no-sd; | |
585 | cap-mmc-hw-reset; | |
586 | }; | |
587 | }; | |
588 | }; | |
589 | }; |